1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2/*
  3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2023 Intel Corporation
  5 */
  6#include <linux/module.h>
  7#include <linux/stringify.h>
  8#include "iwl-config.h"
  9#include "iwl-prph.h"
 10#include "fw/api/txq.h"
 11
 12/* Highest firmware API version supported */
 13#define IWL_SC_UCODE_API_MAX	86
 14
 15/* Lowest firmware API version supported */
 16#define IWL_SC_UCODE_API_MIN	82
 17
 18/* NVM versions */
 19#define IWL_SC_NVM_VERSION		0x0a1d
 20
 21/* Memory offsets and lengths */
 22#define IWL_SC_DCCM_OFFSET		0x800000 /* LMAC1 */
 23#define IWL_SC_DCCM_LEN			0x10000 /* LMAC1 */
 24#define IWL_SC_DCCM2_OFFSET		0x880000
 25#define IWL_SC_DCCM2_LEN		0x8000
 26#define IWL_SC_SMEM_OFFSET		0x400000
 27#define IWL_SC_SMEM_LEN			0xD0000
 28
 29#define IWL_SC_A_FM_B_FW_PRE		"iwlwifi-sc-a0-fm-b0"
 30#define IWL_SC_A_FM_C_FW_PRE		"iwlwifi-sc-a0-fm-c0"
 31#define IWL_SC_A_HR_A_FW_PRE		"iwlwifi-sc-a0-hr-b0"
 32#define IWL_SC_A_HR_B_FW_PRE		"iwlwifi-sc-a0-hr-b0"
 33#define IWL_SC_A_GF_A_FW_PRE		"iwlwifi-sc-a0-gf-a0"
 34#define IWL_SC_A_GF4_A_FW_PRE		"iwlwifi-sc-a0-gf4-a0"
 35#define IWL_SC_A_WH_A_FW_PRE		"iwlwifi-sc-a0-wh-a0"
 36
 37#define IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(api) \
 38	IWL_SC_A_FM_B_FW_PRE "-" __stringify(api) ".ucode"
 39#define IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(api) \
 40	IWL_SC_A_FM_C_FW_PRE "-" __stringify(api) ".ucode"
 41#define IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(api) \
 42	IWL_SC_A_HR_A_FW_PRE "-" __stringify(api) ".ucode"
 43#define IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(api) \
 44	IWL_SC_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
 45#define IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(api) \
 46	IWL_SC_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
 47#define IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(api) \
 48	IWL_SC_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
 49#define IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(api) \
 50	IWL_SC_A_WH_A_FW_PRE "-" __stringify(api) ".ucode"
 51
 52static const struct iwl_base_params iwl_sc_base_params = {
 53	.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 54	.num_of_queues = 512,
 55	.max_tfd_queue_size = 65536,
 56	.shadow_ram_support = true,
 57	.led_compensation = 57,
 58	.wd_timeout = IWL_LONG_WD_TIMEOUT,
 59	.max_event_log_size = 512,
 60	.shadow_reg_enable = true,
 61	.pcie_l1_allowed = true,
 62};
 63
 64#define IWL_DEVICE_BZ_COMMON						\
 65	.ucode_api_max = IWL_SC_UCODE_API_MAX,			\
 66	.ucode_api_min = IWL_SC_UCODE_API_MIN,			\
 67	.led_mode = IWL_LED_RF_STATE,					\
 68	.nvm_hw_section_num = 10,					\
 69	.non_shared_ant = ANT_B,					\
 70	.dccm_offset = IWL_SC_DCCM_OFFSET,				\
 71	.dccm_len = IWL_SC_DCCM_LEN,					\
 72	.dccm2_offset = IWL_SC_DCCM2_OFFSET,				\
 73	.dccm2_len = IWL_SC_DCCM2_LEN,				\
 74	.smem_offset = IWL_SC_SMEM_OFFSET,				\
 75	.smem_len = IWL_SC_SMEM_LEN,					\
 76	.apmg_not_supported = true,					\
 77	.trans.mq_rx_supported = true,					\
 78	.vht_mu_mimo_supported = true,					\
 79	.mac_addr_from_csr = 0x30,					\
 80	.nvm_ver = IWL_SC_NVM_VERSION,				\
 81	.trans.rf_id = true,						\
 82	.trans.gen2 = true,						\
 83	.nvm_type = IWL_NVM_EXT,					\
 84	.dbgc_supported = true,						\
 85	.min_umac_error_event_table = 0xD0000,				\
 86	.d3_debug_data_base_addr = 0x401000,				\
 87	.d3_debug_data_length = 60 * 1024,				\
 88	.mon_smem_regs = {						\
 89		.write_ptr = {						\
 90			.addr = LDBG_M2S_BUF_WPTR,			\
 91			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,		\
 92	},								\
 93		.cycle_cnt = {						\
 94			.addr = LDBG_M2S_BUF_WRAP_CNT,			\
 95			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,		\
 96		},							\
 97	},								\
 98	.trans.umac_prph_offset = 0x300000,				\
 99	.trans.device_family = IWL_DEVICE_FAMILY_SC,			\
100	.trans.base_params = &iwl_sc_base_params,			\
101	.min_txq_size = 128,						\
102	.gp2_reg_addr = 0xd02c68,					\
103	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,			\
104	.mon_dram_regs = {						\
105		.write_ptr = {						\
106			.addr = DBGC_CUR_DBGBUF_STATUS,			\
107			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,	\
108		},							\
109		.cycle_cnt = {						\
110			.addr = DBGC_DBGBUF_WRAP_AROUND,		\
111			.mask = 0xffffffff,				\
112		},							\
113		.cur_frag = {						\
114			.addr = DBGC_CUR_DBGBUF_STATUS,			\
115			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,		\
116		},							\
117	},								\
118	.mon_dbgi_regs = {						\
119		.write_ptr = {						\
120			.addr = DBGI_SRAM_FIFO_POINTERS,		\
121			.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,	\
122		},							\
123	}
124
125#define IWL_DEVICE_SC							\
126	IWL_DEVICE_BZ_COMMON,						\
127	.ht_params = &iwl_22000_ht_params
128
129/*
130 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an
131 * A-MPDU, with additional overhead to account for processing time.
132 */
133#define IWL_NUM_RBDS_SC_EHT		(512 * 16)
134
135const struct iwl_cfg_trans_params iwl_sc_trans_cfg = {
136	.device_family = IWL_DEVICE_FAMILY_SC,
137	.base_params = &iwl_sc_base_params,
138	.mq_rx_supported = true,
139	.rf_id = true,
140	.gen2 = true,
141	.integrated = true,
142	.umac_prph_offset = 0x300000,
143	.xtal_latency = 12000,
144	.low_latency_xtal = true,
145	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
146};
147
148const char iwl_sc_name[] = "Intel(R) TBD Sc device";
149
150const struct iwl_cfg iwl_cfg_sc = {
151	.fw_name_mac = "sc",
152	.uhb_supported = true,
153	IWL_DEVICE_SC,
154	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
155	.num_rbds = IWL_NUM_RBDS_SC_EHT,
156};
157
158MODULE_FIRMWARE(IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
159MODULE_FIRMWARE(IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
160MODULE_FIRMWARE(IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
161MODULE_FIRMWARE(IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
162MODULE_FIRMWARE(IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
163MODULE_FIRMWARE(IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
164MODULE_FIRMWARE(IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));