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1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH_H
18#define ATH_H
19
20#include <linux/etherdevice.h>
21#include <linux/skbuff.h>
22#include <linux/if_ether.h>
23#include <linux/spinlock.h>
24#include <net/mac80211.h>
25
26/*
27 * The key cache is used for h/w cipher state and also for
28 * tracking station state such as the current tx antenna.
29 * We also setup a mapping table between key cache slot indices
30 * and station state to short-circuit node lookups on rx.
31 * Different parts have different size key caches. We handle
32 * up to ATH_KEYMAX entries (could dynamically allocate state).
33 */
34#define ATH_KEYMAX 128 /* max key cache size we handle */
35
36struct ath_ani {
37 bool caldone;
38 unsigned int longcal_timer;
39 unsigned int shortcal_timer;
40 unsigned int resetcal_timer;
41 unsigned int checkani_timer;
42 struct timer_list timer;
43};
44
45struct ath_cycle_counters {
46 u32 cycles;
47 u32 rx_busy;
48 u32 rx_frame;
49 u32 tx_frame;
50};
51
52enum ath_device_state {
53 ATH_HW_UNAVAILABLE,
54 ATH_HW_INITIALIZED,
55};
56
57enum ath_op_flags {
58 ATH_OP_INVALID,
59 ATH_OP_BEACONS,
60 ATH_OP_ANI_RUN,
61 ATH_OP_PRIM_STA_VIF,
62 ATH_OP_HW_RESET,
63 ATH_OP_SCANNING,
64 ATH_OP_MULTI_CHANNEL,
65 ATH_OP_WOW_ENABLED,
66};
67
68enum ath_bus_type {
69 ATH_PCI,
70 ATH_AHB,
71 ATH_USB,
72};
73
74struct reg_dmn_pair_mapping {
75 u16 reg_domain;
76 u16 reg_5ghz_ctl;
77 u16 reg_2ghz_ctl;
78};
79
80struct ath_regulatory {
81 char alpha2[2];
82 enum nl80211_dfs_regions region;
83 u16 country_code;
84 u16 max_power_level;
85 u16 current_rd;
86 int16_t power_limit;
87 struct reg_dmn_pair_mapping *regpair;
88};
89
90enum ath_crypt_caps {
91 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
92 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
93};
94
95struct ath_keyval {
96 u8 kv_type;
97 u8 kv_pad;
98 u16 kv_len;
99 struct_group(kv_values,
100 u8 kv_val[16]; /* TK */
101 u8 kv_mic[8]; /* Michael MIC key */
102 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
103 * supports both MIC keys in the same key cache entry;
104 * in that case, kv_mic is the RX key) */
105 );
106};
107
108enum ath_cipher {
109 ATH_CIPHER_WEP = 0,
110 ATH_CIPHER_AES_OCB = 1,
111 ATH_CIPHER_AES_CCM = 2,
112 ATH_CIPHER_CKIP = 3,
113 ATH_CIPHER_TKIP = 4,
114 ATH_CIPHER_CLR = 5,
115 ATH_CIPHER_MIC = 127
116};
117
118/**
119 * struct ath_ops - Register read/write operations
120 *
121 * @read: Register read
122 * @multi_read: Multiple register read
123 * @write: Register write
124 * @enable_write_buffer: Enable multiple register writes
125 * @write_flush: flush buffered register writes and disable buffering
126 */
127struct ath_ops {
128 unsigned int (*read)(void *, u32 reg_offset);
129 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
130 void (*write)(void *, u32 val, u32 reg_offset);
131 void (*enable_write_buffer)(void *);
132 void (*write_flush) (void *);
133 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
134 void (*enable_rmw_buffer)(void *);
135 void (*rmw_flush) (void *);
136
137};
138
139struct ath_common;
140struct ath_bus_ops;
141
142struct ath_ps_ops {
143 void (*wakeup)(struct ath_common *common);
144 void (*restore)(struct ath_common *common);
145};
146
147struct ath_common {
148 void *ah;
149 void *priv;
150 struct ieee80211_hw *hw;
151 int debug_mask;
152 enum ath_device_state state;
153 unsigned long op_flags;
154
155 struct ath_ani ani;
156
157 u16 cachelsz;
158 u16 curaid;
159 u8 macaddr[ETH_ALEN];
160 u8 curbssid[ETH_ALEN] __aligned(2);
161 u8 bssidmask[ETH_ALEN];
162
163 u32 rx_bufsize;
164
165 u32 keymax;
166 DECLARE_BITMAP(keymap, ATH_KEYMAX);
167 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
168 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
169 enum ath_crypt_caps crypt_caps;
170
171 unsigned int clockrate;
172
173 spinlock_t cc_lock;
174 struct ath_cycle_counters cc_ani;
175 struct ath_cycle_counters cc_survey;
176
177 struct ath_regulatory regulatory;
178 struct ath_regulatory reg_world_copy;
179 const struct ath_ops *ops;
180 const struct ath_bus_ops *bus_ops;
181 const struct ath_ps_ops *ps_ops;
182
183 bool btcoex_enabled;
184 bool disable_ani;
185 bool bt_ant_diversity;
186
187 int last_rssi;
188 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
189};
190
191static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common)
192{
193 return common->ps_ops;
194}
195
196struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
197 u32 len,
198 gfp_t gfp_mask);
199bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
200
201void ath_hw_setbssidmask(struct ath_common *common);
202void ath_key_delete(struct ath_common *common, u8 hw_key_idx);
203int ath_key_config(struct ath_common *common,
204 struct ieee80211_vif *vif,
205 struct ieee80211_sta *sta,
206 struct ieee80211_key_conf *key);
207bool ath_hw_keyreset(struct ath_common *common, u16 entry);
208bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac);
209void ath_hw_cycle_counters_update(struct ath_common *common);
210int32_t ath_hw_get_listen_time(struct ath_common *common);
211
212__printf(3, 4)
213void ath_printk(const char *level, const struct ath_common *common,
214 const char *fmt, ...);
215
216#define ath_emerg(common, fmt, ...) \
217 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
218#define ath_alert(common, fmt, ...) \
219 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
220#define ath_crit(common, fmt, ...) \
221 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
222#define ath_err(common, fmt, ...) \
223 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
224#define ath_warn(common, fmt, ...) \
225 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
226#define ath_notice(common, fmt, ...) \
227 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
228#define ath_info(common, fmt, ...) \
229 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
230
231/**
232 * enum ath_debug_level - atheros wireless debug level
233 *
234 * @ATH_DBG_RESET: reset processing
235 * @ATH_DBG_QUEUE: hardware queue management
236 * @ATH_DBG_EEPROM: eeprom processing
237 * @ATH_DBG_CALIBRATE: periodic calibration
238 * @ATH_DBG_INTERRUPT: interrupt processing
239 * @ATH_DBG_REGULATORY: regulatory processing
240 * @ATH_DBG_ANI: adaptive noise immunitive processing
241 * @ATH_DBG_XMIT: basic xmit operation
242 * @ATH_DBG_BEACON: beacon handling
243 * @ATH_DBG_CONFIG: configuration of the hardware
244 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
245 * @ATH_DBG_PS: power save processing
246 * @ATH_DBG_HWTIMER: hardware timer handling
247 * @ATH_DBG_BTCOEX: bluetooth coexistance
248 * @ATH_DBG_BSTUCK: stuck beacons
249 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
250 * used exclusively for WLAN-BT coexistence starting from
251 * AR9462.
252 * @ATH_DBG_DFS: radar datection
253 * @ATH_DBG_WOW: Wake on Wireless
254 * @ATH_DBG_DYNACK: dynack handling
255 * @ATH_DBG_SPECTRAL_SCAN: FFT spectral scan
256 * @ATH_DBG_ANY: enable all debugging
257 *
258 * The debug level is used to control the amount and type of debugging output
259 * we want to see. Each driver has its own method for enabling debugging and
260 * modifying debug level states -- but this is typically done through a
261 * module parameter 'debug' along with a respective 'debug' debugfs file
262 * entry.
263 */
264enum ATH_DEBUG {
265 ATH_DBG_RESET = 0x00000001,
266 ATH_DBG_QUEUE = 0x00000002,
267 ATH_DBG_EEPROM = 0x00000004,
268 ATH_DBG_CALIBRATE = 0x00000008,
269 ATH_DBG_INTERRUPT = 0x00000010,
270 ATH_DBG_REGULATORY = 0x00000020,
271 ATH_DBG_ANI = 0x00000040,
272 ATH_DBG_XMIT = 0x00000080,
273 ATH_DBG_BEACON = 0x00000100,
274 ATH_DBG_CONFIG = 0x00000200,
275 ATH_DBG_FATAL = 0x00000400,
276 ATH_DBG_PS = 0x00000800,
277 ATH_DBG_BTCOEX = 0x00001000,
278 ATH_DBG_WMI = 0x00002000,
279 ATH_DBG_BSTUCK = 0x00004000,
280 ATH_DBG_MCI = 0x00008000,
281 ATH_DBG_DFS = 0x00010000,
282 ATH_DBG_WOW = 0x00020000,
283 ATH_DBG_CHAN_CTX = 0x00040000,
284 ATH_DBG_DYNACK = 0x00080000,
285 ATH_DBG_SPECTRAL_SCAN = 0x00100000,
286 ATH_DBG_ANY = 0xffffffff
287};
288
289#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
290#define ATH_DBG_MAX_LEN 512
291
292#ifdef CONFIG_ATH_DEBUG
293
294#define ath_dbg(common, dbg_mask, fmt, ...) \
295do { \
296 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
297 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
298} while (0)
299
300#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
301#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
302
303#else
304
305static inline __attribute__ ((format (printf, 3, 4)))
306void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
307 const char *fmt, ...)
308{
309}
310#define ath_dbg(common, dbg_mask, fmt, ...) \
311 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
312
313#define ATH_DBG_WARN(foo, arg...) do {} while (0)
314#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
315 int __ret_warn_once = !!(foo); \
316 unlikely(__ret_warn_once); \
317})
318
319#endif /* CONFIG_ATH_DEBUG */
320
321/** Returns string describing opmode, or NULL if unknown mode. */
322#ifdef CONFIG_ATH_DEBUG
323const char *ath_opmode_to_string(enum nl80211_iftype opmode);
324#else
325static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
326{
327 return "UNKNOWN";
328}
329#endif
330
331extern const char *ath_bus_type_strings[];
332static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)
333{
334 return ath_bus_type_strings[bustype];
335}
336
337#endif /* ATH_H */
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH_H
18#define ATH_H
19
20#include <linux/etherdevice.h>
21#include <linux/skbuff.h>
22#include <linux/if_ether.h>
23#include <linux/spinlock.h>
24#include <net/mac80211.h>
25
26/*
27 * The key cache is used for h/w cipher state and also for
28 * tracking station state such as the current tx antenna.
29 * We also setup a mapping table between key cache slot indices
30 * and station state to short-circuit node lookups on rx.
31 * Different parts have different size key caches. We handle
32 * up to ATH_KEYMAX entries (could dynamically allocate state).
33 */
34#define ATH_KEYMAX 128 /* max key cache size we handle */
35
36static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
37
38struct ath_ani {
39 bool caldone;
40 unsigned int longcal_timer;
41 unsigned int shortcal_timer;
42 unsigned int resetcal_timer;
43 unsigned int checkani_timer;
44 struct timer_list timer;
45};
46
47struct ath_cycle_counters {
48 u32 cycles;
49 u32 rx_busy;
50 u32 rx_frame;
51 u32 tx_frame;
52};
53
54enum ath_device_state {
55 ATH_HW_UNAVAILABLE,
56 ATH_HW_INITIALIZED,
57};
58
59enum ath_op_flags {
60 ATH_OP_INVALID,
61 ATH_OP_BEACONS,
62 ATH_OP_ANI_RUN,
63 ATH_OP_PRIM_STA_VIF,
64 ATH_OP_HW_RESET,
65 ATH_OP_SCANNING,
66};
67
68enum ath_bus_type {
69 ATH_PCI,
70 ATH_AHB,
71 ATH_USB,
72};
73
74struct reg_dmn_pair_mapping {
75 u16 reg_domain;
76 u16 reg_5ghz_ctl;
77 u16 reg_2ghz_ctl;
78};
79
80struct ath_regulatory {
81 char alpha2[2];
82 u16 country_code;
83 u16 max_power_level;
84 u16 current_rd;
85 int16_t power_limit;
86 struct reg_dmn_pair_mapping *regpair;
87};
88
89enum ath_crypt_caps {
90 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
91 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
92};
93
94struct ath_keyval {
95 u8 kv_type;
96 u8 kv_pad;
97 u16 kv_len;
98 u8 kv_val[16]; /* TK */
99 u8 kv_mic[8]; /* Michael MIC key */
100 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
101 * supports both MIC keys in the same key cache entry;
102 * in that case, kv_mic is the RX key) */
103};
104
105enum ath_cipher {
106 ATH_CIPHER_WEP = 0,
107 ATH_CIPHER_AES_OCB = 1,
108 ATH_CIPHER_AES_CCM = 2,
109 ATH_CIPHER_CKIP = 3,
110 ATH_CIPHER_TKIP = 4,
111 ATH_CIPHER_CLR = 5,
112 ATH_CIPHER_MIC = 127
113};
114
115/**
116 * struct ath_ops - Register read/write operations
117 *
118 * @read: Register read
119 * @multi_read: Multiple register read
120 * @write: Register write
121 * @enable_write_buffer: Enable multiple register writes
122 * @write_flush: flush buffered register writes and disable buffering
123 */
124struct ath_ops {
125 unsigned int (*read)(void *, u32 reg_offset);
126 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
127 void (*write)(void *, u32 val, u32 reg_offset);
128 void (*enable_write_buffer)(void *);
129 void (*write_flush) (void *);
130 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
131};
132
133struct ath_common;
134struct ath_bus_ops;
135
136struct ath_common {
137 void *ah;
138 void *priv;
139 struct ieee80211_hw *hw;
140 int debug_mask;
141 enum ath_device_state state;
142 unsigned long op_flags;
143
144 struct ath_ani ani;
145
146 u16 cachelsz;
147 u16 curaid;
148 u8 macaddr[ETH_ALEN];
149 u8 curbssid[ETH_ALEN];
150 u8 bssidmask[ETH_ALEN];
151
152 u32 rx_bufsize;
153
154 u32 keymax;
155 DECLARE_BITMAP(keymap, ATH_KEYMAX);
156 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
157 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
158 enum ath_crypt_caps crypt_caps;
159
160 unsigned int clockrate;
161
162 spinlock_t cc_lock;
163 struct ath_cycle_counters cc_ani;
164 struct ath_cycle_counters cc_survey;
165
166 struct ath_regulatory regulatory;
167 struct ath_regulatory reg_world_copy;
168 const struct ath_ops *ops;
169 const struct ath_bus_ops *bus_ops;
170
171 bool btcoex_enabled;
172 bool disable_ani;
173 bool bt_ant_diversity;
174
175 int last_rssi;
176 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
177};
178
179struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
180 u32 len,
181 gfp_t gfp_mask);
182bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
183
184void ath_hw_setbssidmask(struct ath_common *common);
185void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
186int ath_key_config(struct ath_common *common,
187 struct ieee80211_vif *vif,
188 struct ieee80211_sta *sta,
189 struct ieee80211_key_conf *key);
190bool ath_hw_keyreset(struct ath_common *common, u16 entry);
191void ath_hw_cycle_counters_update(struct ath_common *common);
192int32_t ath_hw_get_listen_time(struct ath_common *common);
193
194__printf(3, 4)
195void ath_printk(const char *level, const struct ath_common *common,
196 const char *fmt, ...);
197
198#define ath_emerg(common, fmt, ...) \
199 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
200#define ath_alert(common, fmt, ...) \
201 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
202#define ath_crit(common, fmt, ...) \
203 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
204#define ath_err(common, fmt, ...) \
205 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
206#define ath_warn(common, fmt, ...) \
207 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
208#define ath_notice(common, fmt, ...) \
209 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
210#define ath_info(common, fmt, ...) \
211 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
212
213/**
214 * enum ath_debug_level - atheros wireless debug level
215 *
216 * @ATH_DBG_RESET: reset processing
217 * @ATH_DBG_QUEUE: hardware queue management
218 * @ATH_DBG_EEPROM: eeprom processing
219 * @ATH_DBG_CALIBRATE: periodic calibration
220 * @ATH_DBG_INTERRUPT: interrupt processing
221 * @ATH_DBG_REGULATORY: regulatory processing
222 * @ATH_DBG_ANI: adaptive noise immunitive processing
223 * @ATH_DBG_XMIT: basic xmit operation
224 * @ATH_DBG_BEACON: beacon handling
225 * @ATH_DBG_CONFIG: configuration of the hardware
226 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
227 * @ATH_DBG_PS: power save processing
228 * @ATH_DBG_HWTIMER: hardware timer handling
229 * @ATH_DBG_BTCOEX: bluetooth coexistance
230 * @ATH_DBG_BSTUCK: stuck beacons
231 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
232 * used exclusively for WLAN-BT coexistence starting from
233 * AR9462.
234 * @ATH_DBG_DFS: radar datection
235 * @ATH_DBG_WOW: Wake on Wireless
236 * @ATH_DBG_ANY: enable all debugging
237 *
238 * The debug level is used to control the amount and type of debugging output
239 * we want to see. Each driver has its own method for enabling debugging and
240 * modifying debug level states -- but this is typically done through a
241 * module parameter 'debug' along with a respective 'debug' debugfs file
242 * entry.
243 */
244enum ATH_DEBUG {
245 ATH_DBG_RESET = 0x00000001,
246 ATH_DBG_QUEUE = 0x00000002,
247 ATH_DBG_EEPROM = 0x00000004,
248 ATH_DBG_CALIBRATE = 0x00000008,
249 ATH_DBG_INTERRUPT = 0x00000010,
250 ATH_DBG_REGULATORY = 0x00000020,
251 ATH_DBG_ANI = 0x00000040,
252 ATH_DBG_XMIT = 0x00000080,
253 ATH_DBG_BEACON = 0x00000100,
254 ATH_DBG_CONFIG = 0x00000200,
255 ATH_DBG_FATAL = 0x00000400,
256 ATH_DBG_PS = 0x00000800,
257 ATH_DBG_BTCOEX = 0x00001000,
258 ATH_DBG_WMI = 0x00002000,
259 ATH_DBG_BSTUCK = 0x00004000,
260 ATH_DBG_MCI = 0x00008000,
261 ATH_DBG_DFS = 0x00010000,
262 ATH_DBG_WOW = 0x00020000,
263 ATH_DBG_ANY = 0xffffffff
264};
265
266#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
267
268#ifdef CONFIG_ATH_DEBUG
269
270#define ath_dbg(common, dbg_mask, fmt, ...) \
271do { \
272 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
273 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
274} while (0)
275
276#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
277#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
278
279#else
280
281static inline __attribute__ ((format (printf, 3, 4)))
282void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
283 const char *fmt, ...)
284{
285}
286#define ath_dbg(common, dbg_mask, fmt, ...) \
287 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
288
289#define ATH_DBG_WARN(foo, arg...) do {} while (0)
290#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
291 int __ret_warn_once = !!(foo); \
292 unlikely(__ret_warn_once); \
293})
294
295#endif /* CONFIG_ATH_DEBUG */
296
297/** Returns string describing opmode, or NULL if unknown mode. */
298#ifdef CONFIG_ATH_DEBUG
299const char *ath_opmode_to_string(enum nl80211_iftype opmode);
300#else
301static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
302{
303 return "UNKNOWN";
304}
305#endif
306
307#endif /* ATH_H */