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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477, lan8804
20 */
21
22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31#include <linux/ptp_clock_kernel.h>
32#include <linux/ptp_clock.h>
33#include <linux/ptp_classify.h>
34#include <linux/net_tstamp.h>
35#include <linux/gpio/consumer.h>
36
37/* Operation Mode Strap Override */
38#define MII_KSZPHY_OMSO 0x16
39#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
44
45/* general Interrupt control/status reg in vendor specific block. */
46#define MII_KSZPHY_INTCS 0x1B
47#define KSZPHY_INTCS_JABBER BIT(15)
48#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50#define KSZPHY_INTCS_PARELLEL BIT(12)
51#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52#define KSZPHY_INTCS_LINK_DOWN BIT(10)
53#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54#define KSZPHY_INTCS_LINK_UP BIT(8)
55#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
61
62/* LinkMD Control/Status */
63#define KSZ8081_LMD 0x1d
64#define KSZ8081_LMD_ENABLE_TEST BIT(15)
65#define KSZ8081_LMD_STAT_NORMAL 0
66#define KSZ8081_LMD_STAT_OPEN 1
67#define KSZ8081_LMD_STAT_SHORT 2
68#define KSZ8081_LMD_STAT_FAIL 3
69#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70/* Short cable (<10 meter) has been detected by LinkMD */
71#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
73
74#define KSZ9x31_LMD 0x12
75#define KSZ9x31_LMD_VCT_EN BIT(15)
76#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78#define KSZ9x31_LMD_VCT_SEL_RESULT 0
79#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82#define KSZ9x31_LMD_VCT_ST_NORMAL 0
83#define KSZ9x31_LMD_VCT_ST_OPEN 1
84#define KSZ9x31_LMD_VCT_ST_SHORT 2
85#define KSZ9x31_LMD_VCT_ST_FAIL 3
86#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
94
95#define KSZPHY_WIRE_PAIR_MASK 0x3
96
97#define LAN8814_CABLE_DIAG 0x12
98#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100#define LAN8814_PAIR_BIT_SHIFT 12
101
102#define LAN8814_WIRE_PAIR_MASK 0xF
103
104/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105#define LAN8814_INTC 0x18
106#define LAN8814_INTS 0x1B
107
108#define LAN8814_INT_LINK_DOWN BIT(2)
109#define LAN8814_INT_LINK_UP BIT(0)
110#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
112
113#define LAN8814_INTR_CTRL_REG 0x34
114#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
116
117/* Represents 1ppm adjustment in 2^32 format with
118 * each nsec contains 4 clock cycles.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
120 */
121#define LAN8814_1PPM_FORMAT 17179
122
123#define PTP_RX_VERSION 0x0248
124#define PTP_TX_VERSION 0x0288
125#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
126#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
127
128#define PTP_RX_MOD 0x024F
129#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
130#define PTP_RX_TIMESTAMP_EN 0x024D
131#define PTP_TX_TIMESTAMP_EN 0x028D
132
133#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
134#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
135#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
136#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
137
138#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
139#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
140
141#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
142#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
143#define LTC_HARD_RESET 0x023F
144#define LTC_HARD_RESET_ BIT(0)
145
146#define TSU_HARD_RESET 0x02C1
147#define TSU_HARD_RESET_ BIT(0)
148
149#define PTP_CMD_CTL 0x0200
150#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
151#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
152#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
153#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
154#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
155#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
156
157#define PTP_CLOCK_SET_SEC_MID 0x0206
158#define PTP_CLOCK_SET_SEC_LO 0x0207
159#define PTP_CLOCK_SET_NS_HI 0x0208
160#define PTP_CLOCK_SET_NS_LO 0x0209
161
162#define PTP_CLOCK_READ_SEC_MID 0x022A
163#define PTP_CLOCK_READ_SEC_LO 0x022B
164#define PTP_CLOCK_READ_NS_HI 0x022C
165#define PTP_CLOCK_READ_NS_LO 0x022D
166
167#define PTP_OPERATING_MODE 0x0241
168#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
169
170#define PTP_TX_MOD 0x028F
171#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
172#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
173
174#define PTP_RX_PARSE_CONFIG 0x0242
175#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
176#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
177#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
178
179#define PTP_TX_PARSE_CONFIG 0x0282
180#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
181#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
182#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
183
184#define PTP_CLOCK_RATE_ADJ_HI 0x020C
185#define PTP_CLOCK_RATE_ADJ_LO 0x020D
186#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
187
188#define PTP_LTC_STEP_ADJ_HI 0x0212
189#define PTP_LTC_STEP_ADJ_LO 0x0213
190#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
191
192#define LAN8814_INTR_STS_REG 0x0033
193#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
194#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
195#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
196#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
197
198#define PTP_CAP_INFO 0x022A
199#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
200#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
201
202#define PTP_TX_EGRESS_SEC_HI 0x0296
203#define PTP_TX_EGRESS_SEC_LO 0x0297
204#define PTP_TX_EGRESS_NS_HI 0x0294
205#define PTP_TX_EGRESS_NS_LO 0x0295
206#define PTP_TX_MSG_HEADER2 0x0299
207
208#define PTP_RX_INGRESS_SEC_HI 0x0256
209#define PTP_RX_INGRESS_SEC_LO 0x0257
210#define PTP_RX_INGRESS_NS_HI 0x0254
211#define PTP_RX_INGRESS_NS_LO 0x0255
212#define PTP_RX_MSG_HEADER2 0x0259
213
214#define PTP_TSU_INT_EN 0x0200
215#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
216#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
217#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
218#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
219
220#define PTP_TSU_INT_STS 0x0201
221#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
222#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
223#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
224#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
225
226#define LAN8814_LED_CTRL_1 0x0
227#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
228
229/* PHY Control 1 */
230#define MII_KSZPHY_CTRL_1 0x1e
231#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
232
233/* PHY Control 2 / PHY Control (if no PHY Control 1) */
234#define MII_KSZPHY_CTRL_2 0x1f
235#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
236/* bitmap of PHY register to set interrupt mode */
237#define KSZ8081_CTRL2_HP_MDIX BIT(15)
238#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
239#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
240#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
241#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
242#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
243#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
244
245/* Write/read to/from extended registers */
246#define MII_KSZPHY_EXTREG 0x0b
247#define KSZPHY_EXTREG_WRITE 0x8000
248
249#define MII_KSZPHY_EXTREG_WRITE 0x0c
250#define MII_KSZPHY_EXTREG_READ 0x0d
251
252/* Extended registers */
253#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
254#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
255#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
256
257#define PS_TO_REG 200
258#define FIFO_SIZE 8
259
260/* Delay used to get the second part from the LTC */
261#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
262
263struct kszphy_hw_stat {
264 const char *string;
265 u8 reg;
266 u8 bits;
267};
268
269static struct kszphy_hw_stat kszphy_hw_stats[] = {
270 { "phy_receive_errors", 21, 16},
271 { "phy_idle_errors", 10, 8 },
272};
273
274struct kszphy_type {
275 u32 led_mode_reg;
276 u16 interrupt_level_mask;
277 u16 cable_diag_reg;
278 unsigned long pair_mask;
279 u16 disable_dll_tx_bit;
280 u16 disable_dll_rx_bit;
281 u16 disable_dll_mask;
282 bool has_broadcast_disable;
283 bool has_nand_tree_disable;
284 bool has_rmii_ref_clk_sel;
285};
286
287/* Shared structure between the PHYs of the same package. */
288struct lan8814_shared_priv {
289 struct phy_device *phydev;
290 struct ptp_clock *ptp_clock;
291 struct ptp_clock_info ptp_clock_info;
292
293 /* Reference counter to how many ports in the package are enabling the
294 * timestamping
295 */
296 u8 ref;
297
298 /* Lock for ptp_clock and ref */
299 struct mutex shared_lock;
300};
301
302struct lan8814_ptp_rx_ts {
303 struct list_head list;
304 u32 seconds;
305 u32 nsec;
306 u16 seq_id;
307};
308
309struct kszphy_ptp_priv {
310 struct mii_timestamper mii_ts;
311 struct phy_device *phydev;
312
313 struct sk_buff_head tx_queue;
314 struct sk_buff_head rx_queue;
315
316 struct list_head rx_ts_list;
317 /* Lock for Rx ts fifo */
318 spinlock_t rx_ts_lock;
319
320 int hwts_tx_type;
321 enum hwtstamp_rx_filters rx_filter;
322 int layer;
323 int version;
324
325 struct ptp_clock *ptp_clock;
326 struct ptp_clock_info ptp_clock_info;
327 /* Lock for ptp_clock */
328 struct mutex ptp_lock;
329 struct ptp_pin_desc *pin_config;
330
331 s64 seconds;
332 /* Lock for accessing seconds */
333 spinlock_t seconds_lock;
334};
335
336struct kszphy_priv {
337 struct kszphy_ptp_priv ptp_priv;
338 const struct kszphy_type *type;
339 int led_mode;
340 u16 vct_ctrl1000;
341 bool rmii_ref_clk_sel;
342 bool rmii_ref_clk_sel_val;
343 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
344};
345
346static const struct kszphy_type lan8814_type = {
347 .led_mode_reg = ~LAN8814_LED_CTRL_1,
348 .cable_diag_reg = LAN8814_CABLE_DIAG,
349 .pair_mask = LAN8814_WIRE_PAIR_MASK,
350};
351
352static const struct kszphy_type ksz886x_type = {
353 .cable_diag_reg = KSZ8081_LMD,
354 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
355};
356
357static const struct kszphy_type ksz8021_type = {
358 .led_mode_reg = MII_KSZPHY_CTRL_2,
359 .has_broadcast_disable = true,
360 .has_nand_tree_disable = true,
361 .has_rmii_ref_clk_sel = true,
362};
363
364static const struct kszphy_type ksz8041_type = {
365 .led_mode_reg = MII_KSZPHY_CTRL_1,
366};
367
368static const struct kszphy_type ksz8051_type = {
369 .led_mode_reg = MII_KSZPHY_CTRL_2,
370 .has_nand_tree_disable = true,
371};
372
373static const struct kszphy_type ksz8081_type = {
374 .led_mode_reg = MII_KSZPHY_CTRL_2,
375 .has_broadcast_disable = true,
376 .has_nand_tree_disable = true,
377 .has_rmii_ref_clk_sel = true,
378};
379
380static const struct kszphy_type ks8737_type = {
381 .interrupt_level_mask = BIT(14),
382};
383
384static const struct kszphy_type ksz9021_type = {
385 .interrupt_level_mask = BIT(14),
386};
387
388static const struct kszphy_type ksz9131_type = {
389 .interrupt_level_mask = BIT(14),
390 .disable_dll_tx_bit = BIT(12),
391 .disable_dll_rx_bit = BIT(12),
392 .disable_dll_mask = BIT_MASK(12),
393};
394
395static const struct kszphy_type lan8841_type = {
396 .disable_dll_tx_bit = BIT(14),
397 .disable_dll_rx_bit = BIT(14),
398 .disable_dll_mask = BIT_MASK(14),
399 .cable_diag_reg = LAN8814_CABLE_DIAG,
400 .pair_mask = LAN8814_WIRE_PAIR_MASK,
401};
402
403static int kszphy_extended_write(struct phy_device *phydev,
404 u32 regnum, u16 val)
405{
406 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
407 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
408}
409
410static int kszphy_extended_read(struct phy_device *phydev,
411 u32 regnum)
412{
413 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
414 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
415}
416
417static int kszphy_ack_interrupt(struct phy_device *phydev)
418{
419 /* bit[7..0] int status, which is a read and clear register. */
420 int rc;
421
422 rc = phy_read(phydev, MII_KSZPHY_INTCS);
423
424 return (rc < 0) ? rc : 0;
425}
426
427static int kszphy_config_intr(struct phy_device *phydev)
428{
429 const struct kszphy_type *type = phydev->drv->driver_data;
430 int temp, err;
431 u16 mask;
432
433 if (type && type->interrupt_level_mask)
434 mask = type->interrupt_level_mask;
435 else
436 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
437
438 /* set the interrupt pin active low */
439 temp = phy_read(phydev, MII_KSZPHY_CTRL);
440 if (temp < 0)
441 return temp;
442 temp &= ~mask;
443 phy_write(phydev, MII_KSZPHY_CTRL, temp);
444
445 /* enable / disable interrupts */
446 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
447 err = kszphy_ack_interrupt(phydev);
448 if (err)
449 return err;
450
451 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
452 } else {
453 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
454 if (err)
455 return err;
456
457 err = kszphy_ack_interrupt(phydev);
458 }
459
460 return err;
461}
462
463static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
464{
465 int irq_status;
466
467 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
468 if (irq_status < 0) {
469 phy_error(phydev);
470 return IRQ_NONE;
471 }
472
473 if (!(irq_status & KSZPHY_INTCS_STATUS))
474 return IRQ_NONE;
475
476 phy_trigger_machine(phydev);
477
478 return IRQ_HANDLED;
479}
480
481static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
482{
483 int ctrl;
484
485 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
486 if (ctrl < 0)
487 return ctrl;
488
489 if (val)
490 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
491 else
492 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
493
494 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
495}
496
497static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
498{
499 int rc, temp, shift;
500
501 switch (reg) {
502 case MII_KSZPHY_CTRL_1:
503 shift = 14;
504 break;
505 case MII_KSZPHY_CTRL_2:
506 shift = 4;
507 break;
508 default:
509 return -EINVAL;
510 }
511
512 temp = phy_read(phydev, reg);
513 if (temp < 0) {
514 rc = temp;
515 goto out;
516 }
517
518 temp &= ~(3 << shift);
519 temp |= val << shift;
520 rc = phy_write(phydev, reg, temp);
521out:
522 if (rc < 0)
523 phydev_err(phydev, "failed to set led mode\n");
524
525 return rc;
526}
527
528/* Disable PHY address 0 as the broadcast address, so that it can be used as a
529 * unique (non-broadcast) address on a shared bus.
530 */
531static int kszphy_broadcast_disable(struct phy_device *phydev)
532{
533 int ret;
534
535 ret = phy_read(phydev, MII_KSZPHY_OMSO);
536 if (ret < 0)
537 goto out;
538
539 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
540out:
541 if (ret)
542 phydev_err(phydev, "failed to disable broadcast address\n");
543
544 return ret;
545}
546
547static int kszphy_nand_tree_disable(struct phy_device *phydev)
548{
549 int ret;
550
551 ret = phy_read(phydev, MII_KSZPHY_OMSO);
552 if (ret < 0)
553 goto out;
554
555 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
556 return 0;
557
558 ret = phy_write(phydev, MII_KSZPHY_OMSO,
559 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
560out:
561 if (ret)
562 phydev_err(phydev, "failed to disable NAND tree mode\n");
563
564 return ret;
565}
566
567/* Some config bits need to be set again on resume, handle them here. */
568static int kszphy_config_reset(struct phy_device *phydev)
569{
570 struct kszphy_priv *priv = phydev->priv;
571 int ret;
572
573 if (priv->rmii_ref_clk_sel) {
574 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
575 if (ret) {
576 phydev_err(phydev,
577 "failed to set rmii reference clock\n");
578 return ret;
579 }
580 }
581
582 if (priv->type && priv->led_mode >= 0)
583 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
584
585 return 0;
586}
587
588static int kszphy_config_init(struct phy_device *phydev)
589{
590 struct kszphy_priv *priv = phydev->priv;
591 const struct kszphy_type *type;
592
593 if (!priv)
594 return 0;
595
596 type = priv->type;
597
598 if (type && type->has_broadcast_disable)
599 kszphy_broadcast_disable(phydev);
600
601 if (type && type->has_nand_tree_disable)
602 kszphy_nand_tree_disable(phydev);
603
604 return kszphy_config_reset(phydev);
605}
606
607static int ksz8041_fiber_mode(struct phy_device *phydev)
608{
609 struct device_node *of_node = phydev->mdio.dev.of_node;
610
611 return of_property_read_bool(of_node, "micrel,fiber-mode");
612}
613
614static int ksz8041_config_init(struct phy_device *phydev)
615{
616 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
617
618 /* Limit supported and advertised modes in fiber mode */
619 if (ksz8041_fiber_mode(phydev)) {
620 phydev->dev_flags |= MICREL_PHY_FXEN;
621 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
622 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
623
624 linkmode_and(phydev->supported, phydev->supported, mask);
625 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
626 phydev->supported);
627 linkmode_and(phydev->advertising, phydev->advertising, mask);
628 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
629 phydev->advertising);
630 phydev->autoneg = AUTONEG_DISABLE;
631 }
632
633 return kszphy_config_init(phydev);
634}
635
636static int ksz8041_config_aneg(struct phy_device *phydev)
637{
638 /* Skip auto-negotiation in fiber mode */
639 if (phydev->dev_flags & MICREL_PHY_FXEN) {
640 phydev->speed = SPEED_100;
641 return 0;
642 }
643
644 return genphy_config_aneg(phydev);
645}
646
647static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
648 const bool ksz_8051)
649{
650 int ret;
651
652 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
653 return 0;
654
655 ret = phy_read(phydev, MII_BMSR);
656 if (ret < 0)
657 return ret;
658
659 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
660 * exact PHY ID. However, they can be told apart by the extended
661 * capability registers presence. The KSZ8051 PHY has them while
662 * the switch does not.
663 */
664 ret &= BMSR_ERCAP;
665 if (ksz_8051)
666 return ret;
667 else
668 return !ret;
669}
670
671static int ksz8051_match_phy_device(struct phy_device *phydev)
672{
673 return ksz8051_ksz8795_match_phy_device(phydev, true);
674}
675
676static int ksz8081_config_init(struct phy_device *phydev)
677{
678 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
679 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
680 * pull-down is missing, the factory test mode should be cleared by
681 * manually writing a 0.
682 */
683 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
684
685 return kszphy_config_init(phydev);
686}
687
688static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
689{
690 u16 val;
691
692 switch (ctrl) {
693 case ETH_TP_MDI:
694 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
695 break;
696 case ETH_TP_MDI_X:
697 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
698 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
699 break;
700 case ETH_TP_MDI_AUTO:
701 val = 0;
702 break;
703 default:
704 return 0;
705 }
706
707 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
708 KSZ8081_CTRL2_HP_MDIX |
709 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
710 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
711 KSZ8081_CTRL2_HP_MDIX | val);
712}
713
714static int ksz8081_config_aneg(struct phy_device *phydev)
715{
716 int ret;
717
718 ret = genphy_config_aneg(phydev);
719 if (ret)
720 return ret;
721
722 /* The MDI-X configuration is automatically changed by the PHY after
723 * switching from autoneg off to on. So, take MDI-X configuration under
724 * own control and set it after autoneg configuration was done.
725 */
726 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
727}
728
729static int ksz8081_mdix_update(struct phy_device *phydev)
730{
731 int ret;
732
733 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
734 if (ret < 0)
735 return ret;
736
737 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
738 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
739 phydev->mdix_ctrl = ETH_TP_MDI_X;
740 else
741 phydev->mdix_ctrl = ETH_TP_MDI;
742 } else {
743 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
744 }
745
746 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
747 if (ret < 0)
748 return ret;
749
750 if (ret & KSZ8081_CTRL1_MDIX_STAT)
751 phydev->mdix = ETH_TP_MDI;
752 else
753 phydev->mdix = ETH_TP_MDI_X;
754
755 return 0;
756}
757
758static int ksz8081_read_status(struct phy_device *phydev)
759{
760 int ret;
761
762 ret = ksz8081_mdix_update(phydev);
763 if (ret < 0)
764 return ret;
765
766 return genphy_read_status(phydev);
767}
768
769static int ksz8061_config_init(struct phy_device *phydev)
770{
771 int ret;
772
773 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
774 if (ret)
775 return ret;
776
777 return kszphy_config_init(phydev);
778}
779
780static int ksz8795_match_phy_device(struct phy_device *phydev)
781{
782 return ksz8051_ksz8795_match_phy_device(phydev, false);
783}
784
785static int ksz9021_load_values_from_of(struct phy_device *phydev,
786 const struct device_node *of_node,
787 u16 reg,
788 const char *field1, const char *field2,
789 const char *field3, const char *field4)
790{
791 int val1 = -1;
792 int val2 = -2;
793 int val3 = -3;
794 int val4 = -4;
795 int newval;
796 int matches = 0;
797
798 if (!of_property_read_u32(of_node, field1, &val1))
799 matches++;
800
801 if (!of_property_read_u32(of_node, field2, &val2))
802 matches++;
803
804 if (!of_property_read_u32(of_node, field3, &val3))
805 matches++;
806
807 if (!of_property_read_u32(of_node, field4, &val4))
808 matches++;
809
810 if (!matches)
811 return 0;
812
813 if (matches < 4)
814 newval = kszphy_extended_read(phydev, reg);
815 else
816 newval = 0;
817
818 if (val1 != -1)
819 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
820
821 if (val2 != -2)
822 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
823
824 if (val3 != -3)
825 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
826
827 if (val4 != -4)
828 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
829
830 return kszphy_extended_write(phydev, reg, newval);
831}
832
833static int ksz9021_config_init(struct phy_device *phydev)
834{
835 const struct device_node *of_node;
836 const struct device *dev_walker;
837
838 /* The Micrel driver has a deprecated option to place phy OF
839 * properties in the MAC node. Walk up the tree of devices to
840 * find a device with an OF node.
841 */
842 dev_walker = &phydev->mdio.dev;
843 do {
844 of_node = dev_walker->of_node;
845 dev_walker = dev_walker->parent;
846
847 } while (!of_node && dev_walker);
848
849 if (of_node) {
850 ksz9021_load_values_from_of(phydev, of_node,
851 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
852 "txen-skew-ps", "txc-skew-ps",
853 "rxdv-skew-ps", "rxc-skew-ps");
854 ksz9021_load_values_from_of(phydev, of_node,
855 MII_KSZPHY_RX_DATA_PAD_SKEW,
856 "rxd0-skew-ps", "rxd1-skew-ps",
857 "rxd2-skew-ps", "rxd3-skew-ps");
858 ksz9021_load_values_from_of(phydev, of_node,
859 MII_KSZPHY_TX_DATA_PAD_SKEW,
860 "txd0-skew-ps", "txd1-skew-ps",
861 "txd2-skew-ps", "txd3-skew-ps");
862 }
863 return 0;
864}
865
866#define KSZ9031_PS_TO_REG 60
867
868/* Extended registers */
869/* MMD Address 0x0 */
870#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
871#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
872
873/* MMD Address 0x2 */
874#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
875#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
876#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
877
878#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
879#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
880#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
881#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
882#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
883
884#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
885#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
886#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
887#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
888#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
889
890#define MII_KSZ9031RN_CLK_PAD_SKEW 8
891#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
892#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
893
894/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
895 * provide different RGMII options we need to configure delay offset
896 * for each pad relative to build in delay.
897 */
898/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
899 * 1.80ns
900 */
901#define RX_ID 0x7
902#define RX_CLK_ID 0x19
903
904/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
905 * internal 1.2ns delay.
906 */
907#define RX_ND 0xc
908#define RX_CLK_ND 0x0
909
910/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
911#define TX_ID 0x0
912#define TX_CLK_ID 0x1f
913
914/* set tx and tx_clk to "No delay adjustment" to keep 0ns
915 * dealy
916 */
917#define TX_ND 0x7
918#define TX_CLK_ND 0xf
919
920/* MMD Address 0x1C */
921#define MII_KSZ9031RN_EDPD 0x23
922#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
923
924static int ksz9031_of_load_skew_values(struct phy_device *phydev,
925 const struct device_node *of_node,
926 u16 reg, size_t field_sz,
927 const char *field[], u8 numfields,
928 bool *update)
929{
930 int val[4] = {-1, -2, -3, -4};
931 int matches = 0;
932 u16 mask;
933 u16 maxval;
934 u16 newval;
935 int i;
936
937 for (i = 0; i < numfields; i++)
938 if (!of_property_read_u32(of_node, field[i], val + i))
939 matches++;
940
941 if (!matches)
942 return 0;
943
944 *update |= true;
945
946 if (matches < numfields)
947 newval = phy_read_mmd(phydev, 2, reg);
948 else
949 newval = 0;
950
951 maxval = (field_sz == 4) ? 0xf : 0x1f;
952 for (i = 0; i < numfields; i++)
953 if (val[i] != -(i + 1)) {
954 mask = 0xffff;
955 mask ^= maxval << (field_sz * i);
956 newval = (newval & mask) |
957 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
958 << (field_sz * i));
959 }
960
961 return phy_write_mmd(phydev, 2, reg, newval);
962}
963
964/* Center KSZ9031RNX FLP timing at 16ms. */
965static int ksz9031_center_flp_timing(struct phy_device *phydev)
966{
967 int result;
968
969 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
970 0x0006);
971 if (result)
972 return result;
973
974 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
975 0x1A80);
976 if (result)
977 return result;
978
979 return genphy_restart_aneg(phydev);
980}
981
982/* Enable energy-detect power-down mode */
983static int ksz9031_enable_edpd(struct phy_device *phydev)
984{
985 int reg;
986
987 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
988 if (reg < 0)
989 return reg;
990 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
991 reg | MII_KSZ9031RN_EDPD_ENABLE);
992}
993
994static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
995{
996 u16 rx, tx, rx_clk, tx_clk;
997 int ret;
998
999 switch (phydev->interface) {
1000 case PHY_INTERFACE_MODE_RGMII:
1001 tx = TX_ND;
1002 tx_clk = TX_CLK_ND;
1003 rx = RX_ND;
1004 rx_clk = RX_CLK_ND;
1005 break;
1006 case PHY_INTERFACE_MODE_RGMII_ID:
1007 tx = TX_ID;
1008 tx_clk = TX_CLK_ID;
1009 rx = RX_ID;
1010 rx_clk = RX_CLK_ID;
1011 break;
1012 case PHY_INTERFACE_MODE_RGMII_RXID:
1013 tx = TX_ND;
1014 tx_clk = TX_CLK_ND;
1015 rx = RX_ID;
1016 rx_clk = RX_CLK_ID;
1017 break;
1018 case PHY_INTERFACE_MODE_RGMII_TXID:
1019 tx = TX_ID;
1020 tx_clk = TX_CLK_ID;
1021 rx = RX_ND;
1022 rx_clk = RX_CLK_ND;
1023 break;
1024 default:
1025 return 0;
1026 }
1027
1028 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1029 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1030 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1031 if (ret < 0)
1032 return ret;
1033
1034 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1035 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1036 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1037 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1038 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1039 if (ret < 0)
1040 return ret;
1041
1042 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1043 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1044 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1045 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1046 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1047 if (ret < 0)
1048 return ret;
1049
1050 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1051 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1052 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1053}
1054
1055static int ksz9031_config_init(struct phy_device *phydev)
1056{
1057 const struct device_node *of_node;
1058 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1059 static const char *rx_data_skews[4] = {
1060 "rxd0-skew-ps", "rxd1-skew-ps",
1061 "rxd2-skew-ps", "rxd3-skew-ps"
1062 };
1063 static const char *tx_data_skews[4] = {
1064 "txd0-skew-ps", "txd1-skew-ps",
1065 "txd2-skew-ps", "txd3-skew-ps"
1066 };
1067 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1068 const struct device *dev_walker;
1069 int result;
1070
1071 result = ksz9031_enable_edpd(phydev);
1072 if (result < 0)
1073 return result;
1074
1075 /* The Micrel driver has a deprecated option to place phy OF
1076 * properties in the MAC node. Walk up the tree of devices to
1077 * find a device with an OF node.
1078 */
1079 dev_walker = &phydev->mdio.dev;
1080 do {
1081 of_node = dev_walker->of_node;
1082 dev_walker = dev_walker->parent;
1083 } while (!of_node && dev_walker);
1084
1085 if (of_node) {
1086 bool update = false;
1087
1088 if (phy_interface_is_rgmii(phydev)) {
1089 result = ksz9031_config_rgmii_delay(phydev);
1090 if (result < 0)
1091 return result;
1092 }
1093
1094 ksz9031_of_load_skew_values(phydev, of_node,
1095 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1096 clk_skews, 2, &update);
1097
1098 ksz9031_of_load_skew_values(phydev, of_node,
1099 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1100 control_skews, 2, &update);
1101
1102 ksz9031_of_load_skew_values(phydev, of_node,
1103 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1104 rx_data_skews, 4, &update);
1105
1106 ksz9031_of_load_skew_values(phydev, of_node,
1107 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1108 tx_data_skews, 4, &update);
1109
1110 if (update && !phy_interface_is_rgmii(phydev))
1111 phydev_warn(phydev,
1112 "*-skew-ps values should be used only with RGMII PHY modes\n");
1113
1114 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1115 * When the device links in the 1000BASE-T slave mode only,
1116 * the optional 125MHz reference output clock (CLK125_NDO)
1117 * has wide duty cycle variation.
1118 *
1119 * The optional CLK125_NDO clock does not meet the RGMII
1120 * 45/55 percent (min/max) duty cycle requirement and therefore
1121 * cannot be used directly by the MAC side for clocking
1122 * applications that have setup/hold time requirements on
1123 * rising and falling clock edges.
1124 *
1125 * Workaround:
1126 * Force the phy to be the master to receive a stable clock
1127 * which meets the duty cycle requirement.
1128 */
1129 if (of_property_read_bool(of_node, "micrel,force-master")) {
1130 result = phy_read(phydev, MII_CTRL1000);
1131 if (result < 0)
1132 goto err_force_master;
1133
1134 /* enable master mode, config & prefer master */
1135 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1136 result = phy_write(phydev, MII_CTRL1000, result);
1137 if (result < 0)
1138 goto err_force_master;
1139 }
1140 }
1141
1142 return ksz9031_center_flp_timing(phydev);
1143
1144err_force_master:
1145 phydev_err(phydev, "failed to force the phy to master mode\n");
1146 return result;
1147}
1148
1149#define KSZ9131_SKEW_5BIT_MAX 2400
1150#define KSZ9131_SKEW_4BIT_MAX 800
1151#define KSZ9131_OFFSET 700
1152#define KSZ9131_STEP 100
1153
1154static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1155 struct device_node *of_node,
1156 u16 reg, size_t field_sz,
1157 char *field[], u8 numfields)
1158{
1159 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1160 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1161 int skewval, skewmax = 0;
1162 int matches = 0;
1163 u16 maxval;
1164 u16 newval;
1165 u16 mask;
1166 int i;
1167
1168 /* psec properties in dts should mean x pico seconds */
1169 if (field_sz == 5)
1170 skewmax = KSZ9131_SKEW_5BIT_MAX;
1171 else
1172 skewmax = KSZ9131_SKEW_4BIT_MAX;
1173
1174 for (i = 0; i < numfields; i++)
1175 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1176 if (skewval < -KSZ9131_OFFSET)
1177 skewval = -KSZ9131_OFFSET;
1178 else if (skewval > skewmax)
1179 skewval = skewmax;
1180
1181 val[i] = skewval + KSZ9131_OFFSET;
1182 matches++;
1183 }
1184
1185 if (!matches)
1186 return 0;
1187
1188 if (matches < numfields)
1189 newval = phy_read_mmd(phydev, 2, reg);
1190 else
1191 newval = 0;
1192
1193 maxval = (field_sz == 4) ? 0xf : 0x1f;
1194 for (i = 0; i < numfields; i++)
1195 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1196 mask = 0xffff;
1197 mask ^= maxval << (field_sz * i);
1198 newval = (newval & mask) |
1199 (((val[i] / KSZ9131_STEP) & maxval)
1200 << (field_sz * i));
1201 }
1202
1203 return phy_write_mmd(phydev, 2, reg, newval);
1204}
1205
1206#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1207#define KSZ9131RN_RXC_DLL_CTRL 76
1208#define KSZ9131RN_TXC_DLL_CTRL 77
1209#define KSZ9131RN_DLL_ENABLE_DELAY 0
1210
1211static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1212{
1213 const struct kszphy_type *type = phydev->drv->driver_data;
1214 u16 rxcdll_val, txcdll_val;
1215 int ret;
1216
1217 switch (phydev->interface) {
1218 case PHY_INTERFACE_MODE_RGMII:
1219 rxcdll_val = type->disable_dll_rx_bit;
1220 txcdll_val = type->disable_dll_tx_bit;
1221 break;
1222 case PHY_INTERFACE_MODE_RGMII_ID:
1223 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1224 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1225 break;
1226 case PHY_INTERFACE_MODE_RGMII_RXID:
1227 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1228 txcdll_val = type->disable_dll_tx_bit;
1229 break;
1230 case PHY_INTERFACE_MODE_RGMII_TXID:
1231 rxcdll_val = type->disable_dll_rx_bit;
1232 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1233 break;
1234 default:
1235 return 0;
1236 }
1237
1238 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1239 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1240 rxcdll_val);
1241 if (ret < 0)
1242 return ret;
1243
1244 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1245 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1246 txcdll_val);
1247}
1248
1249/* Silicon Errata DS80000693B
1250 *
1251 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1252 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1253 * according to the datasheet (off if there is no link).
1254 */
1255static int ksz9131_led_errata(struct phy_device *phydev)
1256{
1257 int reg;
1258
1259 reg = phy_read_mmd(phydev, 2, 0);
1260 if (reg < 0)
1261 return reg;
1262
1263 if (!(reg & BIT(4)))
1264 return 0;
1265
1266 return phy_set_bits(phydev, 0x1e, BIT(9));
1267}
1268
1269static int ksz9131_config_init(struct phy_device *phydev)
1270{
1271 struct device_node *of_node;
1272 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1273 char *rx_data_skews[4] = {
1274 "rxd0-skew-psec", "rxd1-skew-psec",
1275 "rxd2-skew-psec", "rxd3-skew-psec"
1276 };
1277 char *tx_data_skews[4] = {
1278 "txd0-skew-psec", "txd1-skew-psec",
1279 "txd2-skew-psec", "txd3-skew-psec"
1280 };
1281 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1282 const struct device *dev_walker;
1283 int ret;
1284
1285 dev_walker = &phydev->mdio.dev;
1286 do {
1287 of_node = dev_walker->of_node;
1288 dev_walker = dev_walker->parent;
1289 } while (!of_node && dev_walker);
1290
1291 if (!of_node)
1292 return 0;
1293
1294 if (phy_interface_is_rgmii(phydev)) {
1295 ret = ksz9131_config_rgmii_delay(phydev);
1296 if (ret < 0)
1297 return ret;
1298 }
1299
1300 ret = ksz9131_of_load_skew_values(phydev, of_node,
1301 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1302 clk_skews, 2);
1303 if (ret < 0)
1304 return ret;
1305
1306 ret = ksz9131_of_load_skew_values(phydev, of_node,
1307 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1308 control_skews, 2);
1309 if (ret < 0)
1310 return ret;
1311
1312 ret = ksz9131_of_load_skew_values(phydev, of_node,
1313 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1314 rx_data_skews, 4);
1315 if (ret < 0)
1316 return ret;
1317
1318 ret = ksz9131_of_load_skew_values(phydev, of_node,
1319 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1320 tx_data_skews, 4);
1321 if (ret < 0)
1322 return ret;
1323
1324 ret = ksz9131_led_errata(phydev);
1325 if (ret < 0)
1326 return ret;
1327
1328 return 0;
1329}
1330
1331#define MII_KSZ9131_AUTO_MDIX 0x1C
1332#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1333#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1334
1335static int ksz9131_mdix_update(struct phy_device *phydev)
1336{
1337 int ret;
1338
1339 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1340 if (ret < 0)
1341 return ret;
1342
1343 if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1344 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1345 phydev->mdix_ctrl = ETH_TP_MDI;
1346 else
1347 phydev->mdix_ctrl = ETH_TP_MDI_X;
1348 } else {
1349 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1350 }
1351
1352 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1353 phydev->mdix = ETH_TP_MDI;
1354 else
1355 phydev->mdix = ETH_TP_MDI_X;
1356
1357 return 0;
1358}
1359
1360static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1361{
1362 u16 val;
1363
1364 switch (ctrl) {
1365 case ETH_TP_MDI:
1366 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1367 MII_KSZ9131_AUTO_MDI_SET;
1368 break;
1369 case ETH_TP_MDI_X:
1370 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1371 break;
1372 case ETH_TP_MDI_AUTO:
1373 val = 0;
1374 break;
1375 default:
1376 return 0;
1377 }
1378
1379 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1380 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1381 MII_KSZ9131_AUTO_MDI_SET, val);
1382}
1383
1384static int ksz9131_read_status(struct phy_device *phydev)
1385{
1386 int ret;
1387
1388 ret = ksz9131_mdix_update(phydev);
1389 if (ret < 0)
1390 return ret;
1391
1392 return genphy_read_status(phydev);
1393}
1394
1395static int ksz9131_config_aneg(struct phy_device *phydev)
1396{
1397 int ret;
1398
1399 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1400 if (ret)
1401 return ret;
1402
1403 return genphy_config_aneg(phydev);
1404}
1405
1406static int ksz9477_get_features(struct phy_device *phydev)
1407{
1408 int ret;
1409
1410 ret = genphy_read_abilities(phydev);
1411 if (ret)
1412 return ret;
1413
1414 /* The "EEE control and capability 1" (Register 3.20) seems to be
1415 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1416 * on the 7.60 will affect 3.20. So, we need to construct our own list
1417 * of caps.
1418 * KSZ8563R should have 100BaseTX/Full only.
1419 */
1420 linkmode_and(phydev->supported_eee, phydev->supported,
1421 PHY_EEE_CAP1_FEATURES);
1422
1423 return 0;
1424}
1425
1426#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1427#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1428#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1429static int ksz8873mll_read_status(struct phy_device *phydev)
1430{
1431 int regval;
1432
1433 /* dummy read */
1434 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1435
1436 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1437
1438 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1439 phydev->duplex = DUPLEX_HALF;
1440 else
1441 phydev->duplex = DUPLEX_FULL;
1442
1443 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1444 phydev->speed = SPEED_10;
1445 else
1446 phydev->speed = SPEED_100;
1447
1448 phydev->link = 1;
1449 phydev->pause = phydev->asym_pause = 0;
1450
1451 return 0;
1452}
1453
1454static int ksz9031_get_features(struct phy_device *phydev)
1455{
1456 int ret;
1457
1458 ret = genphy_read_abilities(phydev);
1459 if (ret < 0)
1460 return ret;
1461
1462 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1463 * Whenever the device's Asymmetric Pause capability is set to 1,
1464 * link-up may fail after a link-up to link-down transition.
1465 *
1466 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1467 *
1468 * Workaround:
1469 * Do not enable the Asymmetric Pause capability bit.
1470 */
1471 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1472
1473 /* We force setting the Pause capability as the core will force the
1474 * Asymmetric Pause capability to 1 otherwise.
1475 */
1476 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1477
1478 return 0;
1479}
1480
1481static int ksz9031_read_status(struct phy_device *phydev)
1482{
1483 int err;
1484 int regval;
1485
1486 err = genphy_read_status(phydev);
1487 if (err)
1488 return err;
1489
1490 /* Make sure the PHY is not broken. Read idle error count,
1491 * and reset the PHY if it is maxed out.
1492 */
1493 regval = phy_read(phydev, MII_STAT1000);
1494 if ((regval & 0xFF) == 0xFF) {
1495 phy_init_hw(phydev);
1496 phydev->link = 0;
1497 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1498 phydev->drv->config_intr(phydev);
1499 return genphy_config_aneg(phydev);
1500 }
1501
1502 return 0;
1503}
1504
1505static int ksz9x31_cable_test_start(struct phy_device *phydev)
1506{
1507 struct kszphy_priv *priv = phydev->priv;
1508 int ret;
1509
1510 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1511 * Prior to running the cable diagnostics, Auto-negotiation should
1512 * be disabled, full duplex set and the link speed set to 1000Mbps
1513 * via the Basic Control Register.
1514 */
1515 ret = phy_modify(phydev, MII_BMCR,
1516 BMCR_SPEED1000 | BMCR_FULLDPLX |
1517 BMCR_ANENABLE | BMCR_SPEED100,
1518 BMCR_SPEED1000 | BMCR_FULLDPLX);
1519 if (ret)
1520 return ret;
1521
1522 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1523 * The Master-Slave configuration should be set to Slave by writing
1524 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1525 * Register.
1526 */
1527 ret = phy_read(phydev, MII_CTRL1000);
1528 if (ret < 0)
1529 return ret;
1530
1531 /* Cache these bits, they need to be restored once LinkMD finishes. */
1532 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1533 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1534 ret |= CTL1000_ENABLE_MASTER;
1535
1536 return phy_write(phydev, MII_CTRL1000, ret);
1537}
1538
1539static int ksz9x31_cable_test_result_trans(u16 status)
1540{
1541 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1542 case KSZ9x31_LMD_VCT_ST_NORMAL:
1543 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1544 case KSZ9x31_LMD_VCT_ST_OPEN:
1545 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1546 case KSZ9x31_LMD_VCT_ST_SHORT:
1547 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1548 case KSZ9x31_LMD_VCT_ST_FAIL:
1549 fallthrough;
1550 default:
1551 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1552 }
1553}
1554
1555static bool ksz9x31_cable_test_failed(u16 status)
1556{
1557 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1558
1559 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1560}
1561
1562static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1563{
1564 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1565 case KSZ9x31_LMD_VCT_ST_OPEN:
1566 fallthrough;
1567 case KSZ9x31_LMD_VCT_ST_SHORT:
1568 return true;
1569 }
1570 return false;
1571}
1572
1573static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1574{
1575 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1576
1577 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1578 *
1579 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1580 */
1581 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1582 dt = clamp(dt - 22, 0, 255);
1583
1584 return (dt * 400) / 10;
1585}
1586
1587static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1588{
1589 int val, ret;
1590
1591 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1592 !(val & KSZ9x31_LMD_VCT_EN),
1593 30000, 100000, true);
1594
1595 return ret < 0 ? ret : 0;
1596}
1597
1598static int ksz9x31_cable_test_get_pair(int pair)
1599{
1600 static const int ethtool_pair[] = {
1601 ETHTOOL_A_CABLE_PAIR_A,
1602 ETHTOOL_A_CABLE_PAIR_B,
1603 ETHTOOL_A_CABLE_PAIR_C,
1604 ETHTOOL_A_CABLE_PAIR_D,
1605 };
1606
1607 return ethtool_pair[pair];
1608}
1609
1610static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1611{
1612 int ret, val;
1613
1614 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1615 * To test each individual cable pair, set the cable pair in the Cable
1616 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1617 * Diagnostic Register, along with setting the Cable Diagnostics Test
1618 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1619 * will self clear when the test is concluded.
1620 */
1621 ret = phy_write(phydev, KSZ9x31_LMD,
1622 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1623 if (ret)
1624 return ret;
1625
1626 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1627 if (ret)
1628 return ret;
1629
1630 val = phy_read(phydev, KSZ9x31_LMD);
1631 if (val < 0)
1632 return val;
1633
1634 if (ksz9x31_cable_test_failed(val))
1635 return -EAGAIN;
1636
1637 ret = ethnl_cable_test_result(phydev,
1638 ksz9x31_cable_test_get_pair(pair),
1639 ksz9x31_cable_test_result_trans(val));
1640 if (ret)
1641 return ret;
1642
1643 if (!ksz9x31_cable_test_fault_length_valid(val))
1644 return 0;
1645
1646 return ethnl_cable_test_fault_length(phydev,
1647 ksz9x31_cable_test_get_pair(pair),
1648 ksz9x31_cable_test_fault_length(phydev, val));
1649}
1650
1651static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1652 bool *finished)
1653{
1654 struct kszphy_priv *priv = phydev->priv;
1655 unsigned long pair_mask = 0xf;
1656 int retries = 20;
1657 int pair, ret, rv;
1658
1659 *finished = false;
1660
1661 /* Try harder if link partner is active */
1662 while (pair_mask && retries--) {
1663 for_each_set_bit(pair, &pair_mask, 4) {
1664 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1665 if (ret == -EAGAIN)
1666 continue;
1667 if (ret < 0)
1668 return ret;
1669 clear_bit(pair, &pair_mask);
1670 }
1671 /* If link partner is in autonegotiation mode it will send 2ms
1672 * of FLPs with at least 6ms of silence.
1673 * Add 2ms sleep to have better chances to hit this silence.
1674 */
1675 if (pair_mask)
1676 usleep_range(2000, 3000);
1677 }
1678
1679 /* Report remaining unfinished pair result as unknown. */
1680 for_each_set_bit(pair, &pair_mask, 4) {
1681 ret = ethnl_cable_test_result(phydev,
1682 ksz9x31_cable_test_get_pair(pair),
1683 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1684 }
1685
1686 *finished = true;
1687
1688 /* Restore cached bits from before LinkMD got started. */
1689 rv = phy_modify(phydev, MII_CTRL1000,
1690 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1691 priv->vct_ctrl1000);
1692 if (rv)
1693 return rv;
1694
1695 return ret;
1696}
1697
1698static int ksz8873mll_config_aneg(struct phy_device *phydev)
1699{
1700 return 0;
1701}
1702
1703static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1704{
1705 u16 val;
1706
1707 switch (ctrl) {
1708 case ETH_TP_MDI:
1709 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1710 break;
1711 case ETH_TP_MDI_X:
1712 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1713 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1714 * sheet seems to be missing:
1715 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1716 * 0 = Normal operation (transmit on TX+/TX- pins)
1717 */
1718 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1719 break;
1720 case ETH_TP_MDI_AUTO:
1721 val = 0;
1722 break;
1723 default:
1724 return 0;
1725 }
1726
1727 return phy_modify(phydev, MII_BMCR,
1728 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1729 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1730 KSZ886X_BMCR_HP_MDIX | val);
1731}
1732
1733static int ksz886x_config_aneg(struct phy_device *phydev)
1734{
1735 int ret;
1736
1737 ret = genphy_config_aneg(phydev);
1738 if (ret)
1739 return ret;
1740
1741 if (phydev->autoneg != AUTONEG_ENABLE) {
1742 /* When autonegotation is disabled, we need to manually force
1743 * the link state. If we don't do this, the PHY will keep
1744 * sending Fast Link Pulses (FLPs) which are part of the
1745 * autonegotiation process. This is not desired when
1746 * autonegotiation is off.
1747 */
1748 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1749 KSZ886X_CTRL_FORCE_LINK);
1750 if (ret)
1751 return ret;
1752 } else {
1753 /* If we had previously forced the link state, we need to
1754 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1755 * will not perform autonegotiation.
1756 */
1757 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1758 KSZ886X_CTRL_FORCE_LINK);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 /* The MDI-X configuration is automatically changed by the PHY after
1764 * switching from autoneg off to on. So, take MDI-X configuration under
1765 * own control and set it after autoneg configuration was done.
1766 */
1767 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1768}
1769
1770static int ksz886x_mdix_update(struct phy_device *phydev)
1771{
1772 int ret;
1773
1774 ret = phy_read(phydev, MII_BMCR);
1775 if (ret < 0)
1776 return ret;
1777
1778 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1779 if (ret & KSZ886X_BMCR_FORCE_MDI)
1780 phydev->mdix_ctrl = ETH_TP_MDI_X;
1781 else
1782 phydev->mdix_ctrl = ETH_TP_MDI;
1783 } else {
1784 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1785 }
1786
1787 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1788 if (ret < 0)
1789 return ret;
1790
1791 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1792 if (ret & KSZ886X_CTRL_MDIX_STAT)
1793 phydev->mdix = ETH_TP_MDI_X;
1794 else
1795 phydev->mdix = ETH_TP_MDI;
1796
1797 return 0;
1798}
1799
1800static int ksz886x_read_status(struct phy_device *phydev)
1801{
1802 int ret;
1803
1804 ret = ksz886x_mdix_update(phydev);
1805 if (ret < 0)
1806 return ret;
1807
1808 return genphy_read_status(phydev);
1809}
1810
1811struct ksz9477_errata_write {
1812 u8 dev_addr;
1813 u8 reg_addr;
1814 u16 val;
1815};
1816
1817static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1818 /* Register settings are needed to improve PHY receive performance */
1819 {0x01, 0x6f, 0xdd0b},
1820 {0x01, 0x8f, 0x6032},
1821 {0x01, 0x9d, 0x248c},
1822 {0x01, 0x75, 0x0060},
1823 {0x01, 0xd3, 0x7777},
1824 {0x1c, 0x06, 0x3008},
1825 {0x1c, 0x08, 0x2000},
1826
1827 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1828 {0x1c, 0x04, 0x00d0},
1829
1830 /* Register settings are required to meet data sheet supply current specifications */
1831 {0x1c, 0x13, 0x6eff},
1832 {0x1c, 0x14, 0xe6ff},
1833 {0x1c, 0x15, 0x6eff},
1834 {0x1c, 0x16, 0xe6ff},
1835 {0x1c, 0x17, 0x00ff},
1836 {0x1c, 0x18, 0x43ff},
1837 {0x1c, 0x19, 0xc3ff},
1838 {0x1c, 0x1a, 0x6fff},
1839 {0x1c, 0x1b, 0x07ff},
1840 {0x1c, 0x1c, 0x0fff},
1841 {0x1c, 0x1d, 0xe7ff},
1842 {0x1c, 0x1e, 0xefff},
1843 {0x1c, 0x20, 0xeeee},
1844};
1845
1846static int ksz9477_config_init(struct phy_device *phydev)
1847{
1848 int err;
1849 int i;
1850
1851 /* Apply PHY settings to address errata listed in
1852 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1853 * Silicon Errata and Data Sheet Clarification documents.
1854 *
1855 * Document notes: Before configuring the PHY MMD registers, it is
1856 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1857 * disabled by writing to register 0xN100-0xN101. After writing the
1858 * MMD registers, and after all errata workarounds that involve PHY
1859 * register settings, write register 0xN100-0xN101 again to enable
1860 * and restart auto-negotiation.
1861 */
1862 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1863 if (err)
1864 return err;
1865
1866 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1867 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1868
1869 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1870 if (err)
1871 return err;
1872 }
1873
1874 /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
1875 * in this switch shall be regarded as broken.
1876 */
1877 if (phydev->dev_flags & MICREL_NO_EEE)
1878 phydev->eee_broken_modes = -1;
1879
1880 err = genphy_restart_aneg(phydev);
1881 if (err)
1882 return err;
1883
1884 return kszphy_config_init(phydev);
1885}
1886
1887static int kszphy_get_sset_count(struct phy_device *phydev)
1888{
1889 return ARRAY_SIZE(kszphy_hw_stats);
1890}
1891
1892static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1893{
1894 int i;
1895
1896 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1897 strscpy(data + i * ETH_GSTRING_LEN,
1898 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1899 }
1900}
1901
1902static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1903{
1904 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1905 struct kszphy_priv *priv = phydev->priv;
1906 int val;
1907 u64 ret;
1908
1909 val = phy_read(phydev, stat.reg);
1910 if (val < 0) {
1911 ret = U64_MAX;
1912 } else {
1913 val = val & ((1 << stat.bits) - 1);
1914 priv->stats[i] += val;
1915 ret = priv->stats[i];
1916 }
1917
1918 return ret;
1919}
1920
1921static void kszphy_get_stats(struct phy_device *phydev,
1922 struct ethtool_stats *stats, u64 *data)
1923{
1924 int i;
1925
1926 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1927 data[i] = kszphy_get_stat(phydev, i);
1928}
1929
1930static int kszphy_suspend(struct phy_device *phydev)
1931{
1932 /* Disable PHY Interrupts */
1933 if (phy_interrupt_is_valid(phydev)) {
1934 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1935 if (phydev->drv->config_intr)
1936 phydev->drv->config_intr(phydev);
1937 }
1938
1939 return genphy_suspend(phydev);
1940}
1941
1942static void kszphy_parse_led_mode(struct phy_device *phydev)
1943{
1944 const struct kszphy_type *type = phydev->drv->driver_data;
1945 const struct device_node *np = phydev->mdio.dev.of_node;
1946 struct kszphy_priv *priv = phydev->priv;
1947 int ret;
1948
1949 if (type && type->led_mode_reg) {
1950 ret = of_property_read_u32(np, "micrel,led-mode",
1951 &priv->led_mode);
1952
1953 if (ret)
1954 priv->led_mode = -1;
1955
1956 if (priv->led_mode > 3) {
1957 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1958 priv->led_mode);
1959 priv->led_mode = -1;
1960 }
1961 } else {
1962 priv->led_mode = -1;
1963 }
1964}
1965
1966static int kszphy_resume(struct phy_device *phydev)
1967{
1968 int ret;
1969
1970 genphy_resume(phydev);
1971
1972 /* After switching from power-down to normal mode, an internal global
1973 * reset is automatically generated. Wait a minimum of 1 ms before
1974 * read/write access to the PHY registers.
1975 */
1976 usleep_range(1000, 2000);
1977
1978 ret = kszphy_config_reset(phydev);
1979 if (ret)
1980 return ret;
1981
1982 /* Enable PHY Interrupts */
1983 if (phy_interrupt_is_valid(phydev)) {
1984 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1985 if (phydev->drv->config_intr)
1986 phydev->drv->config_intr(phydev);
1987 }
1988
1989 return 0;
1990}
1991
1992static int kszphy_probe(struct phy_device *phydev)
1993{
1994 const struct kszphy_type *type = phydev->drv->driver_data;
1995 const struct device_node *np = phydev->mdio.dev.of_node;
1996 struct kszphy_priv *priv;
1997 struct clk *clk;
1998
1999 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2000 if (!priv)
2001 return -ENOMEM;
2002
2003 phydev->priv = priv;
2004
2005 priv->type = type;
2006
2007 kszphy_parse_led_mode(phydev);
2008
2009 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
2010 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2011 if (!IS_ERR_OR_NULL(clk)) {
2012 unsigned long rate = clk_get_rate(clk);
2013 bool rmii_ref_clk_sel_25_mhz;
2014
2015 if (type)
2016 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2017 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2018 "micrel,rmii-reference-clock-select-25-mhz");
2019
2020 if (rate > 24500000 && rate < 25500000) {
2021 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2022 } else if (rate > 49500000 && rate < 50500000) {
2023 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2024 } else {
2025 phydev_err(phydev, "Clock rate out of range: %ld\n",
2026 rate);
2027 return -EINVAL;
2028 }
2029 } else if (!clk) {
2030 /* unnamed clock from the generic ethernet-phy binding */
2031 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
2032 if (IS_ERR(clk))
2033 return PTR_ERR(clk);
2034 }
2035
2036 if (ksz8041_fiber_mode(phydev))
2037 phydev->port = PORT_FIBRE;
2038
2039 /* Support legacy board-file configuration */
2040 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2041 priv->rmii_ref_clk_sel = true;
2042 priv->rmii_ref_clk_sel_val = true;
2043 }
2044
2045 return 0;
2046}
2047
2048static int lan8814_cable_test_start(struct phy_device *phydev)
2049{
2050 /* If autoneg is enabled, we won't be able to test cross pair
2051 * short. In this case, the PHY will "detect" a link and
2052 * confuse the internal state machine - disable auto neg here.
2053 * Set the speed to 1000mbit and full duplex.
2054 */
2055 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2056 BMCR_SPEED1000 | BMCR_FULLDPLX);
2057}
2058
2059static int ksz886x_cable_test_start(struct phy_device *phydev)
2060{
2061 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2062 return -EOPNOTSUPP;
2063
2064 /* If autoneg is enabled, we won't be able to test cross pair
2065 * short. In this case, the PHY will "detect" a link and
2066 * confuse the internal state machine - disable auto neg here.
2067 * If autoneg is disabled, we should set the speed to 10mbit.
2068 */
2069 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2070}
2071
2072static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2073{
2074 switch (FIELD_GET(mask, status)) {
2075 case KSZ8081_LMD_STAT_NORMAL:
2076 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2077 case KSZ8081_LMD_STAT_SHORT:
2078 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2079 case KSZ8081_LMD_STAT_OPEN:
2080 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2081 case KSZ8081_LMD_STAT_FAIL:
2082 fallthrough;
2083 default:
2084 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2085 }
2086}
2087
2088static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2089{
2090 return FIELD_GET(mask, status) ==
2091 KSZ8081_LMD_STAT_FAIL;
2092}
2093
2094static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2095{
2096 switch (FIELD_GET(mask, status)) {
2097 case KSZ8081_LMD_STAT_OPEN:
2098 fallthrough;
2099 case KSZ8081_LMD_STAT_SHORT:
2100 return true;
2101 }
2102 return false;
2103}
2104
2105static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2106 u16 status, u16 data_mask)
2107{
2108 int dt;
2109
2110 /* According to the data sheet the distance to the fault is
2111 * DELTA_TIME * 0.4 meters for ksz phys.
2112 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2113 */
2114 dt = FIELD_GET(data_mask, status);
2115
2116 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2117 return ((dt - 22) * 800) / 10;
2118 else
2119 return (dt * 400) / 10;
2120}
2121
2122static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2123{
2124 const struct kszphy_type *type = phydev->drv->driver_data;
2125 int val, ret;
2126
2127 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2128 !(val & KSZ8081_LMD_ENABLE_TEST),
2129 30000, 100000, true);
2130
2131 return ret < 0 ? ret : 0;
2132}
2133
2134static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2135{
2136 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2137 ETHTOOL_A_CABLE_PAIR_B,
2138 ETHTOOL_A_CABLE_PAIR_C,
2139 ETHTOOL_A_CABLE_PAIR_D,
2140 };
2141 u32 fault_length;
2142 int ret;
2143 int val;
2144
2145 val = KSZ8081_LMD_ENABLE_TEST;
2146 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2147
2148 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2149 if (ret < 0)
2150 return ret;
2151
2152 ret = ksz886x_cable_test_wait_for_completion(phydev);
2153 if (ret)
2154 return ret;
2155
2156 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2157 if (val < 0)
2158 return val;
2159
2160 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2161 return -EAGAIN;
2162
2163 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2164 ksz886x_cable_test_result_trans(val,
2165 LAN8814_CABLE_DIAG_STAT_MASK
2166 ));
2167 if (ret)
2168 return ret;
2169
2170 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2171 return 0;
2172
2173 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2174 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2175
2176 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2177}
2178
2179static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2180{
2181 static const int ethtool_pair[] = {
2182 ETHTOOL_A_CABLE_PAIR_A,
2183 ETHTOOL_A_CABLE_PAIR_B,
2184 };
2185 int ret, val, mdix;
2186 u32 fault_length;
2187
2188 /* There is no way to choice the pair, like we do one ksz9031.
2189 * We can workaround this limitation by using the MDI-X functionality.
2190 */
2191 if (pair == 0)
2192 mdix = ETH_TP_MDI;
2193 else
2194 mdix = ETH_TP_MDI_X;
2195
2196 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2197 case PHY_ID_KSZ8081:
2198 ret = ksz8081_config_mdix(phydev, mdix);
2199 break;
2200 case PHY_ID_KSZ886X:
2201 ret = ksz886x_config_mdix(phydev, mdix);
2202 break;
2203 default:
2204 ret = -ENODEV;
2205 }
2206
2207 if (ret)
2208 return ret;
2209
2210 /* Now we are ready to fire. This command will send a 100ns pulse
2211 * to the pair.
2212 */
2213 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2214 if (ret)
2215 return ret;
2216
2217 ret = ksz886x_cable_test_wait_for_completion(phydev);
2218 if (ret)
2219 return ret;
2220
2221 val = phy_read(phydev, KSZ8081_LMD);
2222 if (val < 0)
2223 return val;
2224
2225 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2226 return -EAGAIN;
2227
2228 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2229 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2230 if (ret)
2231 return ret;
2232
2233 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2234 return 0;
2235
2236 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2237
2238 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2239}
2240
2241static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2242 bool *finished)
2243{
2244 const struct kszphy_type *type = phydev->drv->driver_data;
2245 unsigned long pair_mask = type->pair_mask;
2246 int retries = 20;
2247 int ret = 0;
2248 int pair;
2249
2250 *finished = false;
2251
2252 /* Try harder if link partner is active */
2253 while (pair_mask && retries--) {
2254 for_each_set_bit(pair, &pair_mask, 4) {
2255 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2256 ret = lan8814_cable_test_one_pair(phydev, pair);
2257 else
2258 ret = ksz886x_cable_test_one_pair(phydev, pair);
2259 if (ret == -EAGAIN)
2260 continue;
2261 if (ret < 0)
2262 return ret;
2263 clear_bit(pair, &pair_mask);
2264 }
2265 /* If link partner is in autonegotiation mode it will send 2ms
2266 * of FLPs with at least 6ms of silence.
2267 * Add 2ms sleep to have better chances to hit this silence.
2268 */
2269 if (pair_mask)
2270 msleep(2);
2271 }
2272
2273 *finished = true;
2274
2275 return ret;
2276}
2277
2278#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2279#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2280#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2281
2282#define LAN8814_QSGMII_SOFT_RESET 0x43
2283#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2284#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2285#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2286#define LAN8814_ALIGN_SWAP 0x4a
2287#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2288#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2289
2290#define LAN8804_ALIGN_SWAP 0x4a
2291#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2292#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2293#define LAN8814_CLOCK_MANAGEMENT 0xd
2294#define LAN8814_LINK_QUALITY 0x8e
2295
2296static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2297{
2298 int data;
2299
2300 phy_lock_mdio_bus(phydev);
2301 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2302 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2303 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2304 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2305 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2306 phy_unlock_mdio_bus(phydev);
2307
2308 return data;
2309}
2310
2311static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2312 u16 val)
2313{
2314 phy_lock_mdio_bus(phydev);
2315 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2316 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2317 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2318 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2319
2320 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2321 if (val != 0)
2322 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2323 val);
2324 phy_unlock_mdio_bus(phydev);
2325 return val;
2326}
2327
2328static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2329{
2330 u16 val = 0;
2331
2332 if (enable)
2333 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2334 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2335 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2336 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2337
2338 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2339}
2340
2341static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2342 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2343{
2344 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2345 *seconds = (*seconds << 16) |
2346 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2347
2348 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2349 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2350 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2351
2352 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2353}
2354
2355static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2356 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2357{
2358 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2359 *seconds = *seconds << 16 |
2360 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2361
2362 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2363 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2364 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2365
2366 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2367}
2368
2369static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2370{
2371 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2372 struct phy_device *phydev = ptp_priv->phydev;
2373 struct lan8814_shared_priv *shared = phydev->shared->priv;
2374
2375 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2376 SOF_TIMESTAMPING_RX_HARDWARE |
2377 SOF_TIMESTAMPING_RAW_HARDWARE;
2378
2379 info->phc_index = ptp_clock_index(shared->ptp_clock);
2380
2381 info->tx_types =
2382 (1 << HWTSTAMP_TX_OFF) |
2383 (1 << HWTSTAMP_TX_ON) |
2384 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2385
2386 info->rx_filters =
2387 (1 << HWTSTAMP_FILTER_NONE) |
2388 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2389 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2390 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2391 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2392
2393 return 0;
2394}
2395
2396static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2397{
2398 int i;
2399
2400 for (i = 0; i < FIFO_SIZE; ++i)
2401 lanphy_read_page_reg(phydev, 5,
2402 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2403
2404 /* Read to clear overflow status bit */
2405 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2406}
2407
2408static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2409 struct kernel_hwtstamp_config *config,
2410 struct netlink_ext_ack *extack)
2411{
2412 struct kszphy_ptp_priv *ptp_priv =
2413 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2414 struct phy_device *phydev = ptp_priv->phydev;
2415 struct lan8814_shared_priv *shared = phydev->shared->priv;
2416 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2417 int txcfg = 0, rxcfg = 0;
2418 int pkt_ts_enable;
2419
2420 ptp_priv->hwts_tx_type = config->tx_type;
2421 ptp_priv->rx_filter = config->rx_filter;
2422
2423 switch (config->rx_filter) {
2424 case HWTSTAMP_FILTER_NONE:
2425 ptp_priv->layer = 0;
2426 ptp_priv->version = 0;
2427 break;
2428 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2429 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2430 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2431 ptp_priv->layer = PTP_CLASS_L4;
2432 ptp_priv->version = PTP_CLASS_V2;
2433 break;
2434 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2435 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2436 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2437 ptp_priv->layer = PTP_CLASS_L2;
2438 ptp_priv->version = PTP_CLASS_V2;
2439 break;
2440 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2441 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2442 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2443 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2444 ptp_priv->version = PTP_CLASS_V2;
2445 break;
2446 default:
2447 return -ERANGE;
2448 }
2449
2450 if (ptp_priv->layer & PTP_CLASS_L2) {
2451 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2452 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2453 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2454 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2455 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2456 }
2457 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2458 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2459
2460 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2461 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2462 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2463 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2464
2465 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2466 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2467 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2468
2469 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2470 lan8814_config_ts_intr(ptp_priv->phydev, true);
2471 else
2472 lan8814_config_ts_intr(ptp_priv->phydev, false);
2473
2474 mutex_lock(&shared->shared_lock);
2475 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2476 shared->ref++;
2477 else
2478 shared->ref--;
2479
2480 if (shared->ref)
2481 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2482 PTP_CMD_CTL_PTP_ENABLE_);
2483 else
2484 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2485 PTP_CMD_CTL_PTP_DISABLE_);
2486 mutex_unlock(&shared->shared_lock);
2487
2488 /* In case of multiple starts and stops, these needs to be cleared */
2489 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2490 list_del(&rx_ts->list);
2491 kfree(rx_ts);
2492 }
2493 skb_queue_purge(&ptp_priv->rx_queue);
2494 skb_queue_purge(&ptp_priv->tx_queue);
2495
2496 lan8814_flush_fifo(ptp_priv->phydev, false);
2497 lan8814_flush_fifo(ptp_priv->phydev, true);
2498
2499 return 0;
2500}
2501
2502static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2503 struct sk_buff *skb, int type)
2504{
2505 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2506
2507 switch (ptp_priv->hwts_tx_type) {
2508 case HWTSTAMP_TX_ONESTEP_SYNC:
2509 if (ptp_msg_is_sync(skb, type)) {
2510 kfree_skb(skb);
2511 return;
2512 }
2513 fallthrough;
2514 case HWTSTAMP_TX_ON:
2515 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2516 skb_queue_tail(&ptp_priv->tx_queue, skb);
2517 break;
2518 case HWTSTAMP_TX_OFF:
2519 default:
2520 kfree_skb(skb);
2521 break;
2522 }
2523}
2524
2525static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2526{
2527 struct ptp_header *ptp_header;
2528 u32 type;
2529
2530 skb_push(skb, ETH_HLEN);
2531 type = ptp_classify_raw(skb);
2532 ptp_header = ptp_parse_header(skb, type);
2533 skb_pull_inline(skb, ETH_HLEN);
2534
2535 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2536}
2537
2538static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2539 struct sk_buff *skb)
2540{
2541 struct skb_shared_hwtstamps *shhwtstamps;
2542 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2543 unsigned long flags;
2544 bool ret = false;
2545 u16 skb_sig;
2546
2547 lan8814_get_sig_rx(skb, &skb_sig);
2548
2549 /* Iterate over all RX timestamps and match it with the received skbs */
2550 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2551 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2552 /* Check if we found the signature we were looking for. */
2553 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2554 continue;
2555
2556 shhwtstamps = skb_hwtstamps(skb);
2557 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2558 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2559 rx_ts->nsec);
2560 list_del(&rx_ts->list);
2561 kfree(rx_ts);
2562
2563 ret = true;
2564 break;
2565 }
2566 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2567
2568 if (ret)
2569 netif_rx(skb);
2570 return ret;
2571}
2572
2573static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2574{
2575 struct kszphy_ptp_priv *ptp_priv =
2576 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2577
2578 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2579 type == PTP_CLASS_NONE)
2580 return false;
2581
2582 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2583 return false;
2584
2585 /* If we failed to match then add it to the queue for when the timestamp
2586 * will come
2587 */
2588 if (!lan8814_match_rx_skb(ptp_priv, skb))
2589 skb_queue_tail(&ptp_priv->rx_queue, skb);
2590
2591 return true;
2592}
2593
2594static void lan8814_ptp_clock_set(struct phy_device *phydev,
2595 u32 seconds, u32 nano_seconds)
2596{
2597 u32 sec_low, sec_high, nsec_low, nsec_high;
2598
2599 sec_low = seconds & 0xffff;
2600 sec_high = (seconds >> 16) & 0xffff;
2601 nsec_low = nano_seconds & 0xffff;
2602 nsec_high = (nano_seconds >> 16) & 0x3fff;
2603
2604 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2605 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2606 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2607 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2608
2609 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2610}
2611
2612static void lan8814_ptp_clock_get(struct phy_device *phydev,
2613 u32 *seconds, u32 *nano_seconds)
2614{
2615 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2616
2617 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2618 *seconds = (*seconds << 16) |
2619 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2620
2621 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2622 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2623 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2624}
2625
2626static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2627 struct timespec64 *ts)
2628{
2629 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2630 ptp_clock_info);
2631 struct phy_device *phydev = shared->phydev;
2632 u32 nano_seconds;
2633 u32 seconds;
2634
2635 mutex_lock(&shared->shared_lock);
2636 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2637 mutex_unlock(&shared->shared_lock);
2638 ts->tv_sec = seconds;
2639 ts->tv_nsec = nano_seconds;
2640
2641 return 0;
2642}
2643
2644static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2645 const struct timespec64 *ts)
2646{
2647 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2648 ptp_clock_info);
2649 struct phy_device *phydev = shared->phydev;
2650
2651 mutex_lock(&shared->shared_lock);
2652 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2653 mutex_unlock(&shared->shared_lock);
2654
2655 return 0;
2656}
2657
2658static void lan8814_ptp_clock_step(struct phy_device *phydev,
2659 s64 time_step_ns)
2660{
2661 u32 nano_seconds_step;
2662 u64 abs_time_step_ns;
2663 u32 unsigned_seconds;
2664 u32 nano_seconds;
2665 u32 remainder;
2666 s32 seconds;
2667
2668 if (time_step_ns > 15000000000LL) {
2669 /* convert to clock set */
2670 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2671 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2672 &remainder);
2673 nano_seconds += remainder;
2674 if (nano_seconds >= 1000000000) {
2675 unsigned_seconds++;
2676 nano_seconds -= 1000000000;
2677 }
2678 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2679 return;
2680 } else if (time_step_ns < -15000000000LL) {
2681 /* convert to clock set */
2682 time_step_ns = -time_step_ns;
2683
2684 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2685 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2686 &remainder);
2687 nano_seconds_step = remainder;
2688 if (nano_seconds < nano_seconds_step) {
2689 unsigned_seconds--;
2690 nano_seconds += 1000000000;
2691 }
2692 nano_seconds -= nano_seconds_step;
2693 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2694 nano_seconds);
2695 return;
2696 }
2697
2698 /* do clock step */
2699 if (time_step_ns >= 0) {
2700 abs_time_step_ns = (u64)time_step_ns;
2701 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2702 &remainder);
2703 nano_seconds = remainder;
2704 } else {
2705 abs_time_step_ns = (u64)(-time_step_ns);
2706 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2707 &remainder));
2708 nano_seconds = remainder;
2709 if (nano_seconds > 0) {
2710 /* subtracting nano seconds is not allowed
2711 * convert to subtracting from seconds,
2712 * and adding to nanoseconds
2713 */
2714 seconds--;
2715 nano_seconds = (1000000000 - nano_seconds);
2716 }
2717 }
2718
2719 if (nano_seconds > 0) {
2720 /* add 8 ns to cover the likely normal increment */
2721 nano_seconds += 8;
2722 }
2723
2724 if (nano_seconds >= 1000000000) {
2725 /* carry into seconds */
2726 seconds++;
2727 nano_seconds -= 1000000000;
2728 }
2729
2730 while (seconds) {
2731 if (seconds > 0) {
2732 u32 adjustment_value = (u32)seconds;
2733 u16 adjustment_value_lo, adjustment_value_hi;
2734
2735 if (adjustment_value > 0xF)
2736 adjustment_value = 0xF;
2737
2738 adjustment_value_lo = adjustment_value & 0xffff;
2739 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2740
2741 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2742 adjustment_value_lo);
2743 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2744 PTP_LTC_STEP_ADJ_DIR_ |
2745 adjustment_value_hi);
2746 seconds -= ((s32)adjustment_value);
2747 } else {
2748 u32 adjustment_value = (u32)(-seconds);
2749 u16 adjustment_value_lo, adjustment_value_hi;
2750
2751 if (adjustment_value > 0xF)
2752 adjustment_value = 0xF;
2753
2754 adjustment_value_lo = adjustment_value & 0xffff;
2755 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2756
2757 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2758 adjustment_value_lo);
2759 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2760 adjustment_value_hi);
2761 seconds += ((s32)adjustment_value);
2762 }
2763 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2764 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2765 }
2766 if (nano_seconds) {
2767 u16 nano_seconds_lo;
2768 u16 nano_seconds_hi;
2769
2770 nano_seconds_lo = nano_seconds & 0xffff;
2771 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2772
2773 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2774 nano_seconds_lo);
2775 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2776 PTP_LTC_STEP_ADJ_DIR_ |
2777 nano_seconds_hi);
2778 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2779 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2780 }
2781}
2782
2783static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2784{
2785 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2786 ptp_clock_info);
2787 struct phy_device *phydev = shared->phydev;
2788
2789 mutex_lock(&shared->shared_lock);
2790 lan8814_ptp_clock_step(phydev, delta);
2791 mutex_unlock(&shared->shared_lock);
2792
2793 return 0;
2794}
2795
2796static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2797{
2798 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2799 ptp_clock_info);
2800 struct phy_device *phydev = shared->phydev;
2801 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2802 bool positive = true;
2803 u32 kszphy_rate_adj;
2804
2805 if (scaled_ppm < 0) {
2806 scaled_ppm = -scaled_ppm;
2807 positive = false;
2808 }
2809
2810 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2811 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2812
2813 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2814 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2815
2816 if (positive)
2817 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2818
2819 mutex_lock(&shared->shared_lock);
2820 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2821 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2822 mutex_unlock(&shared->shared_lock);
2823
2824 return 0;
2825}
2826
2827static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2828{
2829 struct ptp_header *ptp_header;
2830 u32 type;
2831
2832 type = ptp_classify_raw(skb);
2833 ptp_header = ptp_parse_header(skb, type);
2834
2835 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2836}
2837
2838static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2839 u32 seconds, u32 nsec, u16 seq_id)
2840{
2841 struct skb_shared_hwtstamps shhwtstamps;
2842 struct sk_buff *skb, *skb_tmp;
2843 unsigned long flags;
2844 bool ret = false;
2845 u16 skb_sig;
2846
2847 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2848 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2849 lan8814_get_sig_tx(skb, &skb_sig);
2850
2851 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2852 continue;
2853
2854 __skb_unlink(skb, &ptp_priv->tx_queue);
2855 ret = true;
2856 break;
2857 }
2858 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2859
2860 if (ret) {
2861 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2862 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2863 skb_complete_tx_timestamp(skb, &shhwtstamps);
2864 }
2865}
2866
2867static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2868{
2869 struct phy_device *phydev = ptp_priv->phydev;
2870 u32 seconds, nsec;
2871 u16 seq_id;
2872
2873 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2874 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2875}
2876
2877static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2878{
2879 struct phy_device *phydev = ptp_priv->phydev;
2880 u32 reg;
2881
2882 do {
2883 lan8814_dequeue_tx_skb(ptp_priv);
2884
2885 /* If other timestamps are available in the FIFO,
2886 * process them.
2887 */
2888 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2889 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2890}
2891
2892static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2893 struct lan8814_ptp_rx_ts *rx_ts)
2894{
2895 struct skb_shared_hwtstamps *shhwtstamps;
2896 struct sk_buff *skb, *skb_tmp;
2897 unsigned long flags;
2898 bool ret = false;
2899 u16 skb_sig;
2900
2901 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2902 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2903 lan8814_get_sig_rx(skb, &skb_sig);
2904
2905 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2906 continue;
2907
2908 __skb_unlink(skb, &ptp_priv->rx_queue);
2909
2910 ret = true;
2911 break;
2912 }
2913 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2914
2915 if (ret) {
2916 shhwtstamps = skb_hwtstamps(skb);
2917 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2918 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2919 netif_rx(skb);
2920 }
2921
2922 return ret;
2923}
2924
2925static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2926 struct lan8814_ptp_rx_ts *rx_ts)
2927{
2928 unsigned long flags;
2929
2930 /* If we failed to match the skb add it to the queue for when
2931 * the frame will come
2932 */
2933 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2934 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2935 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2936 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2937 } else {
2938 kfree(rx_ts);
2939 }
2940}
2941
2942static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2943{
2944 struct phy_device *phydev = ptp_priv->phydev;
2945 struct lan8814_ptp_rx_ts *rx_ts;
2946 u32 reg;
2947
2948 do {
2949 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2950 if (!rx_ts)
2951 return;
2952
2953 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2954 &rx_ts->seq_id);
2955 lan8814_match_rx_ts(ptp_priv, rx_ts);
2956
2957 /* If other timestamps are available in the FIFO,
2958 * process them.
2959 */
2960 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2961 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2962}
2963
2964static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2965{
2966 struct kszphy_priv *priv = phydev->priv;
2967 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2968
2969 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2970 lan8814_get_tx_ts(ptp_priv);
2971
2972 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2973 lan8814_get_rx_ts(ptp_priv);
2974
2975 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2976 lan8814_flush_fifo(phydev, true);
2977 skb_queue_purge(&ptp_priv->tx_queue);
2978 }
2979
2980 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2981 lan8814_flush_fifo(phydev, false);
2982 skb_queue_purge(&ptp_priv->rx_queue);
2983 }
2984}
2985
2986static int lan8804_config_init(struct phy_device *phydev)
2987{
2988 int val;
2989
2990 /* MDI-X setting for swap A,B transmit */
2991 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2992 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2993 val |= LAN8804_ALIGN_TX_A_B_SWAP;
2994 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2995
2996 /* Make sure that the PHY will not stop generating the clock when the
2997 * link partner goes down
2998 */
2999 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3000 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3001
3002 return 0;
3003}
3004
3005static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3006{
3007 int status;
3008
3009 status = phy_read(phydev, LAN8814_INTS);
3010 if (status < 0) {
3011 phy_error(phydev);
3012 return IRQ_NONE;
3013 }
3014
3015 if (status > 0)
3016 phy_trigger_machine(phydev);
3017
3018 return IRQ_HANDLED;
3019}
3020
3021#define LAN8804_OUTPUT_CONTROL 25
3022#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3023#define LAN8804_CONTROL 31
3024#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3025
3026static int lan8804_config_intr(struct phy_device *phydev)
3027{
3028 int err;
3029
3030 /* This is an internal PHY of lan966x and is not possible to change the
3031 * polarity on the GIC found in lan966x, therefore change the polarity
3032 * of the interrupt in the PHY from being active low instead of active
3033 * high.
3034 */
3035 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3036
3037 /* By default interrupt buffer is open-drain in which case the interrupt
3038 * can be active only low. Therefore change the interrupt buffer to be
3039 * push-pull to be able to change interrupt polarity
3040 */
3041 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3042 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3043
3044 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3045 err = phy_read(phydev, LAN8814_INTS);
3046 if (err < 0)
3047 return err;
3048
3049 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3050 if (err)
3051 return err;
3052 } else {
3053 err = phy_write(phydev, LAN8814_INTC, 0);
3054 if (err)
3055 return err;
3056
3057 err = phy_read(phydev, LAN8814_INTS);
3058 if (err < 0)
3059 return err;
3060 }
3061
3062 return 0;
3063}
3064
3065static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3066{
3067 int ret = IRQ_NONE;
3068 int irq_status;
3069
3070 irq_status = phy_read(phydev, LAN8814_INTS);
3071 if (irq_status < 0) {
3072 phy_error(phydev);
3073 return IRQ_NONE;
3074 }
3075
3076 if (irq_status & LAN8814_INT_LINK) {
3077 phy_trigger_machine(phydev);
3078 ret = IRQ_HANDLED;
3079 }
3080
3081 while (true) {
3082 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3083 if (!irq_status)
3084 break;
3085
3086 lan8814_handle_ptp_interrupt(phydev, irq_status);
3087 ret = IRQ_HANDLED;
3088 }
3089
3090 return ret;
3091}
3092
3093static int lan8814_ack_interrupt(struct phy_device *phydev)
3094{
3095 /* bit[12..0] int status, which is a read and clear register. */
3096 int rc;
3097
3098 rc = phy_read(phydev, LAN8814_INTS);
3099
3100 return (rc < 0) ? rc : 0;
3101}
3102
3103static int lan8814_config_intr(struct phy_device *phydev)
3104{
3105 int err;
3106
3107 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3108 LAN8814_INTR_CTRL_REG_POLARITY |
3109 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3110
3111 /* enable / disable interrupts */
3112 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3113 err = lan8814_ack_interrupt(phydev);
3114 if (err)
3115 return err;
3116
3117 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3118 } else {
3119 err = phy_write(phydev, LAN8814_INTC, 0);
3120 if (err)
3121 return err;
3122
3123 err = lan8814_ack_interrupt(phydev);
3124 }
3125
3126 return err;
3127}
3128
3129static void lan8814_ptp_init(struct phy_device *phydev)
3130{
3131 struct kszphy_priv *priv = phydev->priv;
3132 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3133 u32 temp;
3134
3135 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3136 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3137 return;
3138
3139 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3140
3141 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3142 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3143 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3144
3145 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3146 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3147 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3148
3149 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3150 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3151
3152 /* Removing default registers configs related to L2 and IP */
3153 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3154 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3155 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3156 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3157
3158 /* Disable checking for minorVersionPTP field */
3159 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3160 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3161 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3162 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3163
3164 skb_queue_head_init(&ptp_priv->tx_queue);
3165 skb_queue_head_init(&ptp_priv->rx_queue);
3166 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3167 spin_lock_init(&ptp_priv->rx_ts_lock);
3168
3169 ptp_priv->phydev = phydev;
3170
3171 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3172 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3173 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3174 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3175
3176 phydev->mii_ts = &ptp_priv->mii_ts;
3177}
3178
3179static int lan8814_ptp_probe_once(struct phy_device *phydev)
3180{
3181 struct lan8814_shared_priv *shared = phydev->shared->priv;
3182
3183 /* Initialise shared lock for clock*/
3184 mutex_init(&shared->shared_lock);
3185
3186 shared->ptp_clock_info.owner = THIS_MODULE;
3187 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3188 shared->ptp_clock_info.max_adj = 31249999;
3189 shared->ptp_clock_info.n_alarm = 0;
3190 shared->ptp_clock_info.n_ext_ts = 0;
3191 shared->ptp_clock_info.n_pins = 0;
3192 shared->ptp_clock_info.pps = 0;
3193 shared->ptp_clock_info.pin_config = NULL;
3194 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3195 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3196 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3197 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3198 shared->ptp_clock_info.getcrosststamp = NULL;
3199
3200 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3201 &phydev->mdio.dev);
3202 if (IS_ERR(shared->ptp_clock)) {
3203 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3204 PTR_ERR(shared->ptp_clock));
3205 return -EINVAL;
3206 }
3207
3208 /* Check if PHC support is missing at the configuration level */
3209 if (!shared->ptp_clock)
3210 return 0;
3211
3212 phydev_dbg(phydev, "successfully registered ptp clock\n");
3213
3214 shared->phydev = phydev;
3215
3216 /* The EP.4 is shared between all the PHYs in the package and also it
3217 * can be accessed by any of the PHYs
3218 */
3219 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3220 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3221 PTP_OPERATING_MODE_STANDALONE_);
3222
3223 return 0;
3224}
3225
3226static void lan8814_setup_led(struct phy_device *phydev, int val)
3227{
3228 int temp;
3229
3230 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3231
3232 if (val)
3233 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3234 else
3235 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3236
3237 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3238}
3239
3240static int lan8814_config_init(struct phy_device *phydev)
3241{
3242 struct kszphy_priv *lan8814 = phydev->priv;
3243 int val;
3244
3245 /* Reset the PHY */
3246 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3247 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3248 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3249
3250 /* Disable ANEG with QSGMII PCS Host side */
3251 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3252 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3253 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3254
3255 /* MDI-X setting for swap A,B transmit */
3256 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3257 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3258 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3259 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3260
3261 if (lan8814->led_mode >= 0)
3262 lan8814_setup_led(phydev, lan8814->led_mode);
3263
3264 return 0;
3265}
3266
3267/* It is expected that there will not be any 'lan8814_take_coma_mode'
3268 * function called in suspend. Because the GPIO line can be shared, so if one of
3269 * the phys goes back in coma mode, then all the other PHYs will go, which is
3270 * wrong.
3271 */
3272static int lan8814_release_coma_mode(struct phy_device *phydev)
3273{
3274 struct gpio_desc *gpiod;
3275
3276 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3277 GPIOD_OUT_HIGH_OPEN_DRAIN |
3278 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3279 if (IS_ERR(gpiod))
3280 return PTR_ERR(gpiod);
3281
3282 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3283 gpiod_set_value_cansleep(gpiod, 0);
3284
3285 return 0;
3286}
3287
3288static int lan8814_probe(struct phy_device *phydev)
3289{
3290 const struct kszphy_type *type = phydev->drv->driver_data;
3291 struct kszphy_priv *priv;
3292 u16 addr;
3293 int err;
3294
3295 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3296 if (!priv)
3297 return -ENOMEM;
3298
3299 phydev->priv = priv;
3300
3301 priv->type = type;
3302
3303 kszphy_parse_led_mode(phydev);
3304
3305 /* Strap-in value for PHY address, below register read gives starting
3306 * phy address value
3307 */
3308 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3309 devm_phy_package_join(&phydev->mdio.dev, phydev,
3310 addr, sizeof(struct lan8814_shared_priv));
3311
3312 if (phy_package_init_once(phydev)) {
3313 err = lan8814_release_coma_mode(phydev);
3314 if (err)
3315 return err;
3316
3317 err = lan8814_ptp_probe_once(phydev);
3318 if (err)
3319 return err;
3320 }
3321
3322 lan8814_ptp_init(phydev);
3323
3324 return 0;
3325}
3326
3327#define LAN8841_MMD_TIMER_REG 0
3328#define LAN8841_MMD0_REGISTER_17 17
3329#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
3330#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
3331#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
3332#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
3333#define LAN8841_MMD_ANALOG_REG 28
3334#define LAN8841_ANALOG_CONTROL_1 1
3335#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
3336#define LAN8841_ANALOG_CONTROL_10 13
3337#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
3338#define LAN8841_ANALOG_CONTROL_11 14
3339#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
3340#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3341#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3342#define LAN8841_BTRX_POWER_DOWN 70
3343#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
3344#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
3345#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
3346#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
3347#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
3348#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
3349#define LAN8841_ADC_CHANNEL_MASK 198
3350#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
3351#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
3352#define LAN8841_PTP_RX_VERSION 374
3353#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
3354#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
3355#define LAN8841_PTP_TX_VERSION 438
3356#define LAN8841_PTP_CMD_CTL 256
3357#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
3358#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
3359#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
3360#define LAN8841_PTP_RX_PARSE_CONFIG 368
3361#define LAN8841_PTP_TX_PARSE_CONFIG 432
3362#define LAN8841_PTP_RX_MODE 381
3363#define LAN8841_PTP_INSERT_TS_EN BIT(0)
3364#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
3365
3366static int lan8841_config_init(struct phy_device *phydev)
3367{
3368 int ret;
3369
3370 ret = ksz9131_config_init(phydev);
3371 if (ret)
3372 return ret;
3373
3374 /* Initialize the HW by resetting everything */
3375 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3376 LAN8841_PTP_CMD_CTL,
3377 LAN8841_PTP_CMD_CTL_PTP_RESET,
3378 LAN8841_PTP_CMD_CTL_PTP_RESET);
3379
3380 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3381 LAN8841_PTP_CMD_CTL,
3382 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3383 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3384
3385 /* Don't process any frames */
3386 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3387 LAN8841_PTP_RX_PARSE_CONFIG, 0);
3388 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3389 LAN8841_PTP_TX_PARSE_CONFIG, 0);
3390 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3391 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3392 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3393 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3394 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3395 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3396 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3397 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3398
3399 /* Disable checking for minorVersionPTP field */
3400 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3401 LAN8841_PTP_RX_VERSION, 0xff00);
3402 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3403 LAN8841_PTP_TX_VERSION, 0xff00);
3404
3405 /* 100BT Clause 40 improvenent errata */
3406 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3407 LAN8841_ANALOG_CONTROL_1,
3408 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3409 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3410 LAN8841_ANALOG_CONTROL_10,
3411 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3412
3413 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3414 * Magnetics
3415 */
3416 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3417 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3418 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3419 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3420 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3421 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3422 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3423 LAN8841_BTRX_POWER_DOWN,
3424 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3425 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3426 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3427 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3428 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3429 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3430 }
3431
3432 /* LDO Adjustment errata */
3433 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3434 LAN8841_ANALOG_CONTROL_11,
3435 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3436
3437 /* 100BT RGMII latency tuning errata */
3438 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3439 LAN8841_ADC_CHANNEL_MASK, 0x0);
3440 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3441 LAN8841_MMD0_REGISTER_17,
3442 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3443 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3444
3445 return 0;
3446}
3447
3448#define LAN8841_OUTPUT_CTRL 25
3449#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
3450#define LAN8841_INT_PTP BIT(9)
3451
3452static int lan8841_config_intr(struct phy_device *phydev)
3453{
3454 int err;
3455
3456 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3457 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3458
3459 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3460 err = phy_read(phydev, LAN8814_INTS);
3461 if (err)
3462 return err;
3463
3464 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3465 * even if it PTP is not enabled. Because the underneath blocks
3466 * will not enable the PTP so we will never get the PTP
3467 * interrupt.
3468 */
3469 err = phy_write(phydev, LAN8814_INTC,
3470 LAN8814_INT_LINK | LAN8841_INT_PTP);
3471 } else {
3472 err = phy_write(phydev, LAN8814_INTC, 0);
3473 if (err)
3474 return err;
3475
3476 err = phy_read(phydev, LAN8814_INTS);
3477 }
3478
3479 return err;
3480}
3481
3482#define LAN8841_PTP_TX_EGRESS_SEC_LO 453
3483#define LAN8841_PTP_TX_EGRESS_SEC_HI 452
3484#define LAN8841_PTP_TX_EGRESS_NS_LO 451
3485#define LAN8841_PTP_TX_EGRESS_NS_HI 450
3486#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
3487#define LAN8841_PTP_TX_MSG_HEADER2 455
3488
3489static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3490 u32 *sec, u32 *nsec, u16 *seq)
3491{
3492 struct phy_device *phydev = ptp_priv->phydev;
3493
3494 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3495 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3496 return false;
3497
3498 *nsec = ((*nsec & 0x3fff) << 16);
3499 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3500
3501 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3502 *sec = *sec << 16;
3503 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3504
3505 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3506
3507 return true;
3508}
3509
3510static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3511{
3512 u32 sec, nsec;
3513 u16 seq;
3514
3515 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3516 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3517}
3518
3519#define LAN8841_PTP_INT_STS 259
3520#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3521#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
3522#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
3523
3524static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3525{
3526 struct phy_device *phydev = ptp_priv->phydev;
3527 int i;
3528
3529 for (i = 0; i < FIFO_SIZE; ++i)
3530 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3531
3532 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3533}
3534
3535#define LAN8841_PTP_GPIO_CAP_STS 506
3536#define LAN8841_PTP_GPIO_SEL 327
3537#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
3538#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
3539#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
3540#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
3541#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
3542#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
3543#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
3544#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
3545#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
3546
3547static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3548{
3549 struct phy_device *phydev = ptp_priv->phydev;
3550 struct ptp_clock_event ptp_event = {0};
3551 int pin, ret, tmp;
3552 s32 sec, nsec;
3553
3554 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3555 if (pin == -1)
3556 return;
3557
3558 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3559 if (tmp < 0)
3560 return;
3561
3562 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3563 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3564 if (ret)
3565 return;
3566
3567 mutex_lock(&ptp_priv->ptp_lock);
3568 if (tmp & BIT(pin)) {
3569 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3570 sec <<= 16;
3571 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3572
3573 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3574 nsec <<= 16;
3575 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3576 } else {
3577 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3578 sec <<= 16;
3579 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3580
3581 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3582 nsec <<= 16;
3583 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3584 }
3585 mutex_unlock(&ptp_priv->ptp_lock);
3586 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3587 if (ret)
3588 return;
3589
3590 ptp_event.index = 0;
3591 ptp_event.timestamp = ktime_set(sec, nsec);
3592 ptp_event.type = PTP_CLOCK_EXTTS;
3593 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3594}
3595
3596static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3597{
3598 struct kszphy_priv *priv = phydev->priv;
3599 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3600 u16 status;
3601
3602 do {
3603 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3604
3605 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3606 lan8841_ptp_process_tx_ts(ptp_priv);
3607
3608 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3609 lan8841_gpio_process_cap(ptp_priv);
3610
3611 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3612 lan8841_ptp_flush_fifo(ptp_priv);
3613 skb_queue_purge(&ptp_priv->tx_queue);
3614 }
3615
3616 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3617 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3618 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3619}
3620
3621#define LAN8841_INTS_PTP BIT(9)
3622
3623static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3624{
3625 irqreturn_t ret = IRQ_NONE;
3626 int irq_status;
3627
3628 irq_status = phy_read(phydev, LAN8814_INTS);
3629 if (irq_status < 0) {
3630 phy_error(phydev);
3631 return IRQ_NONE;
3632 }
3633
3634 if (irq_status & LAN8814_INT_LINK) {
3635 phy_trigger_machine(phydev);
3636 ret = IRQ_HANDLED;
3637 }
3638
3639 if (irq_status & LAN8841_INTS_PTP) {
3640 lan8841_handle_ptp_interrupt(phydev);
3641 ret = IRQ_HANDLED;
3642 }
3643
3644 return ret;
3645}
3646
3647static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3648 struct ethtool_ts_info *info)
3649{
3650 struct kszphy_ptp_priv *ptp_priv;
3651
3652 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3653
3654 info->phc_index = ptp_priv->ptp_clock ?
3655 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3656 if (info->phc_index == -1)
3657 return 0;
3658
3659 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3660 SOF_TIMESTAMPING_RX_HARDWARE |
3661 SOF_TIMESTAMPING_RAW_HARDWARE;
3662
3663 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3664 (1 << HWTSTAMP_TX_ON) |
3665 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3666
3667 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3668 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3669 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3670 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3671
3672 return 0;
3673}
3674
3675#define LAN8841_PTP_INT_EN 260
3676#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
3677#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
3678
3679static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3680 bool enable)
3681{
3682 struct phy_device *phydev = ptp_priv->phydev;
3683
3684 if (enable) {
3685 /* Enable interrupts on the TX side */
3686 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3687 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3688 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3689 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3690 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3691
3692 /* Enable the modification of the frame on RX side,
3693 * this will add the ns and 2 bits of sec in the reserved field
3694 * of the PTP header
3695 */
3696 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3697 LAN8841_PTP_RX_MODE,
3698 LAN8841_PTP_INSERT_TS_EN |
3699 LAN8841_PTP_INSERT_TS_32BIT,
3700 LAN8841_PTP_INSERT_TS_EN |
3701 LAN8841_PTP_INSERT_TS_32BIT);
3702
3703 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3704 } else {
3705 /* Disable interrupts on the TX side */
3706 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3707 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3708 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3709
3710 /* Disable modification of the RX frames */
3711 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3712 LAN8841_PTP_RX_MODE,
3713 LAN8841_PTP_INSERT_TS_EN |
3714 LAN8841_PTP_INSERT_TS_32BIT, 0);
3715
3716 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3717 }
3718}
3719
3720#define LAN8841_PTP_RX_TIMESTAMP_EN 379
3721#define LAN8841_PTP_TX_TIMESTAMP_EN 443
3722#define LAN8841_PTP_TX_MOD 445
3723
3724static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
3725 struct kernel_hwtstamp_config *config,
3726 struct netlink_ext_ack *extack)
3727{
3728 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3729 struct phy_device *phydev = ptp_priv->phydev;
3730 int txcfg = 0, rxcfg = 0;
3731 int pkt_ts_enable;
3732
3733 ptp_priv->hwts_tx_type = config->tx_type;
3734 ptp_priv->rx_filter = config->rx_filter;
3735
3736 switch (config->rx_filter) {
3737 case HWTSTAMP_FILTER_NONE:
3738 ptp_priv->layer = 0;
3739 ptp_priv->version = 0;
3740 break;
3741 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3742 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3743 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3744 ptp_priv->layer = PTP_CLASS_L4;
3745 ptp_priv->version = PTP_CLASS_V2;
3746 break;
3747 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3748 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3749 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3750 ptp_priv->layer = PTP_CLASS_L2;
3751 ptp_priv->version = PTP_CLASS_V2;
3752 break;
3753 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3754 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3755 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3756 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3757 ptp_priv->version = PTP_CLASS_V2;
3758 break;
3759 default:
3760 return -ERANGE;
3761 }
3762
3763 /* Setup parsing of the frames and enable the timestamping for ptp
3764 * frames
3765 */
3766 if (ptp_priv->layer & PTP_CLASS_L2) {
3767 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3768 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3769 } else if (ptp_priv->layer & PTP_CLASS_L4) {
3770 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3771 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3772 }
3773
3774 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3775 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3776
3777 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3778 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3779 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3780 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3781
3782 /* Enable / disable of the TX timestamp in the SYNC frames */
3783 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3784 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3785 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3786 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3787
3788 /* Now enable/disable the timestamping */
3789 lan8841_ptp_enable_processing(ptp_priv,
3790 config->rx_filter != HWTSTAMP_FILTER_NONE);
3791
3792 skb_queue_purge(&ptp_priv->tx_queue);
3793
3794 lan8841_ptp_flush_fifo(ptp_priv);
3795
3796 return 0;
3797}
3798
3799static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3800 struct sk_buff *skb, int type)
3801{
3802 struct kszphy_ptp_priv *ptp_priv =
3803 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3804 struct ptp_header *header = ptp_parse_header(skb, type);
3805 struct skb_shared_hwtstamps *shhwtstamps;
3806 struct timespec64 ts;
3807 unsigned long flags;
3808 u32 ts_header;
3809
3810 if (!header)
3811 return false;
3812
3813 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3814 type == PTP_CLASS_NONE)
3815 return false;
3816
3817 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3818 return false;
3819
3820 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3821 ts.tv_sec = ptp_priv->seconds;
3822 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3823 ts_header = __be32_to_cpu(header->reserved2);
3824
3825 shhwtstamps = skb_hwtstamps(skb);
3826 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3827
3828 /* Check for any wrap arounds for the second part */
3829 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3830 ts.tv_sec -= GENMASK(1, 0) + 1;
3831 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3832 ts.tv_sec += 1;
3833
3834 shhwtstamps->hwtstamp =
3835 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3836 ts_header & GENMASK(29, 0));
3837 header->reserved2 = 0;
3838
3839 netif_rx(skb);
3840
3841 return true;
3842}
3843
3844#define LAN8841_EVENT_A 0
3845#define LAN8841_EVENT_B 1
3846#define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
3847#define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
3848#define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
3849#define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
3850
3851static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3852 s64 sec, u32 nsec)
3853{
3854 struct phy_device *phydev = ptp_priv->phydev;
3855 int ret;
3856
3857 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3858 upper_16_bits(sec));
3859 if (ret)
3860 return ret;
3861
3862 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3863 lower_16_bits(sec));
3864 if (ret)
3865 return ret;
3866
3867 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3868 upper_16_bits(nsec));
3869 if (ret)
3870 return ret;
3871
3872 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3873 lower_16_bits(nsec));
3874}
3875
3876#define LAN8841_BUFFER_TIME 2
3877
3878static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3879 const struct timespec64 *ts)
3880{
3881 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3882 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3883}
3884
3885#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
3886#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
3887#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
3888#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
3889
3890static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3891 s64 sec, u32 nsec)
3892{
3893 struct phy_device *phydev = ptp_priv->phydev;
3894 int ret;
3895
3896 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3897 upper_16_bits(sec));
3898 if (ret)
3899 return ret;
3900
3901 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3902 lower_16_bits(sec));
3903 if (ret)
3904 return ret;
3905
3906 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3907 upper_16_bits(nsec));
3908 if (ret)
3909 return ret;
3910
3911 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3912 lower_16_bits(nsec));
3913}
3914
3915#define LAN8841_PTP_LTC_SET_SEC_HI 262
3916#define LAN8841_PTP_LTC_SET_SEC_MID 263
3917#define LAN8841_PTP_LTC_SET_SEC_LO 264
3918#define LAN8841_PTP_LTC_SET_NS_HI 265
3919#define LAN8841_PTP_LTC_SET_NS_LO 266
3920#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
3921
3922static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
3923 const struct timespec64 *ts)
3924{
3925 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3926 ptp_clock_info);
3927 struct phy_device *phydev = ptp_priv->phydev;
3928 unsigned long flags;
3929 int ret;
3930
3931 /* Set the value to be stored */
3932 mutex_lock(&ptp_priv->ptp_lock);
3933 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
3934 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
3935 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
3936 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
3937 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
3938
3939 /* Set the command to load the LTC */
3940 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3941 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
3942 ret = lan8841_ptp_update_target(ptp_priv, ts);
3943 mutex_unlock(&ptp_priv->ptp_lock);
3944
3945 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3946 ptp_priv->seconds = ts->tv_sec;
3947 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3948
3949 return ret;
3950}
3951
3952#define LAN8841_PTP_LTC_RD_SEC_HI 358
3953#define LAN8841_PTP_LTC_RD_SEC_MID 359
3954#define LAN8841_PTP_LTC_RD_SEC_LO 360
3955#define LAN8841_PTP_LTC_RD_NS_HI 361
3956#define LAN8841_PTP_LTC_RD_NS_LO 362
3957#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
3958
3959static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
3960 struct timespec64 *ts)
3961{
3962 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3963 ptp_clock_info);
3964 struct phy_device *phydev = ptp_priv->phydev;
3965 time64_t s;
3966 s64 ns;
3967
3968 mutex_lock(&ptp_priv->ptp_lock);
3969 /* Issue the command to read the LTC */
3970 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3971 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3972
3973 /* Read the LTC */
3974 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3975 s <<= 16;
3976 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3977 s <<= 16;
3978 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3979
3980 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
3981 ns <<= 16;
3982 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
3983 mutex_unlock(&ptp_priv->ptp_lock);
3984
3985 set_normalized_timespec64(ts, s, ns);
3986 return 0;
3987}
3988
3989static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
3990 struct timespec64 *ts)
3991{
3992 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3993 ptp_clock_info);
3994 struct phy_device *phydev = ptp_priv->phydev;
3995 time64_t s;
3996
3997 mutex_lock(&ptp_priv->ptp_lock);
3998 /* Issue the command to read the LTC */
3999 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4000 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4001
4002 /* Read the LTC */
4003 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4004 s <<= 16;
4005 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4006 s <<= 16;
4007 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4008 mutex_unlock(&ptp_priv->ptp_lock);
4009
4010 set_normalized_timespec64(ts, s, 0);
4011}
4012
4013#define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4014#define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4015#define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4016#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4017#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4018
4019static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4020{
4021 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4022 ptp_clock_info);
4023 struct phy_device *phydev = ptp_priv->phydev;
4024 struct timespec64 ts;
4025 bool add = true;
4026 u32 nsec;
4027 s32 sec;
4028 int ret;
4029
4030 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4031 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4032 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4033 * increment so the value can be bigger than 15 sec. Therefore limit the
4034 * possible adjustments so we will not have these corner cases
4035 */
4036 if (delta > 10000000000LL || delta < -10000000000LL) {
4037 /* The timeadjustment is too big, so fall back using set time */
4038 u64 now;
4039
4040 ptp->gettime64(ptp, &ts);
4041
4042 now = ktime_to_ns(timespec64_to_ktime(ts));
4043 ts = ns_to_timespec64(now + delta);
4044
4045 ptp->settime64(ptp, &ts);
4046 return 0;
4047 }
4048
4049 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4050 if (delta < 0 && nsec != 0) {
4051 /* It is not allowed to adjust low the nsec part, therefore
4052 * subtract more from second part and add to nanosecond such
4053 * that would roll over, so the second part will increase
4054 */
4055 sec--;
4056 nsec = NSEC_PER_SEC - nsec;
4057 }
4058
4059 /* Calculate the adjustments and the direction */
4060 if (delta < 0)
4061 add = false;
4062
4063 if (nsec > 0)
4064 /* add 8 ns to cover the likely normal increment */
4065 nsec += 8;
4066
4067 if (nsec >= NSEC_PER_SEC) {
4068 /* carry into seconds */
4069 sec++;
4070 nsec -= NSEC_PER_SEC;
4071 }
4072
4073 mutex_lock(&ptp_priv->ptp_lock);
4074 if (sec) {
4075 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4076 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4077 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4078 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4079 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4080 }
4081
4082 if (nsec) {
4083 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4084 nsec & 0xffff);
4085 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4086 (nsec >> 16) & 0x3fff);
4087 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4088 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4089 }
4090 mutex_unlock(&ptp_priv->ptp_lock);
4091
4092 /* Update the target clock */
4093 ptp->gettime64(ptp, &ts);
4094 mutex_lock(&ptp_priv->ptp_lock);
4095 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4096 mutex_unlock(&ptp_priv->ptp_lock);
4097
4098 return ret;
4099}
4100
4101#define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4102#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4103#define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4104
4105static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4106{
4107 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4108 ptp_clock_info);
4109 struct phy_device *phydev = ptp_priv->phydev;
4110 bool faster = true;
4111 u32 rate;
4112
4113 if (!scaled_ppm)
4114 return 0;
4115
4116 if (scaled_ppm < 0) {
4117 scaled_ppm = -scaled_ppm;
4118 faster = false;
4119 }
4120
4121 rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4122 rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4123
4124 mutex_lock(&ptp_priv->ptp_lock);
4125 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4126 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4127 : upper_16_bits(rate) & 0x3fff);
4128 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4129 mutex_unlock(&ptp_priv->ptp_lock);
4130
4131 return 0;
4132}
4133
4134static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4135 enum ptp_pin_function func, unsigned int chan)
4136{
4137 switch (func) {
4138 case PTP_PF_NONE:
4139 case PTP_PF_PEROUT:
4140 case PTP_PF_EXTTS:
4141 break;
4142 default:
4143 return -1;
4144 }
4145
4146 return 0;
4147}
4148
4149#define LAN8841_PTP_GPIO_NUM 10
4150#define LAN8841_GPIO_EN 128
4151#define LAN8841_GPIO_DIR 129
4152#define LAN8841_GPIO_BUF 130
4153
4154static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4155{
4156 struct phy_device *phydev = ptp_priv->phydev;
4157 int ret;
4158
4159 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4160 if (ret)
4161 return ret;
4162
4163 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4164 if (ret)
4165 return ret;
4166
4167 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4168}
4169
4170static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4171{
4172 struct phy_device *phydev = ptp_priv->phydev;
4173 int ret;
4174
4175 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4176 if (ret)
4177 return ret;
4178
4179 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4180 if (ret)
4181 return ret;
4182
4183 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4184}
4185
4186#define LAN8841_GPIO_DATA_SEL1 131
4187#define LAN8841_GPIO_DATA_SEL2 132
4188#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4189#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4190#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4191#define LAN8841_PTP_GENERAL_CONFIG 257
4192#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4193#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4194#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4195#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4196#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4197#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4198
4199static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4200 u8 event)
4201{
4202 struct phy_device *phydev = ptp_priv->phydev;
4203 u16 tmp;
4204 int ret;
4205
4206 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4207 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4208 * depending on the pin, it requires to read a different register
4209 */
4210 if (pin < 5) {
4211 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4212 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4213 } else {
4214 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4215 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4216 }
4217 if (ret)
4218 return ret;
4219
4220 /* Disable the event */
4221 if (event == LAN8841_EVENT_A)
4222 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4223 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4224 else
4225 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4226 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4227 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4228}
4229
4230static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4231 u8 event, int pulse_width)
4232{
4233 struct phy_device *phydev = ptp_priv->phydev;
4234 u16 tmp;
4235 int ret;
4236
4237 /* Enable the event */
4238 if (event == LAN8841_EVENT_A)
4239 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4240 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4241 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4242 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4243 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4244 else
4245 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4246 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4247 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4248 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4249 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4250 if (ret)
4251 return ret;
4252
4253 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4254 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4255 * depending on the pin, it requires to read a different register
4256 */
4257 if (event == LAN8841_EVENT_A)
4258 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4259 else
4260 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4261
4262 if (pin < 5)
4263 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4264 tmp << (3 * pin));
4265 else
4266 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4267 tmp << (3 * (pin - 5)));
4268
4269 return ret;
4270}
4271
4272#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
4273#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
4274#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
4275#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
4276#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
4277#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
4278#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
4279#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
4280#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
4281#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
4282#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
4283#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
4284#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
4285#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
4286
4287static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4288 struct ptp_clock_request *rq, int on)
4289{
4290 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4291 ptp_clock_info);
4292 struct phy_device *phydev = ptp_priv->phydev;
4293 struct timespec64 ts_on, ts_period;
4294 s64 on_nsec, period_nsec;
4295 int pulse_width;
4296 int pin;
4297 int ret;
4298
4299 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4300 return -EOPNOTSUPP;
4301
4302 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4303 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4304 return -EINVAL;
4305
4306 if (!on) {
4307 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4308 if (ret)
4309 return ret;
4310
4311 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4312 }
4313
4314 ts_on.tv_sec = rq->perout.on.sec;
4315 ts_on.tv_nsec = rq->perout.on.nsec;
4316 on_nsec = timespec64_to_ns(&ts_on);
4317
4318 ts_period.tv_sec = rq->perout.period.sec;
4319 ts_period.tv_nsec = rq->perout.period.nsec;
4320 period_nsec = timespec64_to_ns(&ts_period);
4321
4322 if (period_nsec < 200) {
4323 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4324 phydev_name(phydev));
4325 return -EOPNOTSUPP;
4326 }
4327
4328 if (on_nsec >= period_nsec) {
4329 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4330 phydev_name(phydev));
4331 return -EINVAL;
4332 }
4333
4334 switch (on_nsec) {
4335 case 200000000:
4336 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4337 break;
4338 case 100000000:
4339 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4340 break;
4341 case 50000000:
4342 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4343 break;
4344 case 10000000:
4345 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4346 break;
4347 case 5000000:
4348 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4349 break;
4350 case 1000000:
4351 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4352 break;
4353 case 500000:
4354 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4355 break;
4356 case 100000:
4357 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4358 break;
4359 case 50000:
4360 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4361 break;
4362 case 10000:
4363 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4364 break;
4365 case 5000:
4366 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4367 break;
4368 case 1000:
4369 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4370 break;
4371 case 500:
4372 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4373 break;
4374 case 100:
4375 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4376 break;
4377 default:
4378 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4379 phydev_name(phydev));
4380 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4381 break;
4382 }
4383
4384 mutex_lock(&ptp_priv->ptp_lock);
4385 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4386 rq->perout.start.nsec);
4387 mutex_unlock(&ptp_priv->ptp_lock);
4388 if (ret)
4389 return ret;
4390
4391 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4392 rq->perout.period.nsec);
4393 if (ret)
4394 return ret;
4395
4396 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4397 pulse_width);
4398 if (ret)
4399 return ret;
4400
4401 ret = lan8841_ptp_perout_on(ptp_priv, pin);
4402 if (ret)
4403 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4404
4405 return ret;
4406}
4407
4408#define LAN8841_PTP_GPIO_CAP_EN 496
4409#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
4410#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
4411#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
4412
4413static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4414 u32 flags)
4415{
4416 struct phy_device *phydev = ptp_priv->phydev;
4417 u16 tmp = 0;
4418 int ret;
4419
4420 /* Set GPIO to be intput */
4421 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4422 if (ret)
4423 return ret;
4424
4425 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4426 if (ret)
4427 return ret;
4428
4429 /* Enable capture on the edges of the pin */
4430 if (flags & PTP_RISING_EDGE)
4431 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4432 if (flags & PTP_FALLING_EDGE)
4433 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4434 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4435 if (ret)
4436 return ret;
4437
4438 /* Enable interrupt */
4439 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4440 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4441 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4442}
4443
4444static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4445{
4446 struct phy_device *phydev = ptp_priv->phydev;
4447 int ret;
4448
4449 /* Set GPIO to be output */
4450 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4451 if (ret)
4452 return ret;
4453
4454 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4455 if (ret)
4456 return ret;
4457
4458 /* Disable capture on both of the edges */
4459 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4460 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4461 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4462 0);
4463 if (ret)
4464 return ret;
4465
4466 /* Disable interrupt */
4467 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4468 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4469 0);
4470}
4471
4472static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4473 struct ptp_clock_request *rq, int on)
4474{
4475 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4476 ptp_clock_info);
4477 int pin;
4478 int ret;
4479
4480 /* Reject requests with unsupported flags */
4481 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4482 PTP_EXTTS_EDGES |
4483 PTP_STRICT_FLAGS))
4484 return -EOPNOTSUPP;
4485
4486 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4487 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4488 return -EINVAL;
4489
4490 mutex_lock(&ptp_priv->ptp_lock);
4491 if (on)
4492 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4493 else
4494 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4495 mutex_unlock(&ptp_priv->ptp_lock);
4496
4497 return ret;
4498}
4499
4500static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4501 struct ptp_clock_request *rq, int on)
4502{
4503 switch (rq->type) {
4504 case PTP_CLK_REQ_EXTTS:
4505 return lan8841_ptp_extts(ptp, rq, on);
4506 case PTP_CLK_REQ_PEROUT:
4507 return lan8841_ptp_perout(ptp, rq, on);
4508 default:
4509 return -EOPNOTSUPP;
4510 }
4511
4512 return 0;
4513}
4514
4515static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4516{
4517 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4518 ptp_clock_info);
4519 struct timespec64 ts;
4520 unsigned long flags;
4521
4522 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4523
4524 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4525 ptp_priv->seconds = ts.tv_sec;
4526 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4527
4528 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4529}
4530
4531static struct ptp_clock_info lan8841_ptp_clock_info = {
4532 .owner = THIS_MODULE,
4533 .name = "lan8841 ptp",
4534 .max_adj = 31249999,
4535 .gettime64 = lan8841_ptp_gettime64,
4536 .settime64 = lan8841_ptp_settime64,
4537 .adjtime = lan8841_ptp_adjtime,
4538 .adjfine = lan8841_ptp_adjfine,
4539 .verify = lan8841_ptp_verify,
4540 .enable = lan8841_ptp_enable,
4541 .do_aux_work = lan8841_ptp_do_aux_work,
4542 .n_per_out = LAN8841_PTP_GPIO_NUM,
4543 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
4544 .n_pins = LAN8841_PTP_GPIO_NUM,
4545};
4546
4547#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4548#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4549
4550static int lan8841_probe(struct phy_device *phydev)
4551{
4552 struct kszphy_ptp_priv *ptp_priv;
4553 struct kszphy_priv *priv;
4554 int err;
4555
4556 err = kszphy_probe(phydev);
4557 if (err)
4558 return err;
4559
4560 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4561 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4562 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4563 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4564
4565 /* Register the clock */
4566 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4567 return 0;
4568
4569 priv = phydev->priv;
4570 ptp_priv = &priv->ptp_priv;
4571
4572 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4573 LAN8841_PTP_GPIO_NUM,
4574 sizeof(*ptp_priv->pin_config),
4575 GFP_KERNEL);
4576 if (!ptp_priv->pin_config)
4577 return -ENOMEM;
4578
4579 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4580 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4581
4582 snprintf(p->name, sizeof(p->name), "pin%d", i);
4583 p->index = i;
4584 p->func = PTP_PF_NONE;
4585 }
4586
4587 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4588 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4589 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4590 &phydev->mdio.dev);
4591 if (IS_ERR(ptp_priv->ptp_clock)) {
4592 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4593 PTR_ERR(ptp_priv->ptp_clock));
4594 return -EINVAL;
4595 }
4596
4597 if (!ptp_priv->ptp_clock)
4598 return 0;
4599
4600 /* Initialize the SW */
4601 skb_queue_head_init(&ptp_priv->tx_queue);
4602 ptp_priv->phydev = phydev;
4603 mutex_init(&ptp_priv->ptp_lock);
4604 spin_lock_init(&ptp_priv->seconds_lock);
4605
4606 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4607 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4608 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4609 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4610
4611 phydev->mii_ts = &ptp_priv->mii_ts;
4612
4613 return 0;
4614}
4615
4616static int lan8841_suspend(struct phy_device *phydev)
4617{
4618 struct kszphy_priv *priv = phydev->priv;
4619 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4620
4621 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4622
4623 return genphy_suspend(phydev);
4624}
4625
4626static struct phy_driver ksphy_driver[] = {
4627{
4628 .phy_id = PHY_ID_KS8737,
4629 .phy_id_mask = MICREL_PHY_ID_MASK,
4630 .name = "Micrel KS8737",
4631 /* PHY_BASIC_FEATURES */
4632 .driver_data = &ks8737_type,
4633 .probe = kszphy_probe,
4634 .config_init = kszphy_config_init,
4635 .config_intr = kszphy_config_intr,
4636 .handle_interrupt = kszphy_handle_interrupt,
4637 .suspend = kszphy_suspend,
4638 .resume = kszphy_resume,
4639}, {
4640 .phy_id = PHY_ID_KSZ8021,
4641 .phy_id_mask = 0x00ffffff,
4642 .name = "Micrel KSZ8021 or KSZ8031",
4643 /* PHY_BASIC_FEATURES */
4644 .driver_data = &ksz8021_type,
4645 .probe = kszphy_probe,
4646 .config_init = kszphy_config_init,
4647 .config_intr = kszphy_config_intr,
4648 .handle_interrupt = kszphy_handle_interrupt,
4649 .get_sset_count = kszphy_get_sset_count,
4650 .get_strings = kszphy_get_strings,
4651 .get_stats = kszphy_get_stats,
4652 .suspend = kszphy_suspend,
4653 .resume = kszphy_resume,
4654}, {
4655 .phy_id = PHY_ID_KSZ8031,
4656 .phy_id_mask = 0x00ffffff,
4657 .name = "Micrel KSZ8031",
4658 /* PHY_BASIC_FEATURES */
4659 .driver_data = &ksz8021_type,
4660 .probe = kszphy_probe,
4661 .config_init = kszphy_config_init,
4662 .config_intr = kszphy_config_intr,
4663 .handle_interrupt = kszphy_handle_interrupt,
4664 .get_sset_count = kszphy_get_sset_count,
4665 .get_strings = kszphy_get_strings,
4666 .get_stats = kszphy_get_stats,
4667 .suspend = kszphy_suspend,
4668 .resume = kszphy_resume,
4669}, {
4670 .phy_id = PHY_ID_KSZ8041,
4671 .phy_id_mask = MICREL_PHY_ID_MASK,
4672 .name = "Micrel KSZ8041",
4673 /* PHY_BASIC_FEATURES */
4674 .driver_data = &ksz8041_type,
4675 .probe = kszphy_probe,
4676 .config_init = ksz8041_config_init,
4677 .config_aneg = ksz8041_config_aneg,
4678 .config_intr = kszphy_config_intr,
4679 .handle_interrupt = kszphy_handle_interrupt,
4680 .get_sset_count = kszphy_get_sset_count,
4681 .get_strings = kszphy_get_strings,
4682 .get_stats = kszphy_get_stats,
4683 /* No suspend/resume callbacks because of errata DS80000700A,
4684 * receiver error following software power down.
4685 */
4686}, {
4687 .phy_id = PHY_ID_KSZ8041RNLI,
4688 .phy_id_mask = MICREL_PHY_ID_MASK,
4689 .name = "Micrel KSZ8041RNLI",
4690 /* PHY_BASIC_FEATURES */
4691 .driver_data = &ksz8041_type,
4692 .probe = kszphy_probe,
4693 .config_init = kszphy_config_init,
4694 .config_intr = kszphy_config_intr,
4695 .handle_interrupt = kszphy_handle_interrupt,
4696 .get_sset_count = kszphy_get_sset_count,
4697 .get_strings = kszphy_get_strings,
4698 .get_stats = kszphy_get_stats,
4699 .suspend = kszphy_suspend,
4700 .resume = kszphy_resume,
4701}, {
4702 .name = "Micrel KSZ8051",
4703 /* PHY_BASIC_FEATURES */
4704 .driver_data = &ksz8051_type,
4705 .probe = kszphy_probe,
4706 .config_init = kszphy_config_init,
4707 .config_intr = kszphy_config_intr,
4708 .handle_interrupt = kszphy_handle_interrupt,
4709 .get_sset_count = kszphy_get_sset_count,
4710 .get_strings = kszphy_get_strings,
4711 .get_stats = kszphy_get_stats,
4712 .match_phy_device = ksz8051_match_phy_device,
4713 .suspend = kszphy_suspend,
4714 .resume = kszphy_resume,
4715}, {
4716 .phy_id = PHY_ID_KSZ8001,
4717 .name = "Micrel KSZ8001 or KS8721",
4718 .phy_id_mask = 0x00fffffc,
4719 /* PHY_BASIC_FEATURES */
4720 .driver_data = &ksz8041_type,
4721 .probe = kszphy_probe,
4722 .config_init = kszphy_config_init,
4723 .config_intr = kszphy_config_intr,
4724 .handle_interrupt = kszphy_handle_interrupt,
4725 .get_sset_count = kszphy_get_sset_count,
4726 .get_strings = kszphy_get_strings,
4727 .get_stats = kszphy_get_stats,
4728 .suspend = kszphy_suspend,
4729 .resume = kszphy_resume,
4730}, {
4731 .phy_id = PHY_ID_KSZ8081,
4732 .name = "Micrel KSZ8081 or KSZ8091",
4733 .phy_id_mask = MICREL_PHY_ID_MASK,
4734 .flags = PHY_POLL_CABLE_TEST,
4735 /* PHY_BASIC_FEATURES */
4736 .driver_data = &ksz8081_type,
4737 .probe = kszphy_probe,
4738 .config_init = ksz8081_config_init,
4739 .soft_reset = genphy_soft_reset,
4740 .config_aneg = ksz8081_config_aneg,
4741 .read_status = ksz8081_read_status,
4742 .config_intr = kszphy_config_intr,
4743 .handle_interrupt = kszphy_handle_interrupt,
4744 .get_sset_count = kszphy_get_sset_count,
4745 .get_strings = kszphy_get_strings,
4746 .get_stats = kszphy_get_stats,
4747 .suspend = kszphy_suspend,
4748 .resume = kszphy_resume,
4749 .cable_test_start = ksz886x_cable_test_start,
4750 .cable_test_get_status = ksz886x_cable_test_get_status,
4751}, {
4752 .phy_id = PHY_ID_KSZ8061,
4753 .name = "Micrel KSZ8061",
4754 .phy_id_mask = MICREL_PHY_ID_MASK,
4755 /* PHY_BASIC_FEATURES */
4756 .probe = kszphy_probe,
4757 .config_init = ksz8061_config_init,
4758 .config_intr = kszphy_config_intr,
4759 .handle_interrupt = kszphy_handle_interrupt,
4760 .suspend = kszphy_suspend,
4761 .resume = kszphy_resume,
4762}, {
4763 .phy_id = PHY_ID_KSZ9021,
4764 .phy_id_mask = 0x000ffffe,
4765 .name = "Micrel KSZ9021 Gigabit PHY",
4766 /* PHY_GBIT_FEATURES */
4767 .driver_data = &ksz9021_type,
4768 .probe = kszphy_probe,
4769 .get_features = ksz9031_get_features,
4770 .config_init = ksz9021_config_init,
4771 .config_intr = kszphy_config_intr,
4772 .handle_interrupt = kszphy_handle_interrupt,
4773 .get_sset_count = kszphy_get_sset_count,
4774 .get_strings = kszphy_get_strings,
4775 .get_stats = kszphy_get_stats,
4776 .suspend = kszphy_suspend,
4777 .resume = kszphy_resume,
4778 .read_mmd = genphy_read_mmd_unsupported,
4779 .write_mmd = genphy_write_mmd_unsupported,
4780}, {
4781 .phy_id = PHY_ID_KSZ9031,
4782 .phy_id_mask = MICREL_PHY_ID_MASK,
4783 .name = "Micrel KSZ9031 Gigabit PHY",
4784 .flags = PHY_POLL_CABLE_TEST,
4785 .driver_data = &ksz9021_type,
4786 .probe = kszphy_probe,
4787 .get_features = ksz9031_get_features,
4788 .config_init = ksz9031_config_init,
4789 .soft_reset = genphy_soft_reset,
4790 .read_status = ksz9031_read_status,
4791 .config_intr = kszphy_config_intr,
4792 .handle_interrupt = kszphy_handle_interrupt,
4793 .get_sset_count = kszphy_get_sset_count,
4794 .get_strings = kszphy_get_strings,
4795 .get_stats = kszphy_get_stats,
4796 .suspend = kszphy_suspend,
4797 .resume = kszphy_resume,
4798 .cable_test_start = ksz9x31_cable_test_start,
4799 .cable_test_get_status = ksz9x31_cable_test_get_status,
4800}, {
4801 .phy_id = PHY_ID_LAN8814,
4802 .phy_id_mask = MICREL_PHY_ID_MASK,
4803 .name = "Microchip INDY Gigabit Quad PHY",
4804 .flags = PHY_POLL_CABLE_TEST,
4805 .config_init = lan8814_config_init,
4806 .driver_data = &lan8814_type,
4807 .probe = lan8814_probe,
4808 .soft_reset = genphy_soft_reset,
4809 .read_status = ksz9031_read_status,
4810 .get_sset_count = kszphy_get_sset_count,
4811 .get_strings = kszphy_get_strings,
4812 .get_stats = kszphy_get_stats,
4813 .suspend = genphy_suspend,
4814 .resume = kszphy_resume,
4815 .config_intr = lan8814_config_intr,
4816 .handle_interrupt = lan8814_handle_interrupt,
4817 .cable_test_start = lan8814_cable_test_start,
4818 .cable_test_get_status = ksz886x_cable_test_get_status,
4819}, {
4820 .phy_id = PHY_ID_LAN8804,
4821 .phy_id_mask = MICREL_PHY_ID_MASK,
4822 .name = "Microchip LAN966X Gigabit PHY",
4823 .config_init = lan8804_config_init,
4824 .driver_data = &ksz9021_type,
4825 .probe = kszphy_probe,
4826 .soft_reset = genphy_soft_reset,
4827 .read_status = ksz9031_read_status,
4828 .get_sset_count = kszphy_get_sset_count,
4829 .get_strings = kszphy_get_strings,
4830 .get_stats = kszphy_get_stats,
4831 .suspend = genphy_suspend,
4832 .resume = kszphy_resume,
4833 .config_intr = lan8804_config_intr,
4834 .handle_interrupt = lan8804_handle_interrupt,
4835}, {
4836 .phy_id = PHY_ID_LAN8841,
4837 .phy_id_mask = MICREL_PHY_ID_MASK,
4838 .name = "Microchip LAN8841 Gigabit PHY",
4839 .flags = PHY_POLL_CABLE_TEST,
4840 .driver_data = &lan8841_type,
4841 .config_init = lan8841_config_init,
4842 .probe = lan8841_probe,
4843 .soft_reset = genphy_soft_reset,
4844 .config_intr = lan8841_config_intr,
4845 .handle_interrupt = lan8841_handle_interrupt,
4846 .get_sset_count = kszphy_get_sset_count,
4847 .get_strings = kszphy_get_strings,
4848 .get_stats = kszphy_get_stats,
4849 .suspend = lan8841_suspend,
4850 .resume = genphy_resume,
4851 .cable_test_start = lan8814_cable_test_start,
4852 .cable_test_get_status = ksz886x_cable_test_get_status,
4853}, {
4854 .phy_id = PHY_ID_KSZ9131,
4855 .phy_id_mask = MICREL_PHY_ID_MASK,
4856 .name = "Microchip KSZ9131 Gigabit PHY",
4857 /* PHY_GBIT_FEATURES */
4858 .flags = PHY_POLL_CABLE_TEST,
4859 .driver_data = &ksz9131_type,
4860 .probe = kszphy_probe,
4861 .soft_reset = genphy_soft_reset,
4862 .config_init = ksz9131_config_init,
4863 .config_intr = kszphy_config_intr,
4864 .config_aneg = ksz9131_config_aneg,
4865 .read_status = ksz9131_read_status,
4866 .handle_interrupt = kszphy_handle_interrupt,
4867 .get_sset_count = kszphy_get_sset_count,
4868 .get_strings = kszphy_get_strings,
4869 .get_stats = kszphy_get_stats,
4870 .suspend = kszphy_suspend,
4871 .resume = kszphy_resume,
4872 .cable_test_start = ksz9x31_cable_test_start,
4873 .cable_test_get_status = ksz9x31_cable_test_get_status,
4874 .get_features = ksz9477_get_features,
4875}, {
4876 .phy_id = PHY_ID_KSZ8873MLL,
4877 .phy_id_mask = MICREL_PHY_ID_MASK,
4878 .name = "Micrel KSZ8873MLL Switch",
4879 /* PHY_BASIC_FEATURES */
4880 .config_init = kszphy_config_init,
4881 .config_aneg = ksz8873mll_config_aneg,
4882 .read_status = ksz8873mll_read_status,
4883 .suspend = genphy_suspend,
4884 .resume = genphy_resume,
4885}, {
4886 .phy_id = PHY_ID_KSZ886X,
4887 .phy_id_mask = MICREL_PHY_ID_MASK,
4888 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4889 .driver_data = &ksz886x_type,
4890 /* PHY_BASIC_FEATURES */
4891 .flags = PHY_POLL_CABLE_TEST,
4892 .config_init = kszphy_config_init,
4893 .config_aneg = ksz886x_config_aneg,
4894 .read_status = ksz886x_read_status,
4895 .suspend = genphy_suspend,
4896 .resume = genphy_resume,
4897 .cable_test_start = ksz886x_cable_test_start,
4898 .cable_test_get_status = ksz886x_cable_test_get_status,
4899}, {
4900 .name = "Micrel KSZ87XX Switch",
4901 /* PHY_BASIC_FEATURES */
4902 .config_init = kszphy_config_init,
4903 .match_phy_device = ksz8795_match_phy_device,
4904 .suspend = genphy_suspend,
4905 .resume = genphy_resume,
4906}, {
4907 .phy_id = PHY_ID_KSZ9477,
4908 .phy_id_mask = MICREL_PHY_ID_MASK,
4909 .name = "Microchip KSZ9477",
4910 /* PHY_GBIT_FEATURES */
4911 .config_init = ksz9477_config_init,
4912 .config_intr = kszphy_config_intr,
4913 .handle_interrupt = kszphy_handle_interrupt,
4914 .suspend = genphy_suspend,
4915 .resume = genphy_resume,
4916 .get_features = ksz9477_get_features,
4917} };
4918
4919module_phy_driver(ksphy_driver);
4920
4921MODULE_DESCRIPTION("Micrel PHY driver");
4922MODULE_AUTHOR("David J. Choi");
4923MODULE_LICENSE("GPL");
4924
4925static struct mdio_device_id __maybe_unused micrel_tbl[] = {
4926 { PHY_ID_KSZ9021, 0x000ffffe },
4927 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
4928 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
4929 { PHY_ID_KSZ8001, 0x00fffffc },
4930 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
4931 { PHY_ID_KSZ8021, 0x00ffffff },
4932 { PHY_ID_KSZ8031, 0x00ffffff },
4933 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
4934 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
4935 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
4936 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
4937 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
4938 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
4939 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
4940 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
4941 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
4942 { }
4943};
4944
4945MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29
30/* Operation Mode Strap Override */
31#define MII_KSZPHY_OMSO 0x16
32#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
34#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
35
36/* general Interrupt control/status reg in vendor specific block. */
37#define MII_KSZPHY_INTCS 0x1B
38#define KSZPHY_INTCS_JABBER (1 << 15)
39#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
40#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
41#define KSZPHY_INTCS_PARELLEL (1 << 12)
42#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
43#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
44#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
45#define KSZPHY_INTCS_LINK_UP (1 << 8)
46#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
47 KSZPHY_INTCS_LINK_DOWN)
48
49/* general PHY control reg in vendor specific block. */
50#define MII_KSZPHY_CTRL 0x1F
51/* bitmap of PHY register to set interrupt mode */
52#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
53#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
54#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
55#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
56
57/* Write/read to/from extended registers */
58#define MII_KSZPHY_EXTREG 0x0b
59#define KSZPHY_EXTREG_WRITE 0x8000
60
61#define MII_KSZPHY_EXTREG_WRITE 0x0c
62#define MII_KSZPHY_EXTREG_READ 0x0d
63
64/* Extended registers */
65#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
66#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
67#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
68
69#define PS_TO_REG 200
70
71static int ksz_config_flags(struct phy_device *phydev)
72{
73 int regval;
74
75 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
76 regval = phy_read(phydev, MII_KSZPHY_CTRL);
77 regval |= KSZ8051_RMII_50MHZ_CLK;
78 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
79 }
80 return 0;
81}
82
83static int kszphy_extended_write(struct phy_device *phydev,
84 u32 regnum, u16 val)
85{
86 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
87 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
88}
89
90static int kszphy_extended_read(struct phy_device *phydev,
91 u32 regnum)
92{
93 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
94 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
95}
96
97static int kszphy_ack_interrupt(struct phy_device *phydev)
98{
99 /* bit[7..0] int status, which is a read and clear register. */
100 int rc;
101
102 rc = phy_read(phydev, MII_KSZPHY_INTCS);
103
104 return (rc < 0) ? rc : 0;
105}
106
107static int kszphy_set_interrupt(struct phy_device *phydev)
108{
109 int temp;
110 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
111 KSZPHY_INTCS_ALL : 0;
112 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
113}
114
115static int kszphy_config_intr(struct phy_device *phydev)
116{
117 int temp, rc;
118
119 /* set the interrupt pin active low */
120 temp = phy_read(phydev, MII_KSZPHY_CTRL);
121 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
122 phy_write(phydev, MII_KSZPHY_CTRL, temp);
123 rc = kszphy_set_interrupt(phydev);
124 return rc < 0 ? rc : 0;
125}
126
127static int ksz9021_config_intr(struct phy_device *phydev)
128{
129 int temp, rc;
130
131 /* set the interrupt pin active low */
132 temp = phy_read(phydev, MII_KSZPHY_CTRL);
133 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
134 phy_write(phydev, MII_KSZPHY_CTRL, temp);
135 rc = kszphy_set_interrupt(phydev);
136 return rc < 0 ? rc : 0;
137}
138
139static int ks8737_config_intr(struct phy_device *phydev)
140{
141 int temp, rc;
142
143 /* set the interrupt pin active low */
144 temp = phy_read(phydev, MII_KSZPHY_CTRL);
145 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
146 phy_write(phydev, MII_KSZPHY_CTRL, temp);
147 rc = kszphy_set_interrupt(phydev);
148 return rc < 0 ? rc : 0;
149}
150
151static int kszphy_setup_led(struct phy_device *phydev,
152 unsigned int reg, unsigned int shift)
153{
154
155 struct device *dev = &phydev->dev;
156 struct device_node *of_node = dev->of_node;
157 int rc, temp;
158 u32 val;
159
160 if (!of_node && dev->parent->of_node)
161 of_node = dev->parent->of_node;
162
163 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
164 return 0;
165
166 temp = phy_read(phydev, reg);
167 if (temp < 0)
168 return temp;
169
170 temp &= ~(3 << shift);
171 temp |= val << shift;
172 rc = phy_write(phydev, reg, temp);
173
174 return rc < 0 ? rc : 0;
175}
176
177static int kszphy_config_init(struct phy_device *phydev)
178{
179 return 0;
180}
181
182static int kszphy_config_init_led8041(struct phy_device *phydev)
183{
184 /* single led control, register 0x1e bits 15..14 */
185 return kszphy_setup_led(phydev, 0x1e, 14);
186}
187
188static int ksz8021_config_init(struct phy_device *phydev)
189{
190 const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
191 int rc;
192
193 rc = kszphy_setup_led(phydev, 0x1f, 4);
194 if (rc)
195 dev_err(&phydev->dev, "failed to set led mode\n");
196
197 phy_write(phydev, MII_KSZPHY_OMSO, val);
198 rc = ksz_config_flags(phydev);
199 return rc < 0 ? rc : 0;
200}
201
202static int ks8051_config_init(struct phy_device *phydev)
203{
204 int rc;
205
206 rc = kszphy_setup_led(phydev, 0x1f, 4);
207 if (rc)
208 dev_err(&phydev->dev, "failed to set led mode\n");
209
210 rc = ksz_config_flags(phydev);
211 return rc < 0 ? rc : 0;
212}
213
214static int ksz9021_load_values_from_of(struct phy_device *phydev,
215 struct device_node *of_node, u16 reg,
216 char *field1, char *field2,
217 char *field3, char *field4)
218{
219 int val1 = -1;
220 int val2 = -2;
221 int val3 = -3;
222 int val4 = -4;
223 int newval;
224 int matches = 0;
225
226 if (!of_property_read_u32(of_node, field1, &val1))
227 matches++;
228
229 if (!of_property_read_u32(of_node, field2, &val2))
230 matches++;
231
232 if (!of_property_read_u32(of_node, field3, &val3))
233 matches++;
234
235 if (!of_property_read_u32(of_node, field4, &val4))
236 matches++;
237
238 if (!matches)
239 return 0;
240
241 if (matches < 4)
242 newval = kszphy_extended_read(phydev, reg);
243 else
244 newval = 0;
245
246 if (val1 != -1)
247 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
248
249 if (val2 != -2)
250 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
251
252 if (val3 != -3)
253 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
254
255 if (val4 != -4)
256 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
257
258 return kszphy_extended_write(phydev, reg, newval);
259}
260
261static int ksz9021_config_init(struct phy_device *phydev)
262{
263 struct device *dev = &phydev->dev;
264 struct device_node *of_node = dev->of_node;
265
266 if (!of_node && dev->parent->of_node)
267 of_node = dev->parent->of_node;
268
269 if (of_node) {
270 ksz9021_load_values_from_of(phydev, of_node,
271 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
272 "txen-skew-ps", "txc-skew-ps",
273 "rxdv-skew-ps", "rxc-skew-ps");
274 ksz9021_load_values_from_of(phydev, of_node,
275 MII_KSZPHY_RX_DATA_PAD_SKEW,
276 "rxd0-skew-ps", "rxd1-skew-ps",
277 "rxd2-skew-ps", "rxd3-skew-ps");
278 ksz9021_load_values_from_of(phydev, of_node,
279 MII_KSZPHY_TX_DATA_PAD_SKEW,
280 "txd0-skew-ps", "txd1-skew-ps",
281 "txd2-skew-ps", "txd3-skew-ps");
282 }
283 return 0;
284}
285
286#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
287#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
288#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
289static int ksz8873mll_read_status(struct phy_device *phydev)
290{
291 int regval;
292
293 /* dummy read */
294 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
295
296 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
297
298 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
299 phydev->duplex = DUPLEX_HALF;
300 else
301 phydev->duplex = DUPLEX_FULL;
302
303 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
304 phydev->speed = SPEED_10;
305 else
306 phydev->speed = SPEED_100;
307
308 phydev->link = 1;
309 phydev->pause = phydev->asym_pause = 0;
310
311 return 0;
312}
313
314static int ksz8873mll_config_aneg(struct phy_device *phydev)
315{
316 return 0;
317}
318
319static struct phy_driver ksphy_driver[] = {
320{
321 .phy_id = PHY_ID_KS8737,
322 .phy_id_mask = 0x00fffff0,
323 .name = "Micrel KS8737",
324 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
325 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
326 .config_init = kszphy_config_init,
327 .config_aneg = genphy_config_aneg,
328 .read_status = genphy_read_status,
329 .ack_interrupt = kszphy_ack_interrupt,
330 .config_intr = ks8737_config_intr,
331 .suspend = genphy_suspend,
332 .resume = genphy_resume,
333 .driver = { .owner = THIS_MODULE,},
334}, {
335 .phy_id = PHY_ID_KSZ8021,
336 .phy_id_mask = 0x00ffffff,
337 .name = "Micrel KSZ8021 or KSZ8031",
338 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
339 SUPPORTED_Asym_Pause),
340 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
341 .config_init = ksz8021_config_init,
342 .config_aneg = genphy_config_aneg,
343 .read_status = genphy_read_status,
344 .ack_interrupt = kszphy_ack_interrupt,
345 .config_intr = kszphy_config_intr,
346 .suspend = genphy_suspend,
347 .resume = genphy_resume,
348 .driver = { .owner = THIS_MODULE,},
349}, {
350 .phy_id = PHY_ID_KSZ8031,
351 .phy_id_mask = 0x00ffffff,
352 .name = "Micrel KSZ8031",
353 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
354 SUPPORTED_Asym_Pause),
355 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
356 .config_init = ksz8021_config_init,
357 .config_aneg = genphy_config_aneg,
358 .read_status = genphy_read_status,
359 .ack_interrupt = kszphy_ack_interrupt,
360 .config_intr = kszphy_config_intr,
361 .suspend = genphy_suspend,
362 .resume = genphy_resume,
363 .driver = { .owner = THIS_MODULE,},
364}, {
365 .phy_id = PHY_ID_KSZ8041,
366 .phy_id_mask = 0x00fffff0,
367 .name = "Micrel KSZ8041",
368 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
369 | SUPPORTED_Asym_Pause),
370 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
371 .config_init = kszphy_config_init_led8041,
372 .config_aneg = genphy_config_aneg,
373 .read_status = genphy_read_status,
374 .ack_interrupt = kszphy_ack_interrupt,
375 .config_intr = kszphy_config_intr,
376 .suspend = genphy_suspend,
377 .resume = genphy_resume,
378 .driver = { .owner = THIS_MODULE,},
379}, {
380 .phy_id = PHY_ID_KSZ8041RNLI,
381 .phy_id_mask = 0x00fffff0,
382 .name = "Micrel KSZ8041RNLI",
383 .features = PHY_BASIC_FEATURES |
384 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
385 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
386 .config_init = kszphy_config_init_led8041,
387 .config_aneg = genphy_config_aneg,
388 .read_status = genphy_read_status,
389 .ack_interrupt = kszphy_ack_interrupt,
390 .config_intr = kszphy_config_intr,
391 .suspend = genphy_suspend,
392 .resume = genphy_resume,
393 .driver = { .owner = THIS_MODULE,},
394}, {
395 .phy_id = PHY_ID_KSZ8051,
396 .phy_id_mask = 0x00fffff0,
397 .name = "Micrel KSZ8051",
398 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
399 | SUPPORTED_Asym_Pause),
400 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
401 .config_init = ks8051_config_init,
402 .config_aneg = genphy_config_aneg,
403 .read_status = genphy_read_status,
404 .ack_interrupt = kszphy_ack_interrupt,
405 .config_intr = kszphy_config_intr,
406 .suspend = genphy_suspend,
407 .resume = genphy_resume,
408 .driver = { .owner = THIS_MODULE,},
409}, {
410 .phy_id = PHY_ID_KSZ8001,
411 .name = "Micrel KSZ8001 or KS8721",
412 .phy_id_mask = 0x00ffffff,
413 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
414 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
415 .config_init = kszphy_config_init_led8041,
416 .config_aneg = genphy_config_aneg,
417 .read_status = genphy_read_status,
418 .ack_interrupt = kszphy_ack_interrupt,
419 .config_intr = kszphy_config_intr,
420 .suspend = genphy_suspend,
421 .resume = genphy_resume,
422 .driver = { .owner = THIS_MODULE,},
423}, {
424 .phy_id = PHY_ID_KSZ8081,
425 .name = "Micrel KSZ8081 or KSZ8091",
426 .phy_id_mask = 0x00fffff0,
427 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
428 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
429 .config_init = kszphy_config_init,
430 .config_aneg = genphy_config_aneg,
431 .read_status = genphy_read_status,
432 .ack_interrupt = kszphy_ack_interrupt,
433 .config_intr = kszphy_config_intr,
434 .suspend = genphy_suspend,
435 .resume = genphy_resume,
436 .driver = { .owner = THIS_MODULE,},
437}, {
438 .phy_id = PHY_ID_KSZ8061,
439 .name = "Micrel KSZ8061",
440 .phy_id_mask = 0x00fffff0,
441 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
442 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
443 .config_init = kszphy_config_init,
444 .config_aneg = genphy_config_aneg,
445 .read_status = genphy_read_status,
446 .ack_interrupt = kszphy_ack_interrupt,
447 .config_intr = kszphy_config_intr,
448 .suspend = genphy_suspend,
449 .resume = genphy_resume,
450 .driver = { .owner = THIS_MODULE,},
451}, {
452 .phy_id = PHY_ID_KSZ9021,
453 .phy_id_mask = 0x000ffffe,
454 .name = "Micrel KSZ9021 Gigabit PHY",
455 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
456 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
457 .config_init = ksz9021_config_init,
458 .config_aneg = genphy_config_aneg,
459 .read_status = genphy_read_status,
460 .ack_interrupt = kszphy_ack_interrupt,
461 .config_intr = ksz9021_config_intr,
462 .suspend = genphy_suspend,
463 .resume = genphy_resume,
464 .driver = { .owner = THIS_MODULE, },
465}, {
466 .phy_id = PHY_ID_KSZ9031,
467 .phy_id_mask = 0x00fffff0,
468 .name = "Micrel KSZ9031 Gigabit PHY",
469 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
470 | SUPPORTED_Asym_Pause),
471 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
472 .config_init = kszphy_config_init,
473 .config_aneg = genphy_config_aneg,
474 .read_status = genphy_read_status,
475 .ack_interrupt = kszphy_ack_interrupt,
476 .config_intr = ksz9021_config_intr,
477 .suspend = genphy_suspend,
478 .resume = genphy_resume,
479 .driver = { .owner = THIS_MODULE, },
480}, {
481 .phy_id = PHY_ID_KSZ8873MLL,
482 .phy_id_mask = 0x00fffff0,
483 .name = "Micrel KSZ8873MLL Switch",
484 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
485 .flags = PHY_HAS_MAGICANEG,
486 .config_init = kszphy_config_init,
487 .config_aneg = ksz8873mll_config_aneg,
488 .read_status = ksz8873mll_read_status,
489 .suspend = genphy_suspend,
490 .resume = genphy_resume,
491 .driver = { .owner = THIS_MODULE, },
492}, {
493 .phy_id = PHY_ID_KSZ886X,
494 .phy_id_mask = 0x00fffff0,
495 .name = "Micrel KSZ886X Switch",
496 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
497 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
498 .config_init = kszphy_config_init,
499 .config_aneg = genphy_config_aneg,
500 .read_status = genphy_read_status,
501 .suspend = genphy_suspend,
502 .resume = genphy_resume,
503 .driver = { .owner = THIS_MODULE, },
504} };
505
506static int __init ksphy_init(void)
507{
508 return phy_drivers_register(ksphy_driver,
509 ARRAY_SIZE(ksphy_driver));
510}
511
512static void __exit ksphy_exit(void)
513{
514 phy_drivers_unregister(ksphy_driver,
515 ARRAY_SIZE(ksphy_driver));
516}
517
518module_init(ksphy_init);
519module_exit(ksphy_exit);
520
521MODULE_DESCRIPTION("Micrel PHY driver");
522MODULE_AUTHOR("David J. Choi");
523MODULE_LICENSE("GPL");
524
525static struct mdio_device_id __maybe_unused micrel_tbl[] = {
526 { PHY_ID_KSZ9021, 0x000ffffe },
527 { PHY_ID_KSZ9031, 0x00fffff0 },
528 { PHY_ID_KSZ8001, 0x00ffffff },
529 { PHY_ID_KS8737, 0x00fffff0 },
530 { PHY_ID_KSZ8021, 0x00ffffff },
531 { PHY_ID_KSZ8031, 0x00ffffff },
532 { PHY_ID_KSZ8041, 0x00fffff0 },
533 { PHY_ID_KSZ8051, 0x00fffff0 },
534 { PHY_ID_KSZ8061, 0x00fffff0 },
535 { PHY_ID_KSZ8081, 0x00fffff0 },
536 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
537 { PHY_ID_KSZ886X, 0x00fffff0 },
538 { }
539};
540
541MODULE_DEVICE_TABLE(mdio, micrel_tbl);