1# SPDX-License-Identifier: GPL-2.0-only
 2config FSL_FMAN
 3	tristate "FMan support"
 4	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
 5	select GENERIC_ALLOCATOR
 6	select PHYLINK
 7	select PCS_LYNX
 8	select CRC32
 9	default n
10	help
11		Freescale Data-Path Acceleration Architecture Frame Manager
12		(FMan) support
13
14config DPAA_ERRATUM_A050385
15	bool
16	depends on ARM64 && FSL_DPAA
17	default y
18	help
19		DPAA FMan erratum A050385 software workaround implementation:
20		align buffers, data start, SG fragment length to avoid FMan DMA
21		splits.
22		FMAN DMA read or writes under heavy traffic load may cause FMAN
23		internal resource leak thus stopping further packet processing.
24		The FMAN internal queue can overflow when FMAN splits single
25		read or write transactions into multiple smaller transactions
26		such that more than 17 AXI transactions are in flight from FMAN
27		to interconnect. When the FMAN internal queue overflows, it can
28		stall further packet processing. The issue can occur with any
29		one of the following three conditions:
30		1. FMAN AXI transaction crosses 4K address boundary (Errata
31		A010022)
32		2. FMAN DMA address for an AXI transaction is not 16 byte
33		aligned, i.e. the last 4 bits of an address are non-zero
34		3. Scatter Gather (SG) frames have more than one SG buffer in
35		the SG list and any one of the buffers, except the last
36		buffer in the SG list has data size that is not a multiple
37		of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
38		With any one of the above three conditions present, there is
39		likelihood of stalled FMAN packet processing, especially under
40		stress with multiple ports injecting line-rate traffic.