Linux Audio

Check our new training course

Open-source upstreaming

Need help get the support for your hardware in upstream Linux?
Loading...
v6.8
 1/* bnx2_fw.h: QLogic bnx2 network driver.
 2 *
 3 * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
 4 * Copyright (c) 2014-2015 QLogic Corporation
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License as published by
 8 * the Free Software Foundation.
 9 */
10
11/* Initialized Values for the Completion Processor. */
12static const struct cpu_reg cpu_reg_com = {
13	.mode = BNX2_COM_CPU_MODE,
14	.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
15	.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
16	.state = BNX2_COM_CPU_STATE,
17	.state_value_clear = 0xffffff,
18	.gpr0 = BNX2_COM_CPU_REG_FILE,
19	.evmask = BNX2_COM_CPU_EVENT_MASK,
20	.pc = BNX2_COM_CPU_PROGRAM_COUNTER,
21	.inst = BNX2_COM_CPU_INSTRUCTION,
22	.bp = BNX2_COM_CPU_HW_BREAKPOINT,
23	.spad_base = BNX2_COM_SCRATCH,
24	.mips_view_base = 0x8000000,
25};
26
27/* Initialized Values the Command Processor. */
28static const struct cpu_reg cpu_reg_cp = {
29	.mode = BNX2_CP_CPU_MODE,
30	.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
31	.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
32	.state = BNX2_CP_CPU_STATE,
33	.state_value_clear = 0xffffff,
34	.gpr0 = BNX2_CP_CPU_REG_FILE,
35	.evmask = BNX2_CP_CPU_EVENT_MASK,
36	.pc = BNX2_CP_CPU_PROGRAM_COUNTER,
37	.inst = BNX2_CP_CPU_INSTRUCTION,
38	.bp = BNX2_CP_CPU_HW_BREAKPOINT,
39	.spad_base = BNX2_CP_SCRATCH,
40	.mips_view_base = 0x8000000,
41};
42
43/* Initialized Values for the RX Processor. */
44static const struct cpu_reg cpu_reg_rxp = {
45	.mode = BNX2_RXP_CPU_MODE,
46	.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
47	.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
48	.state = BNX2_RXP_CPU_STATE,
49	.state_value_clear = 0xffffff,
50	.gpr0 = BNX2_RXP_CPU_REG_FILE,
51	.evmask = BNX2_RXP_CPU_EVENT_MASK,
52	.pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
53	.inst = BNX2_RXP_CPU_INSTRUCTION,
54	.bp = BNX2_RXP_CPU_HW_BREAKPOINT,
55	.spad_base = BNX2_RXP_SCRATCH,
56	.mips_view_base = 0x8000000,
57};
58
59/* Initialized Values for the TX Patch-up Processor. */
60static const struct cpu_reg cpu_reg_tpat = {
61	.mode = BNX2_TPAT_CPU_MODE,
62	.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
63	.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
64	.state = BNX2_TPAT_CPU_STATE,
65	.state_value_clear = 0xffffff,
66	.gpr0 = BNX2_TPAT_CPU_REG_FILE,
67	.evmask = BNX2_TPAT_CPU_EVENT_MASK,
68	.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
69	.inst = BNX2_TPAT_CPU_INSTRUCTION,
70	.bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
71	.spad_base = BNX2_TPAT_SCRATCH,
72	.mips_view_base = 0x8000000,
73};
74
75/* Initialized Values for the TX Processor. */
76static const struct cpu_reg cpu_reg_txp = {
77	.mode = BNX2_TXP_CPU_MODE,
78	.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
79	.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
80	.state = BNX2_TXP_CPU_STATE,
81	.state_value_clear = 0xffffff,
82	.gpr0 = BNX2_TXP_CPU_REG_FILE,
83	.evmask = BNX2_TXP_CPU_EVENT_MASK,
84	.pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
85	.inst = BNX2_TXP_CPU_INSTRUCTION,
86	.bp = BNX2_TXP_CPU_HW_BREAKPOINT,
87	.spad_base = BNX2_TXP_SCRATCH,
88	.mips_view_base = 0x8000000,
89};
v3.15
 1/* bnx2_fw.h: Broadcom NX2 network driver.
 2 *
 3 * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
 
 4 *
 5 * This program is free software; you can redistribute it and/or modify
 6 * it under the terms of the GNU General Public License as published by
 7 * the Free Software Foundation.
 8 */
 9
10/* Initialized Values for the Completion Processor. */
11static const struct cpu_reg cpu_reg_com = {
12	.mode = BNX2_COM_CPU_MODE,
13	.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
14	.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
15	.state = BNX2_COM_CPU_STATE,
16	.state_value_clear = 0xffffff,
17	.gpr0 = BNX2_COM_CPU_REG_FILE,
18	.evmask = BNX2_COM_CPU_EVENT_MASK,
19	.pc = BNX2_COM_CPU_PROGRAM_COUNTER,
20	.inst = BNX2_COM_CPU_INSTRUCTION,
21	.bp = BNX2_COM_CPU_HW_BREAKPOINT,
22	.spad_base = BNX2_COM_SCRATCH,
23	.mips_view_base = 0x8000000,
24};
25
26/* Initialized Values the Command Processor. */
27static const struct cpu_reg cpu_reg_cp = {
28	.mode = BNX2_CP_CPU_MODE,
29	.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
30	.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
31	.state = BNX2_CP_CPU_STATE,
32	.state_value_clear = 0xffffff,
33	.gpr0 = BNX2_CP_CPU_REG_FILE,
34	.evmask = BNX2_CP_CPU_EVENT_MASK,
35	.pc = BNX2_CP_CPU_PROGRAM_COUNTER,
36	.inst = BNX2_CP_CPU_INSTRUCTION,
37	.bp = BNX2_CP_CPU_HW_BREAKPOINT,
38	.spad_base = BNX2_CP_SCRATCH,
39	.mips_view_base = 0x8000000,
40};
41
42/* Initialized Values for the RX Processor. */
43static const struct cpu_reg cpu_reg_rxp = {
44	.mode = BNX2_RXP_CPU_MODE,
45	.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
46	.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
47	.state = BNX2_RXP_CPU_STATE,
48	.state_value_clear = 0xffffff,
49	.gpr0 = BNX2_RXP_CPU_REG_FILE,
50	.evmask = BNX2_RXP_CPU_EVENT_MASK,
51	.pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
52	.inst = BNX2_RXP_CPU_INSTRUCTION,
53	.bp = BNX2_RXP_CPU_HW_BREAKPOINT,
54	.spad_base = BNX2_RXP_SCRATCH,
55	.mips_view_base = 0x8000000,
56};
57
58/* Initialized Values for the TX Patch-up Processor. */
59static const struct cpu_reg cpu_reg_tpat = {
60	.mode = BNX2_TPAT_CPU_MODE,
61	.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
62	.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
63	.state = BNX2_TPAT_CPU_STATE,
64	.state_value_clear = 0xffffff,
65	.gpr0 = BNX2_TPAT_CPU_REG_FILE,
66	.evmask = BNX2_TPAT_CPU_EVENT_MASK,
67	.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
68	.inst = BNX2_TPAT_CPU_INSTRUCTION,
69	.bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
70	.spad_base = BNX2_TPAT_SCRATCH,
71	.mips_view_base = 0x8000000,
72};
73
74/* Initialized Values for the TX Processor. */
75static const struct cpu_reg cpu_reg_txp = {
76	.mode = BNX2_TXP_CPU_MODE,
77	.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
78	.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
79	.state = BNX2_TXP_CPU_STATE,
80	.state_value_clear = 0xffffff,
81	.gpr0 = BNX2_TXP_CPU_REG_FILE,
82	.evmask = BNX2_TXP_CPU_EVENT_MASK,
83	.pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
84	.inst = BNX2_TXP_CPU_INSTRUCTION,
85	.bp = BNX2_TXP_CPU_HW_BREAKPOINT,
86	.spad_base = BNX2_TXP_SCRATCH,
87	.mips_view_base = 0x8000000,
88};