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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
4 *
5 * Registers and bits definitions of ARC EMAC
6 */
7
8#ifndef ARC_EMAC_H
9#define ARC_EMAC_H
10
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/phy.h>
15#include <linux/clk.h>
16
17/* STATUS and ENABLE Register bit masks */
18#define TXINT_MASK (1 << 0) /* Transmit interrupt */
19#define RXINT_MASK (1 << 1) /* Receive interrupt */
20#define ERR_MASK (1 << 2) /* Error interrupt */
21#define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
22#define MSER_MASK (1 << 4) /* Missed packet counter error */
23#define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
24#define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
25#define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
26#define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
27#define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
28
29/* CONTROL Register bit masks */
30#define EN_MASK (1 << 0) /* VMAC enable */
31#define TXRN_MASK (1 << 3) /* TX enable */
32#define RXRN_MASK (1 << 4) /* RX enable */
33#define DSBC_MASK (1 << 8) /* Disable receive broadcast */
34#define ENFL_MASK (1 << 10) /* Enable Full-duplex */
35#define PROM_MASK (1 << 11) /* Promiscuous mode */
36
37/* Buffer descriptor INFO bit masks */
38#define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
39#define FIRST_MASK (1 << 16) /* First buffer in chain */
40#define LAST_MASK (1 << 17) /* Last buffer in chain */
41#define LEN_MASK 0x000007FF /* last 11 bits */
42#define CRLS (1 << 21)
43#define DEFR (1 << 22)
44#define DROP (1 << 23)
45#define RTRY (1 << 24)
46#define LTCL (1 << 28)
47#define UFLO (1 << 29)
48
49#define FOR_EMAC OWN_MASK
50#define FOR_CPU 0
51
52/* ARC EMAC register set combines entries for MAC and MDIO */
53enum {
54 R_ID = 0,
55 R_STATUS,
56 R_ENABLE,
57 R_CTRL,
58 R_POLLRATE,
59 R_RXERR,
60 R_MISS,
61 R_TX_RING,
62 R_RX_RING,
63 R_ADDRL,
64 R_ADDRH,
65 R_LAFL,
66 R_LAFH,
67 R_MDIO,
68};
69
70#define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
71
72#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
73
74#define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
75
76/**
77 * struct arc_emac_bd - EMAC buffer descriptor (BD).
78 *
79 * @info: Contains status information on the buffer itself.
80 * @data: 32-bit byte addressable pointer to the packet data.
81 */
82struct arc_emac_bd {
83 __le32 info;
84 dma_addr_t data;
85};
86
87/* Number of Rx/Tx BD's */
88#define RX_BD_NUM 128
89#define TX_BD_NUM 128
90
91#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
92#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
93
94/**
95 * struct buffer_state - Stores Rx/Tx buffer state.
96 * @sk_buff: Pointer to socket buffer.
97 * @addr: Start address of DMA-mapped memory region.
98 * @len: Length of DMA-mapped memory region.
99 */
100struct buffer_state {
101 struct sk_buff *skb;
102 DEFINE_DMA_UNMAP_ADDR(addr);
103 DEFINE_DMA_UNMAP_LEN(len);
104};
105
106struct arc_emac_mdio_bus_data {
107 struct gpio_desc *reset_gpio;
108 int msec;
109};
110
111/**
112 * struct arc_emac_priv - Storage of EMAC's private information.
113 * @dev: Pointer to the current device.
114 * @phy_dev: Pointer to attached PHY device.
115 * @bus: Pointer to the current MII bus.
116 * @regs: Base address of EMAC memory-mapped control registers.
117 * @napi: Structure for NAPI.
118 * @rxbd: Pointer to Rx BD ring.
119 * @txbd: Pointer to Tx BD ring.
120 * @rxbd_dma: DMA handle for Rx BD ring.
121 * @txbd_dma: DMA handle for Tx BD ring.
122 * @rx_buff: Storage for Rx buffers states.
123 * @tx_buff: Storage for Tx buffers states.
124 * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
125 * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
126 * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
127 * @link: PHY's last seen link state.
128 * @duplex: PHY's last set duplex mode.
129 * @speed: PHY's last set speed.
130 */
131struct arc_emac_priv {
132 const char *drv_name;
133 void (*set_mac_speed)(void *priv, unsigned int speed);
134
135 /* Devices */
136 struct device *dev;
137 struct mii_bus *bus;
138 struct arc_emac_mdio_bus_data bus_data;
139
140 void __iomem *regs;
141 struct clk *clk;
142
143 struct napi_struct napi;
144
145 struct arc_emac_bd *rxbd;
146 struct arc_emac_bd *txbd;
147
148 dma_addr_t rxbd_dma;
149 dma_addr_t txbd_dma;
150
151 struct buffer_state rx_buff[RX_BD_NUM];
152 struct buffer_state tx_buff[TX_BD_NUM];
153 unsigned int txbd_curr;
154 unsigned int txbd_dirty;
155
156 unsigned int last_rx_bd;
157
158 unsigned int link;
159 unsigned int duplex;
160 unsigned int speed;
161
162 unsigned int rx_missed_errors;
163};
164
165/**
166 * arc_reg_set - Sets EMAC register with provided value.
167 * @priv: Pointer to ARC EMAC private data structure.
168 * @reg: Register offset from base address.
169 * @value: Value to set in register.
170 */
171static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
172{
173 iowrite32(value, priv->regs + reg * sizeof(int));
174}
175
176/**
177 * arc_reg_get - Gets value of specified EMAC register.
178 * @priv: Pointer to ARC EMAC private data structure.
179 * @reg: Register offset from base address.
180 *
181 * returns: Value of requested register.
182 */
183static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
184{
185 return ioread32(priv->regs + reg * sizeof(int));
186}
187
188/**
189 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
190 * @priv: Pointer to ARC EMAC private data structure.
191 * @reg: Register offset from base address.
192 * @mask: Mask to apply to specified register.
193 *
194 * This function reads initial register value, then applies provided mask
195 * to it and then writes register back.
196 */
197static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
198{
199 unsigned int value = arc_reg_get(priv, reg);
200
201 arc_reg_set(priv, reg, value | mask);
202}
203
204/**
205 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
206 * @priv: Pointer to ARC EMAC private data structure.
207 * @reg: Register offset from base address.
208 * @mask: Mask to apply to specified register.
209 *
210 * This function reads initial register value, then applies provided mask
211 * to it and then writes register back.
212 */
213static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
214{
215 unsigned int value = arc_reg_get(priv, reg);
216
217 arc_reg_set(priv, reg, value & ~mask);
218}
219
220int arc_mdio_probe(struct arc_emac_priv *priv);
221int arc_mdio_remove(struct arc_emac_priv *priv);
222int arc_emac_probe(struct net_device *ndev, int interface);
223void arc_emac_remove(struct net_device *ndev);
224
225#endif /* ARC_EMAC_H */
1/*
2 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
3 *
4 * Registers and bits definitions of ARC EMAC
5 */
6
7#ifndef ARC_EMAC_H
8#define ARC_EMAC_H
9
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/phy.h>
14#include <linux/clk.h>
15
16/* STATUS and ENABLE Register bit masks */
17#define TXINT_MASK (1<<0) /* Transmit interrupt */
18#define RXINT_MASK (1<<1) /* Receive interrupt */
19#define ERR_MASK (1<<2) /* Error interrupt */
20#define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
21#define MSER_MASK (1<<4) /* Missed packet counter error */
22#define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
23#define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
24#define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
25#define MDIO_MASK (1<<12) /* MDIO complete interrupt */
26#define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */
27
28/* CONTROL Register bit masks */
29#define EN_MASK (1<<0) /* VMAC enable */
30#define TXRN_MASK (1<<3) /* TX enable */
31#define RXRN_MASK (1<<4) /* RX enable */
32#define DSBC_MASK (1<<8) /* Disable receive broadcast */
33#define ENFL_MASK (1<<10) /* Enable Full-duplex */
34#define PROM_MASK (1<<11) /* Promiscuous mode */
35
36/* Buffer descriptor INFO bit masks */
37#define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */
38#define FIRST_MASK (1<<16) /* First buffer in chain */
39#define LAST_MASK (1<<17) /* Last buffer in chain */
40#define LEN_MASK 0x000007FF /* last 11 bits */
41#define CRLS (1<<21)
42#define DEFR (1<<22)
43#define DROP (1<<23)
44#define RTRY (1<<24)
45#define LTCL (1<<28)
46#define UFLO (1<<29)
47
48#define FOR_EMAC OWN_MASK
49#define FOR_CPU 0
50
51/* ARC EMAC register set combines entries for MAC and MDIO */
52enum {
53 R_ID = 0,
54 R_STATUS,
55 R_ENABLE,
56 R_CTRL,
57 R_POLLRATE,
58 R_RXERR,
59 R_MISS,
60 R_TX_RING,
61 R_RX_RING,
62 R_ADDRL,
63 R_ADDRH,
64 R_LAFL,
65 R_LAFH,
66 R_MDIO,
67};
68
69#define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */
70
71#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
72
73#define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
74
75/**
76 * struct arc_emac_bd - EMAC buffer descriptor (BD).
77 *
78 * @info: Contains status information on the buffer itself.
79 * @data: 32-bit byte addressable pointer to the packet data.
80 */
81struct arc_emac_bd {
82 __le32 info;
83 dma_addr_t data;
84};
85
86/* Number of Rx/Tx BD's */
87#define RX_BD_NUM 128
88#define TX_BD_NUM 128
89
90#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
91#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
92
93/**
94 * struct buffer_state - Stores Rx/Tx buffer state.
95 * @sk_buff: Pointer to socket buffer.
96 * @addr: Start address of DMA-mapped memory region.
97 * @len: Length of DMA-mapped memory region.
98 */
99struct buffer_state {
100 struct sk_buff *skb;
101 DEFINE_DMA_UNMAP_ADDR(addr);
102 DEFINE_DMA_UNMAP_LEN(len);
103};
104
105/**
106 * struct arc_emac_priv - Storage of EMAC's private information.
107 * @dev: Pointer to the current device.
108 * @ndev: Pointer to the current network device.
109 * @phy_dev: Pointer to attached PHY device.
110 * @bus: Pointer to the current MII bus.
111 * @regs: Base address of EMAC memory-mapped control registers.
112 * @napi: Structure for NAPI.
113 * @stats: Network device statistics.
114 * @rxbd: Pointer to Rx BD ring.
115 * @txbd: Pointer to Tx BD ring.
116 * @rxbd_dma: DMA handle for Rx BD ring.
117 * @txbd_dma: DMA handle for Tx BD ring.
118 * @rx_buff: Storage for Rx buffers states.
119 * @tx_buff: Storage for Tx buffers states.
120 * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
121 * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
122 * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
123 * @link: PHY's last seen link state.
124 * @duplex: PHY's last set duplex mode.
125 * @speed: PHY's last set speed.
126 */
127struct arc_emac_priv {
128 /* Devices */
129 struct device *dev;
130 struct net_device *ndev;
131 struct phy_device *phy_dev;
132 struct mii_bus *bus;
133
134 void __iomem *regs;
135 struct clk *clk;
136
137 struct napi_struct napi;
138 struct net_device_stats stats;
139
140 struct arc_emac_bd *rxbd;
141 struct arc_emac_bd *txbd;
142
143 dma_addr_t rxbd_dma;
144 dma_addr_t txbd_dma;
145
146 struct buffer_state rx_buff[RX_BD_NUM];
147 struct buffer_state tx_buff[TX_BD_NUM];
148 unsigned int txbd_curr;
149 unsigned int txbd_dirty;
150
151 unsigned int last_rx_bd;
152
153 unsigned int link;
154 unsigned int duplex;
155 unsigned int speed;
156};
157
158/**
159 * arc_reg_set - Sets EMAC register with provided value.
160 * @priv: Pointer to ARC EMAC private data structure.
161 * @reg: Register offset from base address.
162 * @value: Value to set in register.
163 */
164static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
165{
166 iowrite32(value, priv->regs + reg * sizeof(int));
167}
168
169/**
170 * arc_reg_get - Gets value of specified EMAC register.
171 * @priv: Pointer to ARC EMAC private data structure.
172 * @reg: Register offset from base address.
173 *
174 * returns: Value of requested register.
175 */
176static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
177{
178 return ioread32(priv->regs + reg * sizeof(int));
179}
180
181/**
182 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
183 * @priv: Pointer to ARC EMAC private data structure.
184 * @reg: Register offset from base address.
185 * @mask: Mask to apply to specified register.
186 *
187 * This function reads initial register value, then applies provided mask
188 * to it and then writes register back.
189 */
190static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
191{
192 unsigned int value = arc_reg_get(priv, reg);
193 arc_reg_set(priv, reg, value | mask);
194}
195
196/**
197 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
198 * @priv: Pointer to ARC EMAC private data structure.
199 * @reg: Register offset from base address.
200 * @mask: Mask to apply to specified register.
201 *
202 * This function reads initial register value, then applies provided mask
203 * to it and then writes register back.
204 */
205static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
206{
207 unsigned int value = arc_reg_get(priv, reg);
208 arc_reg_set(priv, reg, value & ~mask);
209}
210
211int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv);
212int arc_mdio_remove(struct arc_emac_priv *priv);
213
214#endif /* ARC_EMAC_H */