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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
4 *
5 * Contributors:
6 * Dalon Westergreen
7 * Thomas Chou
8 * Ian Abbott
9 * Yuriy Kozlov
10 * Tobias Klauser
11 * Andriy Smolskyy
12 * Roman Bulgakov
13 * Dmytro Mytarchuk
14 * Matthew Gerlach
15 *
16 * Original driver contributed by SLS.
17 * Major updates contributed by GlobalLogic
18 */
19
20#ifndef __ALTERA_TSE_H__
21#define __ALTERA_TSE_H__
22
23#define ALTERA_TSE_RESOURCE_NAME "altera_tse"
24
25#include <linux/bitops.h>
26#include <linux/if_vlan.h>
27#include <linux/list.h>
28#include <linux/netdevice.h>
29#include <linux/phy.h>
30#include <linux/phylink.h>
31
32#define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000
33#define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
34 * bytes
35 */
36/* Rx FIFO default settings */
37#define ALTERA_TSE_RX_SECTION_EMPTY 16
38#define ALTERA_TSE_RX_SECTION_FULL 0
39#define ALTERA_TSE_RX_ALMOST_EMPTY 8
40#define ALTERA_TSE_RX_ALMOST_FULL 8
41
42/* Tx FIFO default settings */
43#define ALTERA_TSE_TX_SECTION_EMPTY 16
44#define ALTERA_TSE_TX_SECTION_FULL 0
45#define ALTERA_TSE_TX_ALMOST_EMPTY 8
46#define ALTERA_TSE_TX_ALMOST_FULL 3
47
48/* MAC function configuration default settings */
49#define ALTERA_TSE_TX_IPG_LENGTH 12
50
51#define ALTERA_TSE_PAUSE_QUANTA 0xffff
52
53#define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
54
55/* MAC Command_Config Register Bit Definitions
56 */
57#define MAC_CMDCFG_TX_ENA BIT(0)
58#define MAC_CMDCFG_RX_ENA BIT(1)
59#define MAC_CMDCFG_XON_GEN BIT(2)
60#define MAC_CMDCFG_ETH_SPEED BIT(3)
61#define MAC_CMDCFG_PROMIS_EN BIT(4)
62#define MAC_CMDCFG_PAD_EN BIT(5)
63#define MAC_CMDCFG_CRC_FWD BIT(6)
64#define MAC_CMDCFG_PAUSE_FWD BIT(7)
65#define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
66#define MAC_CMDCFG_TX_ADDR_INS BIT(9)
67#define MAC_CMDCFG_HD_ENA BIT(10)
68#define MAC_CMDCFG_EXCESS_COL BIT(11)
69#define MAC_CMDCFG_LATE_COL BIT(12)
70#define MAC_CMDCFG_SW_RESET BIT(13)
71#define MAC_CMDCFG_MHASH_SEL BIT(14)
72#define MAC_CMDCFG_LOOP_ENA BIT(15)
73#define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
74#define MAC_CMDCFG_MAGIC_ENA BIT(19)
75#define MAC_CMDCFG_SLEEP BIT(20)
76#define MAC_CMDCFG_WAKEUP BIT(21)
77#define MAC_CMDCFG_XOFF_GEN BIT(22)
78#define MAC_CMDCFG_CNTL_FRM_ENA BIT(23)
79#define MAC_CMDCFG_NO_LGTH_CHECK BIT(24)
80#define MAC_CMDCFG_ENA_10 BIT(25)
81#define MAC_CMDCFG_RX_ERR_DISC BIT(26)
82#define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27)
83#define MAC_CMDCFG_CNT_RESET BIT(31)
84
85#define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
86#define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
87#define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
88#define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
89#define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
90#define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
91#define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
92#define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
93#define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
94#define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
95#define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
96#define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
97#define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
98#define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
99#define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
100#define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
101#define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
102#define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
103#define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
104#define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
105#define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
106#define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
107#define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
108#define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
109#define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
110#define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
111#define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
112
113/* MDIO registers within MAC register Space
114 */
115struct altera_tse_mdio {
116 u32 control; /* PHY device operation control register */
117 u32 status; /* PHY device operation status register */
118 u32 phy_id1; /* Bits 31:16 of PHY identifier */
119 u32 phy_id2; /* Bits 15:0 of PHY identifier */
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
121 * advertisement
122 * register
123 */
124 u32 remote_partner_base_page_ability;
125
126 u32 reg6;
127 u32 reg7;
128 u32 reg8;
129 u32 reg9;
130 u32 rega;
131 u32 regb;
132 u32 regc;
133 u32 regd;
134 u32 rege;
135 u32 regf;
136 u32 reg10;
137 u32 reg11;
138 u32 reg12;
139 u32 reg13;
140 u32 reg14;
141 u32 reg15;
142 u32 reg16;
143 u32 reg17;
144 u32 reg18;
145 u32 reg19;
146 u32 reg1a;
147 u32 reg1b;
148 u32 reg1c;
149 u32 reg1d;
150 u32 reg1e;
151 u32 reg1f;
152};
153
154/* MAC register Space. Note that some of these registers may or may not be
155 * present depending upon options chosen by the user when the core was
156 * configured and built. Please consult the Altera Triple Speed Ethernet User
157 * Guide for details.
158 */
159struct altera_tse_mac {
160 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
161 * specific revision
162 */
163 u32 megacore_revision;
164 /* Provides a memory location for user applications to test the device
165 * memory operation.
166 */
167 u32 scratch_pad;
168 /* The host processor uses this register to control and configure the
169 * MAC block
170 */
171 u32 command_config;
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
173 * MAC address
174 */
175 u32 mac_addr_0;
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
177 * MAC address
178 */
179 u32 mac_addr_1;
180 /* 14-bit maximum frame length. The MAC receive logic */
181 u32 frm_length;
182 /* The pause quanta is used in each pause frame sent to a remote
183 * Ethernet device, in increments of 512 Ethernet bit times
184 */
185 u32 pause_quanta;
186 /* 12-bit receive FIFO section-empty threshold */
187 u32 rx_section_empty;
188 /* 12-bit receive FIFO section-full threshold */
189 u32 rx_section_full;
190 /* 12-bit transmit FIFO section-empty threshold */
191 u32 tx_section_empty;
192 /* 12-bit transmit FIFO section-full threshold */
193 u32 tx_section_full;
194 /* 12-bit receive FIFO almost-empty threshold */
195 u32 rx_almost_empty;
196 /* 12-bit receive FIFO almost-full threshold */
197 u32 rx_almost_full;
198 /* 12-bit transmit FIFO almost-empty threshold */
199 u32 tx_almost_empty;
200 /* 12-bit transmit FIFO almost-full threshold */
201 u32 tx_almost_full;
202 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
203 u32 mdio_phy0_addr;
204 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
205 u32 mdio_phy1_addr;
206
207 /* Bit[15:0]—16-bit holdoff quanta */
208 u32 holdoff_quant;
209
210 /* only if 100/1000 BaseX PCS, reserved otherwise */
211 u32 reserved1[5];
212
213 /* Minimum IPG between consecutive transmit frame in terms of bytes */
214 u32 tx_ipg_length;
215
216 /* IEEE 802.3 oEntity Managed Object Support */
217
218 /* The MAC addresses */
219 u32 mac_id_1;
220 u32 mac_id_2;
221
222 /* Number of frames transmitted without error including pause frames */
223 u32 frames_transmitted_ok;
224 /* Number of frames received without error including pause frames */
225 u32 frames_received_ok;
226 /* Number of frames received with a CRC error */
227 u32 frames_check_sequence_errors;
228 /* Frame received with an alignment error */
229 u32 alignment_errors;
230 /* Sum of payload and padding octets of frames transmitted without
231 * error
232 */
233 u32 octets_transmitted_ok;
234 /* Sum of payload and padding octets of frames received without error */
235 u32 octets_received_ok;
236
237 /* IEEE 802.3 oPausedEntity Managed Object Support */
238
239 /* Number of transmitted pause frames */
240 u32 tx_pause_mac_ctrl_frames;
241 /* Number of Received pause frames */
242 u32 rx_pause_mac_ctrl_frames;
243
244 /* IETF MIB (MIB-II) Object Support */
245
246 /* Number of frames received with error */
247 u32 if_in_errors;
248 /* Number of frames transmitted with error */
249 u32 if_out_errors;
250 /* Number of valid received unicast frames */
251 u32 if_in_ucast_pkts;
252 /* Number of valid received multicasts frames (without pause) */
253 u32 if_in_multicast_pkts;
254 /* Number of valid received broadcast frames */
255 u32 if_in_broadcast_pkts;
256 u32 if_out_discards;
257 /* The number of valid unicast frames transmitted */
258 u32 if_out_ucast_pkts;
259 /* The number of valid multicast frames transmitted,
260 * excluding pause frames
261 */
262 u32 if_out_multicast_pkts;
263 u32 if_out_broadcast_pkts;
264
265 /* IETF RMON MIB Object Support */
266
267 /* Counts the number of dropped packets due to internal errors
268 * of the MAC client.
269 */
270 u32 ether_stats_drop_events;
271 /* Total number of bytes received. Good and bad frames. */
272 u32 ether_stats_octets;
273 /* Total number of packets received. Counts good and bad packets. */
274 u32 ether_stats_pkts;
275 /* Number of packets received with less than 64 bytes. */
276 u32 ether_stats_undersize_pkts;
277 /* The number of frames received that are longer than the
278 * value configured in the frm_length register
279 */
280 u32 ether_stats_oversize_pkts;
281 /* Number of received packet with 64 bytes */
282 u32 ether_stats_pkts_64_octets;
283 /* Frames (good and bad) with 65 to 127 bytes */
284 u32 ether_stats_pkts_65to127_octets;
285 /* Frames (good and bad) with 128 to 255 bytes */
286 u32 ether_stats_pkts_128to255_octets;
287 /* Frames (good and bad) with 256 to 511 bytes */
288 u32 ether_stats_pkts_256to511_octets;
289 /* Frames (good and bad) with 512 to 1023 bytes */
290 u32 ether_stats_pkts_512to1023_octets;
291 /* Frames (good and bad) with 1024 to 1518 bytes */
292 u32 ether_stats_pkts_1024to1518_octets;
293
294 /* Any frame length from 1519 to the maximum length configured in the
295 * frm_length register, if it is greater than 1518
296 */
297 u32 ether_stats_pkts_1519tox_octets;
298 /* Too long frames with CRC error */
299 u32 ether_stats_jabbers;
300 /* Too short frames with CRC error */
301 u32 ether_stats_fragments;
302
303 u32 reserved2;
304
305 /* FIFO control register */
306 u32 tx_cmd_stat;
307 u32 rx_cmd_stat;
308
309 /* Extended Statistics Counters */
310 u32 msb_octets_transmitted_ok;
311 u32 msb_octets_received_ok;
312 u32 msb_ether_stats_octets;
313
314 u32 reserved3;
315
316 /* Multicast address resolution table, mapped in the controller address
317 * space
318 */
319 u32 hash_table[64];
320
321 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
322 * management interface
323 */
324 struct altera_tse_mdio mdio_phy0;
325 struct altera_tse_mdio mdio_phy1;
326
327 /* 4 Supplemental MAC Addresses */
328 u32 supp_mac_addr_0_0;
329 u32 supp_mac_addr_0_1;
330 u32 supp_mac_addr_1_0;
331 u32 supp_mac_addr_1_1;
332 u32 supp_mac_addr_2_0;
333 u32 supp_mac_addr_2_1;
334 u32 supp_mac_addr_3_0;
335 u32 supp_mac_addr_3_1;
336
337 u32 reserved4[8];
338
339 /* IEEE 1588v2 Feature */
340 u32 tx_period;
341 u32 tx_adjust_fns;
342 u32 tx_adjust_ns;
343 u32 rx_period;
344 u32 rx_adjust_fns;
345 u32 rx_adjust_ns;
346
347 u32 reserved5[42];
348};
349
350#define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
351
352/* Transmit and Receive Command Registers Bit Definitions
353 */
354#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
355#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18)
356#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25)
357
358/* Wrapper around a pointer to a socket buffer,
359 * so a DMA handle can be stored along with the buffer
360 */
361struct tse_buffer {
362 struct list_head lh;
363 struct sk_buff *skb;
364 dma_addr_t dma_addr;
365 u32 len;
366 int mapped_as_page;
367};
368
369struct altera_tse_private;
370
371#define ALTERA_DTYPE_SGDMA 1
372#define ALTERA_DTYPE_MSGDMA 2
373
374/* standard DMA interface for SGDMA and MSGDMA */
375struct altera_dmaops {
376 int altera_dtype;
377 int dmamask;
378 void (*reset_dma)(struct altera_tse_private *);
379 void (*enable_txirq)(struct altera_tse_private *);
380 void (*enable_rxirq)(struct altera_tse_private *);
381 void (*disable_txirq)(struct altera_tse_private *);
382 void (*disable_rxirq)(struct altera_tse_private *);
383 void (*clear_txirq)(struct altera_tse_private *);
384 void (*clear_rxirq)(struct altera_tse_private *);
385 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
386 u32 (*tx_completions)(struct altera_tse_private *);
387 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
388 u32 (*get_rx_status)(struct altera_tse_private *);
389 int (*init_dma)(struct altera_tse_private *);
390 void (*uninit_dma)(struct altera_tse_private *);
391 void (*start_rxdma)(struct altera_tse_private *);
392};
393
394/* This structure is private to each device.
395 */
396struct altera_tse_private {
397 struct net_device *dev;
398 struct device *device;
399 struct napi_struct napi;
400
401 /* MAC address space */
402 struct altera_tse_mac __iomem *mac_dev;
403
404 /* TSE Revision */
405 u32 revision;
406
407 /* mSGDMA Rx Dispatcher address space */
408 void __iomem *rx_dma_csr;
409 void __iomem *rx_dma_desc;
410 void __iomem *rx_dma_resp;
411
412 /* mSGDMA Tx Dispatcher address space */
413 void __iomem *tx_dma_csr;
414 void __iomem *tx_dma_desc;
415
416 /* SGMII PCS address space */
417 void __iomem *pcs_base;
418
419 /* Rx buffers queue */
420 struct tse_buffer *rx_ring;
421 u32 rx_cons;
422 u32 rx_prod;
423 u32 rx_ring_size;
424 u32 rx_dma_buf_sz;
425
426 /* Tx ring buffer */
427 struct tse_buffer *tx_ring;
428 u32 tx_prod;
429 u32 tx_cons;
430 u32 tx_ring_size;
431
432 /* Interrupts */
433 u32 tx_irq;
434 u32 rx_irq;
435
436 /* RX/TX MAC FIFO configs */
437 u32 tx_fifo_depth;
438 u32 rx_fifo_depth;
439
440 /* Hash filter settings */
441 u32 hash_filter;
442 u32 added_unicast;
443
444 /* Descriptor memory info for managing SGDMA */
445 u32 txdescmem;
446 u32 rxdescmem;
447 dma_addr_t rxdescmem_busaddr;
448 dma_addr_t txdescmem_busaddr;
449 u32 txctrlreg;
450 u32 rxctrlreg;
451 dma_addr_t rxdescphys;
452 dma_addr_t txdescphys;
453
454 struct list_head txlisthd;
455 struct list_head rxlisthd;
456
457 /* MAC command_config register protection */
458 spinlock_t mac_cfg_lock;
459 /* Tx path protection */
460 spinlock_t tx_lock;
461 /* Rx DMA & interrupt control protection */
462 spinlock_t rxdma_irq_lock;
463
464 /* PHY */
465 int phy_addr; /* PHY's MDIO address, -1 for autodetection */
466 phy_interface_t phy_iface;
467 struct mii_bus *mdio;
468 int oldspeed;
469 int oldduplex;
470 int oldlink;
471
472 /* ethtool msglvl option */
473 u32 msg_enable;
474
475 const struct altera_dmaops *dmaops;
476
477 struct phylink *phylink;
478 struct phylink_config phylink_config;
479 struct phylink_pcs *pcs;
480};
481
482/* Function prototypes
483 */
484void altera_tse_set_ethtool_ops(struct net_device *);
485
486static inline
487u32 csrrd32(void __iomem *mac, size_t offs)
488{
489 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
490 return readl(paddr);
491}
492
493static inline
494u16 csrrd16(void __iomem *mac, size_t offs)
495{
496 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
497 return readw(paddr);
498}
499
500static inline
501u8 csrrd8(void __iomem *mac, size_t offs)
502{
503 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
504 return readb(paddr);
505}
506
507static inline
508void csrwr32(u32 val, void __iomem *mac, size_t offs)
509{
510 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
511
512 writel(val, paddr);
513}
514
515static inline
516void csrwr16(u16 val, void __iomem *mac, size_t offs)
517{
518 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
519
520 writew(val, paddr);
521}
522
523static inline
524void csrwr8(u8 val, void __iomem *mac, size_t offs)
525{
526 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
527
528 writeb(val, paddr);
529}
530
531#endif /* __ALTERA_TSE_H__ */
1/* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
3 *
4 * Contributors:
5 * Dalon Westergreen
6 * Thomas Chou
7 * Ian Abbott
8 * Yuriy Kozlov
9 * Tobias Klauser
10 * Andriy Smolskyy
11 * Roman Bulgakov
12 * Dmytro Mytarchuk
13 * Matthew Gerlach
14 *
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#ifndef __ALTERA_TSE_H__
32#define __ALTERA_TSE_H__
33
34#define ALTERA_TSE_RESOURCE_NAME "altera_tse"
35
36#include <linux/bitops.h>
37#include <linux/if_vlan.h>
38#include <linux/list.h>
39#include <linux/netdevice.h>
40#include <linux/phy.h>
41
42#define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000
43#define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
44 * bytes
45 */
46/* Rx FIFO default settings */
47#define ALTERA_TSE_RX_SECTION_EMPTY 16
48#define ALTERA_TSE_RX_SECTION_FULL 0
49#define ALTERA_TSE_RX_ALMOST_EMPTY 8
50#define ALTERA_TSE_RX_ALMOST_FULL 8
51
52/* Tx FIFO default settings */
53#define ALTERA_TSE_TX_SECTION_EMPTY 16
54#define ALTERA_TSE_TX_SECTION_FULL 0
55#define ALTERA_TSE_TX_ALMOST_EMPTY 8
56#define ALTERA_TSE_TX_ALMOST_FULL 3
57
58/* MAC function configuration default settings */
59#define ALTERA_TSE_TX_IPG_LENGTH 12
60
61#define ALTERA_TSE_PAUSE_QUANTA 0xffff
62
63#define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
64
65/* MAC Command_Config Register Bit Definitions
66 */
67#define MAC_CMDCFG_TX_ENA BIT(0)
68#define MAC_CMDCFG_RX_ENA BIT(1)
69#define MAC_CMDCFG_XON_GEN BIT(2)
70#define MAC_CMDCFG_ETH_SPEED BIT(3)
71#define MAC_CMDCFG_PROMIS_EN BIT(4)
72#define MAC_CMDCFG_PAD_EN BIT(5)
73#define MAC_CMDCFG_CRC_FWD BIT(6)
74#define MAC_CMDCFG_PAUSE_FWD BIT(7)
75#define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
76#define MAC_CMDCFG_TX_ADDR_INS BIT(9)
77#define MAC_CMDCFG_HD_ENA BIT(10)
78#define MAC_CMDCFG_EXCESS_COL BIT(11)
79#define MAC_CMDCFG_LATE_COL BIT(12)
80#define MAC_CMDCFG_SW_RESET BIT(13)
81#define MAC_CMDCFG_MHASH_SEL BIT(14)
82#define MAC_CMDCFG_LOOP_ENA BIT(15)
83#define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
84#define MAC_CMDCFG_MAGIC_ENA BIT(19)
85#define MAC_CMDCFG_SLEEP BIT(20)
86#define MAC_CMDCFG_WAKEUP BIT(21)
87#define MAC_CMDCFG_XOFF_GEN BIT(22)
88#define MAC_CMDCFG_CNTL_FRM_ENA BIT(23)
89#define MAC_CMDCFG_NO_LGTH_CHECK BIT(24)
90#define MAC_CMDCFG_ENA_10 BIT(25)
91#define MAC_CMDCFG_RX_ERR_DISC BIT(26)
92#define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27)
93#define MAC_CMDCFG_CNT_RESET BIT(31)
94
95#define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
96#define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
97#define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
98#define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
99#define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
100#define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
101#define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
102#define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
103#define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
104#define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
105#define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
106#define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
107#define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
108#define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
109#define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
110#define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
111#define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
112#define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
113#define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
114#define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
115#define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
116#define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
117#define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
118#define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
119#define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
120#define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
121#define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
122
123/* MDIO registers within MAC register Space
124 */
125struct altera_tse_mdio {
126 u32 control; /* PHY device operation control register */
127 u32 status; /* PHY device operation status register */
128 u32 phy_id1; /* Bits 31:16 of PHY identifier */
129 u32 phy_id2; /* Bits 15:0 of PHY identifier */
130 u32 auto_negotiation_advertisement; /* Auto-negotiation
131 * advertisement
132 * register
133 */
134 u32 remote_partner_base_page_ability;
135
136 u32 reg6;
137 u32 reg7;
138 u32 reg8;
139 u32 reg9;
140 u32 rega;
141 u32 regb;
142 u32 regc;
143 u32 regd;
144 u32 rege;
145 u32 regf;
146 u32 reg10;
147 u32 reg11;
148 u32 reg12;
149 u32 reg13;
150 u32 reg14;
151 u32 reg15;
152 u32 reg16;
153 u32 reg17;
154 u32 reg18;
155 u32 reg19;
156 u32 reg1a;
157 u32 reg1b;
158 u32 reg1c;
159 u32 reg1d;
160 u32 reg1e;
161 u32 reg1f;
162};
163
164/* MAC register Space. Note that some of these registers may or may not be
165 * present depending upon options chosen by the user when the core was
166 * configured and built. Please consult the Altera Triple Speed Ethernet User
167 * Guide for details.
168 */
169struct altera_tse_mac {
170 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
171 * specific revision
172 */
173 u32 megacore_revision;
174 /* Provides a memory location for user applications to test the device
175 * memory operation.
176 */
177 u32 scratch_pad;
178 /* The host processor uses this register to control and configure the
179 * MAC block
180 */
181 u32 command_config;
182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
183 * MAC address
184 */
185 u32 mac_addr_0;
186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
187 * MAC address
188 */
189 u32 mac_addr_1;
190 /* 14-bit maximum frame length. The MAC receive logic */
191 u32 frm_length;
192 /* The pause quanta is used in each pause frame sent to a remote
193 * Ethernet device, in increments of 512 Ethernet bit times
194 */
195 u32 pause_quanta;
196 /* 12-bit receive FIFO section-empty threshold */
197 u32 rx_section_empty;
198 /* 12-bit receive FIFO section-full threshold */
199 u32 rx_section_full;
200 /* 12-bit transmit FIFO section-empty threshold */
201 u32 tx_section_empty;
202 /* 12-bit transmit FIFO section-full threshold */
203 u32 tx_section_full;
204 /* 12-bit receive FIFO almost-empty threshold */
205 u32 rx_almost_empty;
206 /* 12-bit receive FIFO almost-full threshold */
207 u32 rx_almost_full;
208 /* 12-bit transmit FIFO almost-empty threshold */
209 u32 tx_almost_empty;
210 /* 12-bit transmit FIFO almost-full threshold */
211 u32 tx_almost_full;
212 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
213 u32 mdio_phy0_addr;
214 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
215 u32 mdio_phy1_addr;
216
217 /* Bit[15:0]—16-bit holdoff quanta */
218 u32 holdoff_quant;
219
220 /* only if 100/1000 BaseX PCS, reserved otherwise */
221 u32 reserved1[5];
222
223 /* Minimum IPG between consecutive transmit frame in terms of bytes */
224 u32 tx_ipg_length;
225
226 /* IEEE 802.3 oEntity Managed Object Support */
227
228 /* The MAC addresses */
229 u32 mac_id_1;
230 u32 mac_id_2;
231
232 /* Number of frames transmitted without error including pause frames */
233 u32 frames_transmitted_ok;
234 /* Number of frames received without error including pause frames */
235 u32 frames_received_ok;
236 /* Number of frames received with a CRC error */
237 u32 frames_check_sequence_errors;
238 /* Frame received with an alignment error */
239 u32 alignment_errors;
240 /* Sum of payload and padding octets of frames transmitted without
241 * error
242 */
243 u32 octets_transmitted_ok;
244 /* Sum of payload and padding octets of frames received without error */
245 u32 octets_received_ok;
246
247 /* IEEE 802.3 oPausedEntity Managed Object Support */
248
249 /* Number of transmitted pause frames */
250 u32 tx_pause_mac_ctrl_frames;
251 /* Number of Received pause frames */
252 u32 rx_pause_mac_ctrl_frames;
253
254 /* IETF MIB (MIB-II) Object Support */
255
256 /* Number of frames received with error */
257 u32 if_in_errors;
258 /* Number of frames transmitted with error */
259 u32 if_out_errors;
260 /* Number of valid received unicast frames */
261 u32 if_in_ucast_pkts;
262 /* Number of valid received multicasts frames (without pause) */
263 u32 if_in_multicast_pkts;
264 /* Number of valid received broadcast frames */
265 u32 if_in_broadcast_pkts;
266 u32 if_out_discards;
267 /* The number of valid unicast frames transmitted */
268 u32 if_out_ucast_pkts;
269 /* The number of valid multicast frames transmitted,
270 * excluding pause frames
271 */
272 u32 if_out_multicast_pkts;
273 u32 if_out_broadcast_pkts;
274
275 /* IETF RMON MIB Object Support */
276
277 /* Counts the number of dropped packets due to internal errors
278 * of the MAC client.
279 */
280 u32 ether_stats_drop_events;
281 /* Total number of bytes received. Good and bad frames. */
282 u32 ether_stats_octets;
283 /* Total number of packets received. Counts good and bad packets. */
284 u32 ether_stats_pkts;
285 /* Number of packets received with less than 64 bytes. */
286 u32 ether_stats_undersize_pkts;
287 /* The number of frames received that are longer than the
288 * value configured in the frm_length register
289 */
290 u32 ether_stats_oversize_pkts;
291 /* Number of received packet with 64 bytes */
292 u32 ether_stats_pkts_64_octets;
293 /* Frames (good and bad) with 65 to 127 bytes */
294 u32 ether_stats_pkts_65to127_octets;
295 /* Frames (good and bad) with 128 to 255 bytes */
296 u32 ether_stats_pkts_128to255_octets;
297 /* Frames (good and bad) with 256 to 511 bytes */
298 u32 ether_stats_pkts_256to511_octets;
299 /* Frames (good and bad) with 512 to 1023 bytes */
300 u32 ether_stats_pkts_512to1023_octets;
301 /* Frames (good and bad) with 1024 to 1518 bytes */
302 u32 ether_stats_pkts_1024to1518_octets;
303
304 /* Any frame length from 1519 to the maximum length configured in the
305 * frm_length register, if it is greater than 1518
306 */
307 u32 ether_stats_pkts_1519tox_octets;
308 /* Too long frames with CRC error */
309 u32 ether_stats_jabbers;
310 /* Too short frames with CRC error */
311 u32 ether_stats_fragments;
312
313 u32 reserved2;
314
315 /* FIFO control register */
316 u32 tx_cmd_stat;
317 u32 rx_cmd_stat;
318
319 /* Extended Statistics Counters */
320 u32 msb_octets_transmitted_ok;
321 u32 msb_octets_received_ok;
322 u32 msb_ether_stats_octets;
323
324 u32 reserved3;
325
326 /* Multicast address resolution table, mapped in the controller address
327 * space
328 */
329 u32 hash_table[64];
330
331 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
332 * management interface
333 */
334 struct altera_tse_mdio mdio_phy0;
335 struct altera_tse_mdio mdio_phy1;
336
337 /* 4 Supplemental MAC Addresses */
338 u32 supp_mac_addr_0_0;
339 u32 supp_mac_addr_0_1;
340 u32 supp_mac_addr_1_0;
341 u32 supp_mac_addr_1_1;
342 u32 supp_mac_addr_2_0;
343 u32 supp_mac_addr_2_1;
344 u32 supp_mac_addr_3_0;
345 u32 supp_mac_addr_3_1;
346
347 u32 reserved4[8];
348
349 /* IEEE 1588v2 Feature */
350 u32 tx_period;
351 u32 tx_adjust_fns;
352 u32 tx_adjust_ns;
353 u32 rx_period;
354 u32 rx_adjust_fns;
355 u32 rx_adjust_ns;
356
357 u32 reserved5[42];
358};
359
360#define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
361
362/* Transmit and Receive Command Registers Bit Definitions
363 */
364#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
365#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18)
366#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25)
367
368/* Wrapper around a pointer to a socket buffer,
369 * so a DMA handle can be stored along with the buffer
370 */
371struct tse_buffer {
372 struct list_head lh;
373 struct sk_buff *skb;
374 dma_addr_t dma_addr;
375 u32 len;
376 int mapped_as_page;
377};
378
379struct altera_tse_private;
380
381#define ALTERA_DTYPE_SGDMA 1
382#define ALTERA_DTYPE_MSGDMA 2
383
384/* standard DMA interface for SGDMA and MSGDMA */
385struct altera_dmaops {
386 int altera_dtype;
387 int dmamask;
388 void (*reset_dma)(struct altera_tse_private *);
389 void (*enable_txirq)(struct altera_tse_private *);
390 void (*enable_rxirq)(struct altera_tse_private *);
391 void (*disable_txirq)(struct altera_tse_private *);
392 void (*disable_rxirq)(struct altera_tse_private *);
393 void (*clear_txirq)(struct altera_tse_private *);
394 void (*clear_rxirq)(struct altera_tse_private *);
395 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
396 u32 (*tx_completions)(struct altera_tse_private *);
397 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
398 u32 (*get_rx_status)(struct altera_tse_private *);
399 int (*init_dma)(struct altera_tse_private *);
400 void (*uninit_dma)(struct altera_tse_private *);
401 void (*start_rxdma)(struct altera_tse_private *);
402};
403
404/* This structure is private to each device.
405 */
406struct altera_tse_private {
407 struct net_device *dev;
408 struct device *device;
409 struct napi_struct napi;
410
411 /* MAC address space */
412 struct altera_tse_mac __iomem *mac_dev;
413
414 /* TSE Revision */
415 u32 revision;
416
417 /* mSGDMA Rx Dispatcher address space */
418 void __iomem *rx_dma_csr;
419 void __iomem *rx_dma_desc;
420 void __iomem *rx_dma_resp;
421
422 /* mSGDMA Tx Dispatcher address space */
423 void __iomem *tx_dma_csr;
424 void __iomem *tx_dma_desc;
425
426 /* Rx buffers queue */
427 struct tse_buffer *rx_ring;
428 u32 rx_cons;
429 u32 rx_prod;
430 u32 rx_ring_size;
431 u32 rx_dma_buf_sz;
432
433 /* Tx ring buffer */
434 struct tse_buffer *tx_ring;
435 u32 tx_prod;
436 u32 tx_cons;
437 u32 tx_ring_size;
438
439 /* Interrupts */
440 u32 tx_irq;
441 u32 rx_irq;
442
443 /* RX/TX MAC FIFO configs */
444 u32 tx_fifo_depth;
445 u32 rx_fifo_depth;
446 u32 max_mtu;
447
448 /* Hash filter settings */
449 u32 hash_filter;
450 u32 added_unicast;
451
452 /* Descriptor memory info for managing SGDMA */
453 u32 txdescmem;
454 u32 rxdescmem;
455 dma_addr_t rxdescmem_busaddr;
456 dma_addr_t txdescmem_busaddr;
457 u32 txctrlreg;
458 u32 rxctrlreg;
459 dma_addr_t rxdescphys;
460 dma_addr_t txdescphys;
461 size_t sgdmadesclen;
462
463 struct list_head txlisthd;
464 struct list_head rxlisthd;
465
466 /* MAC command_config register protection */
467 spinlock_t mac_cfg_lock;
468 /* Tx path protection */
469 spinlock_t tx_lock;
470 /* Rx DMA & interrupt control protection */
471 spinlock_t rxdma_irq_lock;
472
473 /* PHY */
474 int phy_addr; /* PHY's MDIO address, -1 for autodetection */
475 phy_interface_t phy_iface;
476 struct mii_bus *mdio;
477 struct phy_device *phydev;
478 int oldspeed;
479 int oldduplex;
480 int oldlink;
481
482 /* ethtool msglvl option */
483 u32 msg_enable;
484
485 struct altera_dmaops *dmaops;
486};
487
488/* Function prototypes
489 */
490void altera_tse_set_ethtool_ops(struct net_device *);
491
492static inline
493u32 csrrd32(void __iomem *mac, size_t offs)
494{
495 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
496 return readl(paddr);
497}
498
499static inline
500u16 csrrd16(void __iomem *mac, size_t offs)
501{
502 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
503 return readw(paddr);
504}
505
506static inline
507u8 csrrd8(void __iomem *mac, size_t offs)
508{
509 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
510 return readb(paddr);
511}
512
513static inline
514void csrwr32(u32 val, void __iomem *mac, size_t offs)
515{
516 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
517
518 writel(val, paddr);
519}
520
521static inline
522void csrwr16(u16 val, void __iomem *mac, size_t offs)
523{
524 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
525
526 writew(val, paddr);
527}
528
529static inline
530void csrwr8(u8 val, void __iomem *mac, size_t offs)
531{
532 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
533
534 writeb(val, paddr);
535}
536
537#endif /* __ALTERA_TSE_H__ */