Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Altera TSE SGDMA and MSGDMA Linux driver
3 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 */
5
6#ifndef __ALTERA_MSGDMAHW_H__
7#define __ALTERA_MSGDMAHW_H__
8
9/* mSGDMA extended descriptor format
10 */
11struct msgdma_extended_desc {
12 u32 read_addr_lo; /* data buffer source address low bits */
13 u32 write_addr_lo; /* data buffer destination address low bits */
14 u32 len; /* the number of bytes to transfer
15 * per descriptor
16 */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
19 * bit 15:0 sequence number
20 */
21 u32 stride; /* bit 31:16 write stride
22 * bit 15:0 read stride
23 */
24 u32 read_addr_hi; /* data buffer source address high bits */
25 u32 write_addr_hi; /* data buffer destination address high bits */
26 u32 control; /* characteristics of the transfer */
27};
28
29/* mSGDMA descriptor control field bit definitions
30 */
31#define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
32#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
33#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
34#define MSGDMA_DESC_CTL_PARK_READS BIT(10)
35#define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
36#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
37#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
38#define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
39#define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
40#define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
41#define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)
42/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
43 * descriptor FIFO(s)
44 */
45#define MSGDMA_DESC_CTL_GO BIT(31)
46
47/* Tx buffer control flags
48 */
49#define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \
50 MSGDMA_DESC_CTL_GO)
51
52#define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_GO)
53
54#define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \
55 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
56 MSGDMA_DESC_CTL_GO)
57
58#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
59 MSGDMA_DESC_CTL_GEN_EOP | \
60 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
61 MSGDMA_DESC_CTL_GO)
62
63#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
64 MSGDMA_DESC_CTL_END_ON_LEN | \
65 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
66 MSGDMA_DESC_CTL_EARLY_IRQ | \
67 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
68 MSGDMA_DESC_CTL_GO)
69
70/* mSGDMA extended descriptor stride definitions
71 */
72#define MSGDMA_DESC_TX_STRIDE (0x00010001)
73#define MSGDMA_DESC_RX_STRIDE (0x00010001)
74
75/* mSGDMA dispatcher control and status register map
76 */
77struct msgdma_csr {
78 u32 status; /* Read/Clear */
79 u32 control; /* Read/Write */
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
82 */
83 u32 resp_fill_level; /* bit 15:0 */
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
85 * bit 15:0 - read sequence number
86 */
87 u32 pad[3]; /* reserved */
88};
89
90/* mSGDMA CSR status register bit definitions
91 */
92#define MSGDMA_CSR_STAT_BUSY BIT(0)
93#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)
94#define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2)
95#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3)
96#define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4)
97#define MSGDMA_CSR_STAT_STOPPED BIT(5)
98#define MSGDMA_CSR_STAT_RESETTING BIT(6)
99#define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7)
100#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)
101#define MSGDMA_CSR_STAT_IRQ BIT(9)
102#define MSGDMA_CSR_STAT_MASK 0x3FF
103#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF
104
105#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)
106#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)
107#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)
108#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)
109#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)
110#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)
111#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)
112#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)
113#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)
114#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)
115
116/* mSGDMA CSR control register bit definitions
117 */
118#define MSGDMA_CSR_CTL_STOP BIT(0)
119#define MSGDMA_CSR_CTL_RESET BIT(1)
120#define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2)
121#define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3)
122#define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4)
123#define MSGDMA_CSR_CTL_STOP_DESCS BIT(5)
124
125/* mSGDMA CSR fill level bits
126 */
127#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
128#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
129#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
130
131/* mSGDMA response register map
132 */
133struct msgdma_response {
134 u32 bytes_transferred;
135 u32 status;
136};
137
138#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
139#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
140#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
141
142/* mSGDMA response register bit definitions
143 */
144#define MSGDMA_RESP_EARLY_TERM BIT(8)
145#define MSGDMA_RESP_ERR_MASK 0xFF
146
147#endif /* __ALTERA_MSGDMA_H__*/
1/* Altera TSE SGDMA and MSGDMA Linux driver
2 * Copyright (C) 2014 Altera Corporation. All rights reserved
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __ALTERA_MSGDMAHW_H__
18#define __ALTERA_MSGDMAHW_H__
19
20/* mSGDMA extended descriptor format
21 */
22struct msgdma_extended_desc {
23 u32 read_addr_lo; /* data buffer source address low bits */
24 u32 write_addr_lo; /* data buffer destination address low bits */
25 u32 len; /* the number of bytes to transfer
26 * per descriptor
27 */
28 u32 burst_seq_num; /* bit 31:24 write burst
29 * bit 23:16 read burst
30 * bit 15:0 sequence number
31 */
32 u32 stride; /* bit 31:16 write stride
33 * bit 15:0 read stride
34 */
35 u32 read_addr_hi; /* data buffer source address high bits */
36 u32 write_addr_hi; /* data buffer destination address high bits */
37 u32 control; /* characteristics of the transfer */
38};
39
40/* mSGDMA descriptor control field bit definitions
41 */
42#define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
43#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
44#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
45#define MSGDMA_DESC_CTL_PARK_READS BIT(10)
46#define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
47#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
48#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
49#define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
50#define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
51#define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
52#define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)
53/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
54 * descriptor FIFO(s)
55 */
56#define MSGDMA_DESC_CTL_GO BIT(31)
57
58/* Tx buffer control flags
59 */
60#define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \
61 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
62 MSGDMA_DESC_CTL_GO)
63
64#define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_TR_ERR_IRQ | \
65 MSGDMA_DESC_CTL_GO)
66
67#define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \
68 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
69 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
70 MSGDMA_DESC_CTL_GO)
71
72#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
73 MSGDMA_DESC_CTL_GEN_EOP | \
74 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
75 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
76 MSGDMA_DESC_CTL_GO)
77
78#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
79 MSGDMA_DESC_CTL_END_ON_LEN | \
80 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
81 MSGDMA_DESC_CTL_EARLY_IRQ | \
82 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
83 MSGDMA_DESC_CTL_GO)
84
85/* mSGDMA extended descriptor stride definitions
86 */
87#define MSGDMA_DESC_TX_STRIDE (0x00010001)
88#define MSGDMA_DESC_RX_STRIDE (0x00010001)
89
90/* mSGDMA dispatcher control and status register map
91 */
92struct msgdma_csr {
93 u32 status; /* Read/Clear */
94 u32 control; /* Read/Write */
95 u32 rw_fill_level; /* bit 31:16 - write fill level
96 * bit 15:0 - read fill level
97 */
98 u32 resp_fill_level; /* bit 15:0 */
99 u32 rw_seq_num; /* bit 31:16 - write sequence number
100 * bit 15:0 - read sequence number
101 */
102 u32 pad[3]; /* reserved */
103};
104
105/* mSGDMA CSR status register bit definitions
106 */
107#define MSGDMA_CSR_STAT_BUSY BIT(0)
108#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)
109#define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2)
110#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3)
111#define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4)
112#define MSGDMA_CSR_STAT_STOPPED BIT(5)
113#define MSGDMA_CSR_STAT_RESETTING BIT(6)
114#define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7)
115#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)
116#define MSGDMA_CSR_STAT_IRQ BIT(9)
117#define MSGDMA_CSR_STAT_MASK 0x3FF
118#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF
119
120#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)
121#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)
122#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)
123#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)
124#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)
125#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)
126#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)
127#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)
128#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)
129#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)
130
131/* mSGDMA CSR control register bit definitions
132 */
133#define MSGDMA_CSR_CTL_STOP BIT(0)
134#define MSGDMA_CSR_CTL_RESET BIT(1)
135#define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2)
136#define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3)
137#define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4)
138#define MSGDMA_CSR_CTL_STOP_DESCS BIT(5)
139
140/* mSGDMA CSR fill level bits
141 */
142#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
143#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
144#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
145
146/* mSGDMA response register map
147 */
148struct msgdma_response {
149 u32 bytes_transferred;
150 u32 status;
151};
152
153#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
154#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
155#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
156
157/* mSGDMA response register bit definitions
158 */
159#define MSGDMA_RESP_EARLY_TERM BIT(8)
160#define MSGDMA_RESP_ERR_MASK 0xFF
161
162#endif /* __ALTERA_MSGDMA_H__*/