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1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13 * written by:
14 * Copyright
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17 *
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
22 *
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/netdevice.h>
33#include <linux/if_arp.h>
34#include <linux/if_ether.h>
35#include <linux/list.h>
36#include <linux/io.h>
37#include <linux/pm_runtime.h>
38
39#include <linux/can.h>
40#include <linux/can/dev.h>
41#include <linux/can/error.h>
42#include <linux/can/led.h>
43
44#include "c_can.h"
45
46/* Number of interface registers */
47#define IF_ENUM_REG_LEN 11
48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
49
50/* control extension register D_CAN specific */
51#define CONTROL_EX_PDR BIT(8)
52
53/* control register */
54#define CONTROL_TEST BIT(7)
55#define CONTROL_CCE BIT(6)
56#define CONTROL_DISABLE_AR BIT(5)
57#define CONTROL_ENABLE_AR (0 << 5)
58#define CONTROL_EIE BIT(3)
59#define CONTROL_SIE BIT(2)
60#define CONTROL_IE BIT(1)
61#define CONTROL_INIT BIT(0)
62
63#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
64
65/* test register */
66#define TEST_RX BIT(7)
67#define TEST_TX1 BIT(6)
68#define TEST_TX2 BIT(5)
69#define TEST_LBACK BIT(4)
70#define TEST_SILENT BIT(3)
71#define TEST_BASIC BIT(2)
72
73/* status register */
74#define STATUS_PDA BIT(10)
75#define STATUS_BOFF BIT(7)
76#define STATUS_EWARN BIT(6)
77#define STATUS_EPASS BIT(5)
78#define STATUS_RXOK BIT(4)
79#define STATUS_TXOK BIT(3)
80
81/* error counter register */
82#define ERR_CNT_TEC_MASK 0xff
83#define ERR_CNT_TEC_SHIFT 0
84#define ERR_CNT_REC_SHIFT 8
85#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
86#define ERR_CNT_RP_SHIFT 15
87#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
88
89/* bit-timing register */
90#define BTR_BRP_MASK 0x3f
91#define BTR_BRP_SHIFT 0
92#define BTR_SJW_SHIFT 6
93#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
94#define BTR_TSEG1_SHIFT 8
95#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
96#define BTR_TSEG2_SHIFT 12
97#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
98
99/* brp extension register */
100#define BRP_EXT_BRPE_MASK 0x0f
101#define BRP_EXT_BRPE_SHIFT 0
102
103/* IFx command request */
104#define IF_COMR_BUSY BIT(15)
105
106/* IFx command mask */
107#define IF_COMM_WR BIT(7)
108#define IF_COMM_MASK BIT(6)
109#define IF_COMM_ARB BIT(5)
110#define IF_COMM_CONTROL BIT(4)
111#define IF_COMM_CLR_INT_PND BIT(3)
112#define IF_COMM_TXRQST BIT(2)
113#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
114#define IF_COMM_DATAA BIT(1)
115#define IF_COMM_DATAB BIT(0)
116
117/* TX buffer setup */
118#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
119 IF_COMM_TXRQST | \
120 IF_COMM_DATAA | IF_COMM_DATAB)
121
122/* For the low buffers we clear the interrupt bit, but keep newdat */
123#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
124 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
125 IF_COMM_DATAA | IF_COMM_DATAB)
126
127/* For the high buffers we clear the interrupt bit and newdat */
128#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
129
130
131/* Receive setup of message objects */
132#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
133
134/* Invalidation of message objects */
135#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
136
137/* IFx arbitration */
138#define IF_ARB_MSGVAL BIT(31)
139#define IF_ARB_MSGXTD BIT(30)
140#define IF_ARB_TRANSMIT BIT(29)
141
142/* IFx message control */
143#define IF_MCONT_NEWDAT BIT(15)
144#define IF_MCONT_MSGLST BIT(14)
145#define IF_MCONT_INTPND BIT(13)
146#define IF_MCONT_UMASK BIT(12)
147#define IF_MCONT_TXIE BIT(11)
148#define IF_MCONT_RXIE BIT(10)
149#define IF_MCONT_RMTEN BIT(9)
150#define IF_MCONT_TXRQST BIT(8)
151#define IF_MCONT_EOB BIT(7)
152#define IF_MCONT_DLC_MASK 0xf
153
154#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
155#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
156
157#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
158
159/*
160 * Use IF1 for RX and IF2 for TX
161 */
162#define IF_RX 0
163#define IF_TX 1
164
165/* minimum timeout for checking BUSY status */
166#define MIN_TIMEOUT_VALUE 6
167
168/* Wait for ~1 sec for INIT bit */
169#define INIT_WAIT_MS 1000
170
171/* napi related */
172#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
173
174/* c_can lec values */
175enum c_can_lec_type {
176 LEC_NO_ERROR = 0,
177 LEC_STUFF_ERROR,
178 LEC_FORM_ERROR,
179 LEC_ACK_ERROR,
180 LEC_BIT1_ERROR,
181 LEC_BIT0_ERROR,
182 LEC_CRC_ERROR,
183 LEC_UNUSED,
184 LEC_MASK = LEC_UNUSED,
185};
186
187/*
188 * c_can error types:
189 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
190 */
191enum c_can_bus_error_types {
192 C_CAN_NO_ERROR = 0,
193 C_CAN_BUS_OFF,
194 C_CAN_ERROR_WARNING,
195 C_CAN_ERROR_PASSIVE,
196};
197
198static const struct can_bittiming_const c_can_bittiming_const = {
199 .name = KBUILD_MODNAME,
200 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
201 .tseg1_max = 16,
202 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
203 .tseg2_max = 8,
204 .sjw_max = 4,
205 .brp_min = 1,
206 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
207 .brp_inc = 1,
208};
209
210static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
211{
212 if (priv->device)
213 pm_runtime_enable(priv->device);
214}
215
216static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
217{
218 if (priv->device)
219 pm_runtime_disable(priv->device);
220}
221
222static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
223{
224 if (priv->device)
225 pm_runtime_get_sync(priv->device);
226}
227
228static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
229{
230 if (priv->device)
231 pm_runtime_put_sync(priv->device);
232}
233
234static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
235{
236 if (priv->raminit)
237 priv->raminit(priv, enable);
238}
239
240static void c_can_irq_control(struct c_can_priv *priv, bool enable)
241{
242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
243
244 if (enable)
245 ctrl |= CONTROL_IRQMSK;
246
247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
248}
249
250static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
251{
252 struct c_can_priv *priv = netdev_priv(dev);
253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
254
255 priv->write_reg(priv, reg + 1, cmd);
256 priv->write_reg(priv, reg, obj);
257
258 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
259 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
260 return;
261 udelay(1);
262 }
263 netdev_err(dev, "Updating object timed out\n");
264
265}
266
267static inline void c_can_object_get(struct net_device *dev, int iface,
268 u32 obj, u32 cmd)
269{
270 c_can_obj_update(dev, iface, cmd, obj);
271}
272
273static inline void c_can_object_put(struct net_device *dev, int iface,
274 u32 obj, u32 cmd)
275{
276 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
277}
278
279/*
280 * Note: According to documentation clearing TXIE while MSGVAL is set
281 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
282 * load significantly.
283 */
284static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
285{
286 struct c_can_priv *priv = netdev_priv(dev);
287
288 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
289 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
290}
291
292static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
293{
294 struct c_can_priv *priv = netdev_priv(dev);
295
296 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
297 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
298 c_can_inval_tx_object(dev, iface, obj);
299}
300
301static void c_can_setup_tx_object(struct net_device *dev, int iface,
302 struct can_frame *frame, int idx)
303{
304 struct c_can_priv *priv = netdev_priv(dev);
305 u16 ctrl = IF_MCONT_TX | frame->can_dlc;
306 bool rtr = frame->can_id & CAN_RTR_FLAG;
307 u32 arb = IF_ARB_MSGVAL;
308 int i;
309
310 if (frame->can_id & CAN_EFF_FLAG) {
311 arb |= frame->can_id & CAN_EFF_MASK;
312 arb |= IF_ARB_MSGXTD;
313 } else {
314 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
315 }
316
317 if (!rtr)
318 arb |= IF_ARB_TRANSMIT;
319
320 /*
321 * If we change the DIR bit, we need to invalidate the buffer
322 * first, i.e. clear the MSGVAL flag in the arbiter.
323 */
324 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
325 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
326
327 c_can_inval_msg_object(dev, iface, obj);
328 change_bit(idx, &priv->tx_dir);
329 }
330
331 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
332 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), arb >> 16);
333
334 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
335
336 for (i = 0; i < frame->can_dlc; i += 2) {
337 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
338 frame->data[i] | (frame->data[i + 1] << 8));
339 }
340}
341
342static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
343 int iface)
344{
345 int i;
346
347 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++)
348 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT);
349}
350
351static int c_can_handle_lost_msg_obj(struct net_device *dev,
352 int iface, int objno, u32 ctrl)
353{
354 struct net_device_stats *stats = &dev->stats;
355 struct c_can_priv *priv = netdev_priv(dev);
356 struct can_frame *frame;
357 struct sk_buff *skb;
358
359 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
360 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
361 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
362
363 stats->rx_errors++;
364 stats->rx_over_errors++;
365
366 /* create an error msg */
367 skb = alloc_can_err_skb(dev, &frame);
368 if (unlikely(!skb))
369 return 0;
370
371 frame->can_id |= CAN_ERR_CRTL;
372 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
373
374 netif_receive_skb(skb);
375 return 1;
376}
377
378static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
379{
380 struct net_device_stats *stats = &dev->stats;
381 struct c_can_priv *priv = netdev_priv(dev);
382 struct can_frame *frame;
383 struct sk_buff *skb;
384 u32 arb, data;
385
386 skb = alloc_can_skb(dev, &frame);
387 if (!skb) {
388 stats->rx_dropped++;
389 return -ENOMEM;
390 }
391
392 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
393
394 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface));
395 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16;
396
397 if (arb & IF_ARB_MSGXTD)
398 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
399 else
400 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
401
402 if (arb & IF_ARB_TRANSMIT) {
403 frame->can_id |= CAN_RTR_FLAG;
404 } else {
405 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
406
407 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) {
408 data = priv->read_reg(priv, dreg);
409 frame->data[i] = data;
410 frame->data[i + 1] = data >> 8;
411 }
412 }
413
414 stats->rx_packets++;
415 stats->rx_bytes += frame->can_dlc;
416
417 netif_receive_skb(skb);
418 return 0;
419}
420
421static void c_can_setup_receive_object(struct net_device *dev, int iface,
422 u32 obj, u32 mask, u32 id, u32 mcont)
423{
424 struct c_can_priv *priv = netdev_priv(dev);
425
426 mask |= BIT(29);
427 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
428 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16);
429
430 id |= IF_ARB_MSGVAL;
431 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id);
432 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16);
433
434 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
435 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
436}
437
438static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
439 struct net_device *dev)
440{
441 struct can_frame *frame = (struct can_frame *)skb->data;
442 struct c_can_priv *priv = netdev_priv(dev);
443 u32 idx, obj;
444
445 if (can_dropped_invalid_skb(dev, skb))
446 return NETDEV_TX_OK;
447 /*
448 * This is not a FIFO. C/D_CAN sends out the buffers
449 * prioritized. The lowest buffer number wins.
450 */
451 idx = fls(atomic_read(&priv->tx_active));
452 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
453
454 /* If this is the last buffer, stop the xmit queue */
455 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1)
456 netif_stop_queue(dev);
457 /*
458 * Store the message in the interface so we can call
459 * can_put_echo_skb(). We must do this before we enable
460 * transmit as we might race against do_tx().
461 */
462 c_can_setup_tx_object(dev, IF_TX, frame, idx);
463 priv->dlc[idx] = frame->can_dlc;
464 can_put_echo_skb(skb, dev, idx);
465
466 /* Update the active bits */
467 atomic_add((1 << idx), &priv->tx_active);
468 /* Start transmission */
469 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
470
471 return NETDEV_TX_OK;
472}
473
474static int c_can_wait_for_ctrl_init(struct net_device *dev,
475 struct c_can_priv *priv, u32 init)
476{
477 int retry = 0;
478
479 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
480 udelay(10);
481 if (retry++ > 1000) {
482 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
483 return -EIO;
484 }
485 }
486 return 0;
487}
488
489static int c_can_set_bittiming(struct net_device *dev)
490{
491 unsigned int reg_btr, reg_brpe, ctrl_save;
492 u8 brp, brpe, sjw, tseg1, tseg2;
493 u32 ten_bit_brp;
494 struct c_can_priv *priv = netdev_priv(dev);
495 const struct can_bittiming *bt = &priv->can.bittiming;
496 int res;
497
498 /* c_can provides a 6-bit brp and 4-bit brpe fields */
499 ten_bit_brp = bt->brp - 1;
500 brp = ten_bit_brp & BTR_BRP_MASK;
501 brpe = ten_bit_brp >> 6;
502
503 sjw = bt->sjw - 1;
504 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
505 tseg2 = bt->phase_seg2 - 1;
506 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
507 (tseg2 << BTR_TSEG2_SHIFT);
508 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
509
510 netdev_info(dev,
511 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
512
513 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
514 ctrl_save &= ~CONTROL_INIT;
515 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
516 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
517 if (res)
518 return res;
519
520 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
521 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
522 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
523
524 return c_can_wait_for_ctrl_init(dev, priv, 0);
525}
526
527/*
528 * Configure C_CAN message objects for Tx and Rx purposes:
529 * C_CAN provides a total of 32 message objects that can be configured
530 * either for Tx or Rx purposes. Here the first 16 message objects are used as
531 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
532 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
533 * See user guide document for further details on configuring message
534 * objects.
535 */
536static void c_can_configure_msg_objects(struct net_device *dev)
537{
538 int i;
539
540 /* first invalidate all message objects */
541 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
542 c_can_inval_msg_object(dev, IF_RX, i);
543
544 /* setup receive message objects */
545 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
546 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
547
548 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
549 IF_MCONT_RCV_EOB);
550}
551
552/*
553 * Configure C_CAN chip:
554 * - enable/disable auto-retransmission
555 * - set operating mode
556 * - configure message objects
557 */
558static int c_can_chip_config(struct net_device *dev)
559{
560 struct c_can_priv *priv = netdev_priv(dev);
561
562 /* enable automatic retransmission */
563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
564
565 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
566 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
567 /* loopback + silent mode : useful for hot self-test */
568 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
569 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
571 /* loopback mode : useful for self-test function */
572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
573 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
574 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
575 /* silent mode : bus-monitoring mode */
576 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
577 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
578 }
579
580 /* configure message objects */
581 c_can_configure_msg_objects(dev);
582
583 /* set a `lec` value so that we can check for updates later */
584 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
585
586 /* Clear all internal status */
587 atomic_set(&priv->tx_active, 0);
588 priv->rxmasked = 0;
589 priv->tx_dir = 0;
590
591 /* set bittiming params */
592 return c_can_set_bittiming(dev);
593}
594
595static int c_can_start(struct net_device *dev)
596{
597 struct c_can_priv *priv = netdev_priv(dev);
598 int err;
599
600 /* basic c_can configuration */
601 err = c_can_chip_config(dev);
602 if (err)
603 return err;
604
605 /* Setup the command for new messages */
606 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
607 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
608
609 priv->can.state = CAN_STATE_ERROR_ACTIVE;
610
611 return 0;
612}
613
614static void c_can_stop(struct net_device *dev)
615{
616 struct c_can_priv *priv = netdev_priv(dev);
617
618 c_can_irq_control(priv, false);
619 priv->can.state = CAN_STATE_STOPPED;
620}
621
622static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
623{
624 struct c_can_priv *priv = netdev_priv(dev);
625 int err;
626
627 switch (mode) {
628 case CAN_MODE_START:
629 err = c_can_start(dev);
630 if (err)
631 return err;
632 netif_wake_queue(dev);
633 c_can_irq_control(priv, true);
634 break;
635 default:
636 return -EOPNOTSUPP;
637 }
638
639 return 0;
640}
641
642static int __c_can_get_berr_counter(const struct net_device *dev,
643 struct can_berr_counter *bec)
644{
645 unsigned int reg_err_counter;
646 struct c_can_priv *priv = netdev_priv(dev);
647
648 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
649 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
650 ERR_CNT_REC_SHIFT;
651 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
652
653 return 0;
654}
655
656static int c_can_get_berr_counter(const struct net_device *dev,
657 struct can_berr_counter *bec)
658{
659 struct c_can_priv *priv = netdev_priv(dev);
660 int err;
661
662 c_can_pm_runtime_get_sync(priv);
663 err = __c_can_get_berr_counter(dev, bec);
664 c_can_pm_runtime_put_sync(priv);
665
666 return err;
667}
668
669static void c_can_do_tx(struct net_device *dev)
670{
671 struct c_can_priv *priv = netdev_priv(dev);
672 struct net_device_stats *stats = &dev->stats;
673 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
674
675 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
676
677 while ((idx = ffs(pend))) {
678 idx--;
679 pend &= ~(1 << idx);
680 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
681 c_can_inval_tx_object(dev, IF_RX, obj);
682 can_get_echo_skb(dev, idx);
683 bytes += priv->dlc[idx];
684 pkts++;
685 }
686
687 /* Clear the bits in the tx_active mask */
688 atomic_sub(clr, &priv->tx_active);
689
690 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1)))
691 netif_wake_queue(dev);
692
693 if (pkts) {
694 stats->tx_bytes += bytes;
695 stats->tx_packets += pkts;
696 can_led_event(dev, CAN_LED_EVENT_TX);
697 }
698}
699
700/*
701 * If we have a gap in the pending bits, that means we either
702 * raced with the hardware or failed to readout all upper
703 * objects in the last run due to quota limit.
704 */
705static u32 c_can_adjust_pending(u32 pend)
706{
707 u32 weight, lasts;
708
709 if (pend == RECEIVE_OBJECT_BITS)
710 return pend;
711
712 /*
713 * If the last set bit is larger than the number of pending
714 * bits we have a gap.
715 */
716 weight = hweight32(pend);
717 lasts = fls(pend);
718
719 /* If the bits are linear, nothing to do */
720 if (lasts == weight)
721 return pend;
722
723 /*
724 * Find the first set bit after the gap. We walk backwards
725 * from the last set bit.
726 */
727 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
728
729 return pend & ~((1 << lasts) - 1);
730}
731
732static inline void c_can_rx_object_get(struct net_device *dev,
733 struct c_can_priv *priv, u32 obj)
734{
735 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
736}
737
738static inline void c_can_rx_finalize(struct net_device *dev,
739 struct c_can_priv *priv, u32 obj)
740{
741 if (priv->type != BOSCH_D_CAN)
742 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
743}
744
745static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
746 u32 pend, int quota)
747{
748 u32 pkts = 0, ctrl, obj;
749
750 while ((obj = ffs(pend)) && quota > 0) {
751 pend &= ~BIT(obj - 1);
752
753 c_can_rx_object_get(dev, priv, obj);
754 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
755
756 if (ctrl & IF_MCONT_MSGLST) {
757 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
758
759 pkts += n;
760 quota -= n;
761 continue;
762 }
763
764 /*
765 * This really should not happen, but this covers some
766 * odd HW behaviour. Do not remove that unless you
767 * want to brick your machine.
768 */
769 if (!(ctrl & IF_MCONT_NEWDAT))
770 continue;
771
772 /* read the data from the message object */
773 c_can_read_msg_object(dev, IF_RX, ctrl);
774
775 c_can_rx_finalize(dev, priv, obj);
776
777 pkts++;
778 quota--;
779 }
780
781 return pkts;
782}
783
784static inline u32 c_can_get_pending(struct c_can_priv *priv)
785{
786 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
787
788 return pend;
789}
790
791/*
792 * theory of operation:
793 *
794 * c_can core saves a received CAN message into the first free message
795 * object it finds free (starting with the lowest). Bits NEWDAT and
796 * INTPND are set for this message object indicating that a new message
797 * has arrived. To work-around this issue, we keep two groups of message
798 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
799 *
800 * We clear the newdat bit right away.
801 *
802 * This can result in packet reordering when the readout is slow.
803 */
804static int c_can_do_rx_poll(struct net_device *dev, int quota)
805{
806 struct c_can_priv *priv = netdev_priv(dev);
807 u32 pkts = 0, pend = 0, toread, n;
808
809 /*
810 * It is faster to read only one 16bit register. This is only possible
811 * for a maximum number of 16 objects.
812 */
813 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
814 "Implementation does not support more message objects than 16");
815
816 while (quota > 0) {
817 if (!pend) {
818 pend = c_can_get_pending(priv);
819 if (!pend)
820 break;
821 /*
822 * If the pending field has a gap, handle the
823 * bits above the gap first.
824 */
825 toread = c_can_adjust_pending(pend);
826 } else {
827 toread = pend;
828 }
829 /* Remove the bits from pend */
830 pend &= ~toread;
831 /* Read the objects */
832 n = c_can_read_objects(dev, priv, toread, quota);
833 pkts += n;
834 quota -= n;
835 }
836
837 if (pkts)
838 can_led_event(dev, CAN_LED_EVENT_RX);
839
840 return pkts;
841}
842
843static int c_can_handle_state_change(struct net_device *dev,
844 enum c_can_bus_error_types error_type)
845{
846 unsigned int reg_err_counter;
847 unsigned int rx_err_passive;
848 struct c_can_priv *priv = netdev_priv(dev);
849 struct net_device_stats *stats = &dev->stats;
850 struct can_frame *cf;
851 struct sk_buff *skb;
852 struct can_berr_counter bec;
853
854 switch (error_type) {
855 case C_CAN_ERROR_WARNING:
856 /* error warning state */
857 priv->can.can_stats.error_warning++;
858 priv->can.state = CAN_STATE_ERROR_WARNING;
859 break;
860 case C_CAN_ERROR_PASSIVE:
861 /* error passive state */
862 priv->can.can_stats.error_passive++;
863 priv->can.state = CAN_STATE_ERROR_PASSIVE;
864 break;
865 case C_CAN_BUS_OFF:
866 /* bus-off state */
867 priv->can.state = CAN_STATE_BUS_OFF;
868 can_bus_off(dev);
869 break;
870 default:
871 break;
872 }
873
874 /* propagate the error condition to the CAN stack */
875 skb = alloc_can_err_skb(dev, &cf);
876 if (unlikely(!skb))
877 return 0;
878
879 __c_can_get_berr_counter(dev, &bec);
880 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
881 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
882 ERR_CNT_RP_SHIFT;
883
884 switch (error_type) {
885 case C_CAN_ERROR_WARNING:
886 /* error warning state */
887 cf->can_id |= CAN_ERR_CRTL;
888 cf->data[1] = (bec.txerr > bec.rxerr) ?
889 CAN_ERR_CRTL_TX_WARNING :
890 CAN_ERR_CRTL_RX_WARNING;
891 cf->data[6] = bec.txerr;
892 cf->data[7] = bec.rxerr;
893
894 break;
895 case C_CAN_ERROR_PASSIVE:
896 /* error passive state */
897 cf->can_id |= CAN_ERR_CRTL;
898 if (rx_err_passive)
899 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
900 if (bec.txerr > 127)
901 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
902
903 cf->data[6] = bec.txerr;
904 cf->data[7] = bec.rxerr;
905 break;
906 case C_CAN_BUS_OFF:
907 /* bus-off state */
908 cf->can_id |= CAN_ERR_BUSOFF;
909 can_bus_off(dev);
910 break;
911 default:
912 break;
913 }
914
915 stats->rx_packets++;
916 stats->rx_bytes += cf->can_dlc;
917 netif_receive_skb(skb);
918
919 return 1;
920}
921
922static int c_can_handle_bus_err(struct net_device *dev,
923 enum c_can_lec_type lec_type)
924{
925 struct c_can_priv *priv = netdev_priv(dev);
926 struct net_device_stats *stats = &dev->stats;
927 struct can_frame *cf;
928 struct sk_buff *skb;
929
930 /*
931 * early exit if no lec update or no error.
932 * no lec update means that no CAN bus event has been detected
933 * since CPU wrote 0x7 value to status reg.
934 */
935 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
936 return 0;
937
938 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
939 return 0;
940
941 /* common for all type of bus errors */
942 priv->can.can_stats.bus_error++;
943 stats->rx_errors++;
944
945 /* propagate the error condition to the CAN stack */
946 skb = alloc_can_err_skb(dev, &cf);
947 if (unlikely(!skb))
948 return 0;
949
950 /*
951 * check for 'last error code' which tells us the
952 * type of the last error to occur on the CAN bus
953 */
954 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
955 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
956
957 switch (lec_type) {
958 case LEC_STUFF_ERROR:
959 netdev_dbg(dev, "stuff error\n");
960 cf->data[2] |= CAN_ERR_PROT_STUFF;
961 break;
962 case LEC_FORM_ERROR:
963 netdev_dbg(dev, "form error\n");
964 cf->data[2] |= CAN_ERR_PROT_FORM;
965 break;
966 case LEC_ACK_ERROR:
967 netdev_dbg(dev, "ack error\n");
968 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
969 CAN_ERR_PROT_LOC_ACK_DEL);
970 break;
971 case LEC_BIT1_ERROR:
972 netdev_dbg(dev, "bit1 error\n");
973 cf->data[2] |= CAN_ERR_PROT_BIT1;
974 break;
975 case LEC_BIT0_ERROR:
976 netdev_dbg(dev, "bit0 error\n");
977 cf->data[2] |= CAN_ERR_PROT_BIT0;
978 break;
979 case LEC_CRC_ERROR:
980 netdev_dbg(dev, "CRC error\n");
981 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
982 CAN_ERR_PROT_LOC_CRC_DEL);
983 break;
984 default:
985 break;
986 }
987
988 stats->rx_packets++;
989 stats->rx_bytes += cf->can_dlc;
990 netif_receive_skb(skb);
991 return 1;
992}
993
994static int c_can_poll(struct napi_struct *napi, int quota)
995{
996 struct net_device *dev = napi->dev;
997 struct c_can_priv *priv = netdev_priv(dev);
998 u16 curr, last = priv->last_status;
999 int work_done = 0;
1000
1001 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
1002 /* Ack status on C_CAN. D_CAN is self clearing */
1003 if (priv->type != BOSCH_D_CAN)
1004 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1005
1006 /* handle state changes */
1007 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1008 netdev_dbg(dev, "entered error warning state\n");
1009 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1010 }
1011
1012 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1013 netdev_dbg(dev, "entered error passive state\n");
1014 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1015 }
1016
1017 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1018 netdev_dbg(dev, "entered bus off state\n");
1019 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1020 goto end;
1021 }
1022
1023 /* handle bus recovery events */
1024 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1025 netdev_dbg(dev, "left bus off state\n");
1026 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1027 }
1028 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1029 netdev_dbg(dev, "left error passive state\n");
1030 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1031 }
1032
1033 /* handle lec errors on the bus */
1034 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1035
1036 /* Handle Tx/Rx events. We do this unconditionally */
1037 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1038 c_can_do_tx(dev);
1039
1040end:
1041 if (work_done < quota) {
1042 napi_complete(napi);
1043 /* enable all IRQs if we are not in bus off state */
1044 if (priv->can.state != CAN_STATE_BUS_OFF)
1045 c_can_irq_control(priv, true);
1046 }
1047
1048 return work_done;
1049}
1050
1051static irqreturn_t c_can_isr(int irq, void *dev_id)
1052{
1053 struct net_device *dev = (struct net_device *)dev_id;
1054 struct c_can_priv *priv = netdev_priv(dev);
1055
1056 if (!priv->read_reg(priv, C_CAN_INT_REG))
1057 return IRQ_NONE;
1058
1059 /* disable all interrupts and schedule the NAPI */
1060 c_can_irq_control(priv, false);
1061 napi_schedule(&priv->napi);
1062
1063 return IRQ_HANDLED;
1064}
1065
1066static int c_can_open(struct net_device *dev)
1067{
1068 int err;
1069 struct c_can_priv *priv = netdev_priv(dev);
1070
1071 c_can_pm_runtime_get_sync(priv);
1072 c_can_reset_ram(priv, true);
1073
1074 /* open the can device */
1075 err = open_candev(dev);
1076 if (err) {
1077 netdev_err(dev, "failed to open can device\n");
1078 goto exit_open_fail;
1079 }
1080
1081 /* register interrupt handler */
1082 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1083 dev);
1084 if (err < 0) {
1085 netdev_err(dev, "failed to request interrupt\n");
1086 goto exit_irq_fail;
1087 }
1088
1089 /* start the c_can controller */
1090 err = c_can_start(dev);
1091 if (err)
1092 goto exit_start_fail;
1093
1094 can_led_event(dev, CAN_LED_EVENT_OPEN);
1095
1096 napi_enable(&priv->napi);
1097 /* enable status change, error and module interrupts */
1098 c_can_irq_control(priv, true);
1099 netif_start_queue(dev);
1100
1101 return 0;
1102
1103exit_start_fail:
1104 free_irq(dev->irq, dev);
1105exit_irq_fail:
1106 close_candev(dev);
1107exit_open_fail:
1108 c_can_reset_ram(priv, false);
1109 c_can_pm_runtime_put_sync(priv);
1110 return err;
1111}
1112
1113static int c_can_close(struct net_device *dev)
1114{
1115 struct c_can_priv *priv = netdev_priv(dev);
1116
1117 netif_stop_queue(dev);
1118 napi_disable(&priv->napi);
1119 c_can_stop(dev);
1120 free_irq(dev->irq, dev);
1121 close_candev(dev);
1122
1123 c_can_reset_ram(priv, false);
1124 c_can_pm_runtime_put_sync(priv);
1125
1126 can_led_event(dev, CAN_LED_EVENT_STOP);
1127
1128 return 0;
1129}
1130
1131struct net_device *alloc_c_can_dev(void)
1132{
1133 struct net_device *dev;
1134 struct c_can_priv *priv;
1135
1136 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1137 if (!dev)
1138 return NULL;
1139
1140 priv = netdev_priv(dev);
1141 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1142
1143 priv->dev = dev;
1144 priv->can.bittiming_const = &c_can_bittiming_const;
1145 priv->can.do_set_mode = c_can_set_mode;
1146 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1147 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1148 CAN_CTRLMODE_LISTENONLY |
1149 CAN_CTRLMODE_BERR_REPORTING;
1150
1151 return dev;
1152}
1153EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1154
1155#ifdef CONFIG_PM
1156int c_can_power_down(struct net_device *dev)
1157{
1158 u32 val;
1159 unsigned long time_out;
1160 struct c_can_priv *priv = netdev_priv(dev);
1161
1162 if (!(dev->flags & IFF_UP))
1163 return 0;
1164
1165 WARN_ON(priv->type != BOSCH_D_CAN);
1166
1167 /* set PDR value so the device goes to power down mode */
1168 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1169 val |= CONTROL_EX_PDR;
1170 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1171
1172 /* Wait for the PDA bit to get set */
1173 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1174 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1175 time_after(time_out, jiffies))
1176 cpu_relax();
1177
1178 if (time_after(jiffies, time_out))
1179 return -ETIMEDOUT;
1180
1181 c_can_stop(dev);
1182
1183 c_can_reset_ram(priv, false);
1184 c_can_pm_runtime_put_sync(priv);
1185
1186 return 0;
1187}
1188EXPORT_SYMBOL_GPL(c_can_power_down);
1189
1190int c_can_power_up(struct net_device *dev)
1191{
1192 u32 val;
1193 unsigned long time_out;
1194 struct c_can_priv *priv = netdev_priv(dev);
1195 int ret;
1196
1197 if (!(dev->flags & IFF_UP))
1198 return 0;
1199
1200 WARN_ON(priv->type != BOSCH_D_CAN);
1201
1202 c_can_pm_runtime_get_sync(priv);
1203 c_can_reset_ram(priv, true);
1204
1205 /* Clear PDR and INIT bits */
1206 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1207 val &= ~CONTROL_EX_PDR;
1208 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1209 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1210 val &= ~CONTROL_INIT;
1211 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1212
1213 /* Wait for the PDA bit to get clear */
1214 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1215 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1216 time_after(time_out, jiffies))
1217 cpu_relax();
1218
1219 if (time_after(jiffies, time_out))
1220 return -ETIMEDOUT;
1221
1222 ret = c_can_start(dev);
1223 if (!ret)
1224 c_can_irq_control(priv, true);
1225
1226 return ret;
1227}
1228EXPORT_SYMBOL_GPL(c_can_power_up);
1229#endif
1230
1231void free_c_can_dev(struct net_device *dev)
1232{
1233 struct c_can_priv *priv = netdev_priv(dev);
1234
1235 netif_napi_del(&priv->napi);
1236 free_candev(dev);
1237}
1238EXPORT_SYMBOL_GPL(free_c_can_dev);
1239
1240static const struct net_device_ops c_can_netdev_ops = {
1241 .ndo_open = c_can_open,
1242 .ndo_stop = c_can_close,
1243 .ndo_start_xmit = c_can_start_xmit,
1244 .ndo_change_mtu = can_change_mtu,
1245};
1246
1247int register_c_can_dev(struct net_device *dev)
1248{
1249 struct c_can_priv *priv = netdev_priv(dev);
1250 int err;
1251
1252 c_can_pm_runtime_enable(priv);
1253
1254 dev->flags |= IFF_ECHO; /* we support local echo */
1255 dev->netdev_ops = &c_can_netdev_ops;
1256
1257 err = register_candev(dev);
1258 if (err)
1259 c_can_pm_runtime_disable(priv);
1260 else
1261 devm_can_led_init(dev);
1262
1263 return err;
1264}
1265EXPORT_SYMBOL_GPL(register_c_can_dev);
1266
1267void unregister_c_can_dev(struct net_device *dev)
1268{
1269 struct c_can_priv *priv = netdev_priv(dev);
1270
1271 unregister_candev(dev);
1272
1273 c_can_pm_runtime_disable(priv);
1274}
1275EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1276
1277MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1278MODULE_LICENSE("GPL v2");
1279MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");