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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
4// http://www.samsung.com
5
6#include <linux/device.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/module.h>
10#include <linux/regmap.h>
11
12#include <linux/mfd/samsung/core.h>
13#include <linux/mfd/samsung/irq.h>
14#include <linux/mfd/samsung/s2mps11.h>
15#include <linux/mfd/samsung/s2mps14.h>
16#include <linux/mfd/samsung/s2mpu02.h>
17#include <linux/mfd/samsung/s5m8767.h>
18
19static const struct regmap_irq s2mps11_irqs[] = {
20 [S2MPS11_IRQ_PWRONF] = {
21 .reg_offset = 0,
22 .mask = S2MPS11_IRQ_PWRONF_MASK,
23 },
24 [S2MPS11_IRQ_PWRONR] = {
25 .reg_offset = 0,
26 .mask = S2MPS11_IRQ_PWRONR_MASK,
27 },
28 [S2MPS11_IRQ_JIGONBF] = {
29 .reg_offset = 0,
30 .mask = S2MPS11_IRQ_JIGONBF_MASK,
31 },
32 [S2MPS11_IRQ_JIGONBR] = {
33 .reg_offset = 0,
34 .mask = S2MPS11_IRQ_JIGONBR_MASK,
35 },
36 [S2MPS11_IRQ_ACOKBF] = {
37 .reg_offset = 0,
38 .mask = S2MPS11_IRQ_ACOKBF_MASK,
39 },
40 [S2MPS11_IRQ_ACOKBR] = {
41 .reg_offset = 0,
42 .mask = S2MPS11_IRQ_ACOKBR_MASK,
43 },
44 [S2MPS11_IRQ_PWRON1S] = {
45 .reg_offset = 0,
46 .mask = S2MPS11_IRQ_PWRON1S_MASK,
47 },
48 [S2MPS11_IRQ_MRB] = {
49 .reg_offset = 0,
50 .mask = S2MPS11_IRQ_MRB_MASK,
51 },
52 [S2MPS11_IRQ_RTC60S] = {
53 .reg_offset = 1,
54 .mask = S2MPS11_IRQ_RTC60S_MASK,
55 },
56 [S2MPS11_IRQ_RTCA1] = {
57 .reg_offset = 1,
58 .mask = S2MPS11_IRQ_RTCA1_MASK,
59 },
60 [S2MPS11_IRQ_RTCA0] = {
61 .reg_offset = 1,
62 .mask = S2MPS11_IRQ_RTCA0_MASK,
63 },
64 [S2MPS11_IRQ_SMPL] = {
65 .reg_offset = 1,
66 .mask = S2MPS11_IRQ_SMPL_MASK,
67 },
68 [S2MPS11_IRQ_RTC1S] = {
69 .reg_offset = 1,
70 .mask = S2MPS11_IRQ_RTC1S_MASK,
71 },
72 [S2MPS11_IRQ_WTSR] = {
73 .reg_offset = 1,
74 .mask = S2MPS11_IRQ_WTSR_MASK,
75 },
76 [S2MPS11_IRQ_INT120C] = {
77 .reg_offset = 2,
78 .mask = S2MPS11_IRQ_INT120C_MASK,
79 },
80 [S2MPS11_IRQ_INT140C] = {
81 .reg_offset = 2,
82 .mask = S2MPS11_IRQ_INT140C_MASK,
83 },
84};
85
86static const struct regmap_irq s2mps14_irqs[] = {
87 [S2MPS14_IRQ_PWRONF] = {
88 .reg_offset = 0,
89 .mask = S2MPS11_IRQ_PWRONF_MASK,
90 },
91 [S2MPS14_IRQ_PWRONR] = {
92 .reg_offset = 0,
93 .mask = S2MPS11_IRQ_PWRONR_MASK,
94 },
95 [S2MPS14_IRQ_JIGONBF] = {
96 .reg_offset = 0,
97 .mask = S2MPS11_IRQ_JIGONBF_MASK,
98 },
99 [S2MPS14_IRQ_JIGONBR] = {
100 .reg_offset = 0,
101 .mask = S2MPS11_IRQ_JIGONBR_MASK,
102 },
103 [S2MPS14_IRQ_ACOKBF] = {
104 .reg_offset = 0,
105 .mask = S2MPS11_IRQ_ACOKBF_MASK,
106 },
107 [S2MPS14_IRQ_ACOKBR] = {
108 .reg_offset = 0,
109 .mask = S2MPS11_IRQ_ACOKBR_MASK,
110 },
111 [S2MPS14_IRQ_PWRON1S] = {
112 .reg_offset = 0,
113 .mask = S2MPS11_IRQ_PWRON1S_MASK,
114 },
115 [S2MPS14_IRQ_MRB] = {
116 .reg_offset = 0,
117 .mask = S2MPS11_IRQ_MRB_MASK,
118 },
119 [S2MPS14_IRQ_RTC60S] = {
120 .reg_offset = 1,
121 .mask = S2MPS11_IRQ_RTC60S_MASK,
122 },
123 [S2MPS14_IRQ_RTCA1] = {
124 .reg_offset = 1,
125 .mask = S2MPS11_IRQ_RTCA1_MASK,
126 },
127 [S2MPS14_IRQ_RTCA0] = {
128 .reg_offset = 1,
129 .mask = S2MPS11_IRQ_RTCA0_MASK,
130 },
131 [S2MPS14_IRQ_SMPL] = {
132 .reg_offset = 1,
133 .mask = S2MPS11_IRQ_SMPL_MASK,
134 },
135 [S2MPS14_IRQ_RTC1S] = {
136 .reg_offset = 1,
137 .mask = S2MPS11_IRQ_RTC1S_MASK,
138 },
139 [S2MPS14_IRQ_WTSR] = {
140 .reg_offset = 1,
141 .mask = S2MPS11_IRQ_WTSR_MASK,
142 },
143 [S2MPS14_IRQ_INT120C] = {
144 .reg_offset = 2,
145 .mask = S2MPS11_IRQ_INT120C_MASK,
146 },
147 [S2MPS14_IRQ_INT140C] = {
148 .reg_offset = 2,
149 .mask = S2MPS11_IRQ_INT140C_MASK,
150 },
151 [S2MPS14_IRQ_TSD] = {
152 .reg_offset = 2,
153 .mask = S2MPS14_IRQ_TSD_MASK,
154 },
155};
156
157static const struct regmap_irq s2mpu02_irqs[] = {
158 [S2MPU02_IRQ_PWRONF] = {
159 .reg_offset = 0,
160 .mask = S2MPS11_IRQ_PWRONF_MASK,
161 },
162 [S2MPU02_IRQ_PWRONR] = {
163 .reg_offset = 0,
164 .mask = S2MPS11_IRQ_PWRONR_MASK,
165 },
166 [S2MPU02_IRQ_JIGONBF] = {
167 .reg_offset = 0,
168 .mask = S2MPS11_IRQ_JIGONBF_MASK,
169 },
170 [S2MPU02_IRQ_JIGONBR] = {
171 .reg_offset = 0,
172 .mask = S2MPS11_IRQ_JIGONBR_MASK,
173 },
174 [S2MPU02_IRQ_ACOKBF] = {
175 .reg_offset = 0,
176 .mask = S2MPS11_IRQ_ACOKBF_MASK,
177 },
178 [S2MPU02_IRQ_ACOKBR] = {
179 .reg_offset = 0,
180 .mask = S2MPS11_IRQ_ACOKBR_MASK,
181 },
182 [S2MPU02_IRQ_PWRON1S] = {
183 .reg_offset = 0,
184 .mask = S2MPS11_IRQ_PWRON1S_MASK,
185 },
186 [S2MPU02_IRQ_MRB] = {
187 .reg_offset = 0,
188 .mask = S2MPS11_IRQ_MRB_MASK,
189 },
190 [S2MPU02_IRQ_RTC60S] = {
191 .reg_offset = 1,
192 .mask = S2MPS11_IRQ_RTC60S_MASK,
193 },
194 [S2MPU02_IRQ_RTCA1] = {
195 .reg_offset = 1,
196 .mask = S2MPS11_IRQ_RTCA1_MASK,
197 },
198 [S2MPU02_IRQ_RTCA0] = {
199 .reg_offset = 1,
200 .mask = S2MPS11_IRQ_RTCA0_MASK,
201 },
202 [S2MPU02_IRQ_SMPL] = {
203 .reg_offset = 1,
204 .mask = S2MPS11_IRQ_SMPL_MASK,
205 },
206 [S2MPU02_IRQ_RTC1S] = {
207 .reg_offset = 1,
208 .mask = S2MPS11_IRQ_RTC1S_MASK,
209 },
210 [S2MPU02_IRQ_WTSR] = {
211 .reg_offset = 1,
212 .mask = S2MPS11_IRQ_WTSR_MASK,
213 },
214 [S2MPU02_IRQ_INT120C] = {
215 .reg_offset = 2,
216 .mask = S2MPS11_IRQ_INT120C_MASK,
217 },
218 [S2MPU02_IRQ_INT140C] = {
219 .reg_offset = 2,
220 .mask = S2MPS11_IRQ_INT140C_MASK,
221 },
222 [S2MPU02_IRQ_TSD] = {
223 .reg_offset = 2,
224 .mask = S2MPS14_IRQ_TSD_MASK,
225 },
226};
227
228static const struct regmap_irq s5m8767_irqs[] = {
229 [S5M8767_IRQ_PWRR] = {
230 .reg_offset = 0,
231 .mask = S5M8767_IRQ_PWRR_MASK,
232 },
233 [S5M8767_IRQ_PWRF] = {
234 .reg_offset = 0,
235 .mask = S5M8767_IRQ_PWRF_MASK,
236 },
237 [S5M8767_IRQ_PWR1S] = {
238 .reg_offset = 0,
239 .mask = S5M8767_IRQ_PWR1S_MASK,
240 },
241 [S5M8767_IRQ_JIGR] = {
242 .reg_offset = 0,
243 .mask = S5M8767_IRQ_JIGR_MASK,
244 },
245 [S5M8767_IRQ_JIGF] = {
246 .reg_offset = 0,
247 .mask = S5M8767_IRQ_JIGF_MASK,
248 },
249 [S5M8767_IRQ_LOWBAT2] = {
250 .reg_offset = 0,
251 .mask = S5M8767_IRQ_LOWBAT2_MASK,
252 },
253 [S5M8767_IRQ_LOWBAT1] = {
254 .reg_offset = 0,
255 .mask = S5M8767_IRQ_LOWBAT1_MASK,
256 },
257 [S5M8767_IRQ_MRB] = {
258 .reg_offset = 1,
259 .mask = S5M8767_IRQ_MRB_MASK,
260 },
261 [S5M8767_IRQ_DVSOK2] = {
262 .reg_offset = 1,
263 .mask = S5M8767_IRQ_DVSOK2_MASK,
264 },
265 [S5M8767_IRQ_DVSOK3] = {
266 .reg_offset = 1,
267 .mask = S5M8767_IRQ_DVSOK3_MASK,
268 },
269 [S5M8767_IRQ_DVSOK4] = {
270 .reg_offset = 1,
271 .mask = S5M8767_IRQ_DVSOK4_MASK,
272 },
273 [S5M8767_IRQ_RTC60S] = {
274 .reg_offset = 2,
275 .mask = S5M8767_IRQ_RTC60S_MASK,
276 },
277 [S5M8767_IRQ_RTCA1] = {
278 .reg_offset = 2,
279 .mask = S5M8767_IRQ_RTCA1_MASK,
280 },
281 [S5M8767_IRQ_RTCA2] = {
282 .reg_offset = 2,
283 .mask = S5M8767_IRQ_RTCA2_MASK,
284 },
285 [S5M8767_IRQ_SMPL] = {
286 .reg_offset = 2,
287 .mask = S5M8767_IRQ_SMPL_MASK,
288 },
289 [S5M8767_IRQ_RTC1S] = {
290 .reg_offset = 2,
291 .mask = S5M8767_IRQ_RTC1S_MASK,
292 },
293 [S5M8767_IRQ_WTSR] = {
294 .reg_offset = 2,
295 .mask = S5M8767_IRQ_WTSR_MASK,
296 },
297};
298
299static const struct regmap_irq_chip s2mps11_irq_chip = {
300 .name = "s2mps11",
301 .irqs = s2mps11_irqs,
302 .num_irqs = ARRAY_SIZE(s2mps11_irqs),
303 .num_regs = 3,
304 .status_base = S2MPS11_REG_INT1,
305 .mask_base = S2MPS11_REG_INT1M,
306 .ack_base = S2MPS11_REG_INT1,
307};
308
309#define S2MPS1X_IRQ_CHIP_COMMON_DATA \
310 .irqs = s2mps14_irqs, \
311 .num_irqs = ARRAY_SIZE(s2mps14_irqs), \
312 .num_regs = 3, \
313 .status_base = S2MPS14_REG_INT1, \
314 .mask_base = S2MPS14_REG_INT1M, \
315 .ack_base = S2MPS14_REG_INT1 \
316
317static const struct regmap_irq_chip s2mps13_irq_chip = {
318 .name = "s2mps13",
319 S2MPS1X_IRQ_CHIP_COMMON_DATA,
320};
321
322static const struct regmap_irq_chip s2mps14_irq_chip = {
323 .name = "s2mps14",
324 S2MPS1X_IRQ_CHIP_COMMON_DATA,
325};
326
327static const struct regmap_irq_chip s2mps15_irq_chip = {
328 .name = "s2mps15",
329 S2MPS1X_IRQ_CHIP_COMMON_DATA,
330};
331
332static const struct regmap_irq_chip s2mpu02_irq_chip = {
333 .name = "s2mpu02",
334 .irqs = s2mpu02_irqs,
335 .num_irqs = ARRAY_SIZE(s2mpu02_irqs),
336 .num_regs = 3,
337 .status_base = S2MPU02_REG_INT1,
338 .mask_base = S2MPU02_REG_INT1M,
339 .ack_base = S2MPU02_REG_INT1,
340};
341
342static const struct regmap_irq_chip s5m8767_irq_chip = {
343 .name = "s5m8767",
344 .irqs = s5m8767_irqs,
345 .num_irqs = ARRAY_SIZE(s5m8767_irqs),
346 .num_regs = 3,
347 .status_base = S5M8767_REG_INT1,
348 .mask_base = S5M8767_REG_INT1M,
349 .ack_base = S5M8767_REG_INT1,
350};
351
352int sec_irq_init(struct sec_pmic_dev *sec_pmic)
353{
354 int ret = 0;
355 int type = sec_pmic->device_type;
356 const struct regmap_irq_chip *sec_irq_chip;
357
358 if (!sec_pmic->irq) {
359 dev_warn(sec_pmic->dev,
360 "No interrupt specified, no interrupts\n");
361 return 0;
362 }
363
364 switch (type) {
365 case S5M8767X:
366 sec_irq_chip = &s5m8767_irq_chip;
367 break;
368 case S2MPA01:
369 sec_irq_chip = &s2mps14_irq_chip;
370 break;
371 case S2MPS11X:
372 sec_irq_chip = &s2mps11_irq_chip;
373 break;
374 case S2MPS13X:
375 sec_irq_chip = &s2mps13_irq_chip;
376 break;
377 case S2MPS14X:
378 sec_irq_chip = &s2mps14_irq_chip;
379 break;
380 case S2MPS15X:
381 sec_irq_chip = &s2mps15_irq_chip;
382 break;
383 case S2MPU02:
384 sec_irq_chip = &s2mpu02_irq_chip;
385 break;
386 default:
387 dev_err(sec_pmic->dev, "Unknown device type %lu\n",
388 sec_pmic->device_type);
389 return -EINVAL;
390 }
391
392 ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
393 sec_pmic->irq, IRQF_ONESHOT,
394 0, sec_irq_chip, &sec_pmic->irq_data);
395 if (ret != 0) {
396 dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
397 return ret;
398 }
399
400 /*
401 * The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
402 * so the interrupt number must be consistent.
403 */
404 BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
405
406 return 0;
407}
408EXPORT_SYMBOL_GPL(sec_irq_init);
409
410MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
411MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
412MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
413MODULE_DESCRIPTION("Interrupt support for the S5M MFD");
414MODULE_LICENSE("GPL");
1/*
2 * sec-irq.c
3 *
4 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/regmap.h>
18
19#include <linux/mfd/samsung/core.h>
20#include <linux/mfd/samsung/irq.h>
21#include <linux/mfd/samsung/s2mps11.h>
22#include <linux/mfd/samsung/s2mps14.h>
23#include <linux/mfd/samsung/s5m8763.h>
24#include <linux/mfd/samsung/s5m8767.h>
25
26static const struct regmap_irq s2mps11_irqs[] = {
27 [S2MPS11_IRQ_PWRONF] = {
28 .reg_offset = 0,
29 .mask = S2MPS11_IRQ_PWRONF_MASK,
30 },
31 [S2MPS11_IRQ_PWRONR] = {
32 .reg_offset = 0,
33 .mask = S2MPS11_IRQ_PWRONR_MASK,
34 },
35 [S2MPS11_IRQ_JIGONBF] = {
36 .reg_offset = 0,
37 .mask = S2MPS11_IRQ_JIGONBF_MASK,
38 },
39 [S2MPS11_IRQ_JIGONBR] = {
40 .reg_offset = 0,
41 .mask = S2MPS11_IRQ_JIGONBR_MASK,
42 },
43 [S2MPS11_IRQ_ACOKBF] = {
44 .reg_offset = 0,
45 .mask = S2MPS11_IRQ_ACOKBF_MASK,
46 },
47 [S2MPS11_IRQ_ACOKBR] = {
48 .reg_offset = 0,
49 .mask = S2MPS11_IRQ_ACOKBR_MASK,
50 },
51 [S2MPS11_IRQ_PWRON1S] = {
52 .reg_offset = 0,
53 .mask = S2MPS11_IRQ_PWRON1S_MASK,
54 },
55 [S2MPS11_IRQ_MRB] = {
56 .reg_offset = 0,
57 .mask = S2MPS11_IRQ_MRB_MASK,
58 },
59 [S2MPS11_IRQ_RTC60S] = {
60 .reg_offset = 1,
61 .mask = S2MPS11_IRQ_RTC60S_MASK,
62 },
63 [S2MPS11_IRQ_RTCA0] = {
64 .reg_offset = 1,
65 .mask = S2MPS11_IRQ_RTCA0_MASK,
66 },
67 [S2MPS11_IRQ_RTCA1] = {
68 .reg_offset = 1,
69 .mask = S2MPS11_IRQ_RTCA1_MASK,
70 },
71 [S2MPS11_IRQ_SMPL] = {
72 .reg_offset = 1,
73 .mask = S2MPS11_IRQ_SMPL_MASK,
74 },
75 [S2MPS11_IRQ_RTC1S] = {
76 .reg_offset = 1,
77 .mask = S2MPS11_IRQ_RTC1S_MASK,
78 },
79 [S2MPS11_IRQ_WTSR] = {
80 .reg_offset = 1,
81 .mask = S2MPS11_IRQ_WTSR_MASK,
82 },
83 [S2MPS11_IRQ_INT120C] = {
84 .reg_offset = 2,
85 .mask = S2MPS11_IRQ_INT120C_MASK,
86 },
87 [S2MPS11_IRQ_INT140C] = {
88 .reg_offset = 2,
89 .mask = S2MPS11_IRQ_INT140C_MASK,
90 },
91};
92
93static const struct regmap_irq s2mps14_irqs[] = {
94 [S2MPS14_IRQ_PWRONF] = {
95 .reg_offset = 0,
96 .mask = S2MPS11_IRQ_PWRONF_MASK,
97 },
98 [S2MPS14_IRQ_PWRONR] = {
99 .reg_offset = 0,
100 .mask = S2MPS11_IRQ_PWRONR_MASK,
101 },
102 [S2MPS14_IRQ_JIGONBF] = {
103 .reg_offset = 0,
104 .mask = S2MPS11_IRQ_JIGONBF_MASK,
105 },
106 [S2MPS14_IRQ_JIGONBR] = {
107 .reg_offset = 0,
108 .mask = S2MPS11_IRQ_JIGONBR_MASK,
109 },
110 [S2MPS14_IRQ_ACOKBF] = {
111 .reg_offset = 0,
112 .mask = S2MPS11_IRQ_ACOKBF_MASK,
113 },
114 [S2MPS14_IRQ_ACOKBR] = {
115 .reg_offset = 0,
116 .mask = S2MPS11_IRQ_ACOKBR_MASK,
117 },
118 [S2MPS14_IRQ_PWRON1S] = {
119 .reg_offset = 0,
120 .mask = S2MPS11_IRQ_PWRON1S_MASK,
121 },
122 [S2MPS14_IRQ_MRB] = {
123 .reg_offset = 0,
124 .mask = S2MPS11_IRQ_MRB_MASK,
125 },
126 [S2MPS14_IRQ_RTC60S] = {
127 .reg_offset = 1,
128 .mask = S2MPS11_IRQ_RTC60S_MASK,
129 },
130 [S2MPS14_IRQ_RTCA1] = {
131 .reg_offset = 1,
132 .mask = S2MPS11_IRQ_RTCA1_MASK,
133 },
134 [S2MPS14_IRQ_RTCA0] = {
135 .reg_offset = 1,
136 .mask = S2MPS11_IRQ_RTCA0_MASK,
137 },
138 [S2MPS14_IRQ_SMPL] = {
139 .reg_offset = 1,
140 .mask = S2MPS11_IRQ_SMPL_MASK,
141 },
142 [S2MPS14_IRQ_RTC1S] = {
143 .reg_offset = 1,
144 .mask = S2MPS11_IRQ_RTC1S_MASK,
145 },
146 [S2MPS14_IRQ_WTSR] = {
147 .reg_offset = 1,
148 .mask = S2MPS11_IRQ_WTSR_MASK,
149 },
150 [S2MPS14_IRQ_INT120C] = {
151 .reg_offset = 2,
152 .mask = S2MPS11_IRQ_INT120C_MASK,
153 },
154 [S2MPS14_IRQ_INT140C] = {
155 .reg_offset = 2,
156 .mask = S2MPS11_IRQ_INT140C_MASK,
157 },
158 [S2MPS14_IRQ_TSD] = {
159 .reg_offset = 2,
160 .mask = S2MPS14_IRQ_TSD_MASK,
161 },
162};
163
164static const struct regmap_irq s5m8767_irqs[] = {
165 [S5M8767_IRQ_PWRR] = {
166 .reg_offset = 0,
167 .mask = S5M8767_IRQ_PWRR_MASK,
168 },
169 [S5M8767_IRQ_PWRF] = {
170 .reg_offset = 0,
171 .mask = S5M8767_IRQ_PWRF_MASK,
172 },
173 [S5M8767_IRQ_PWR1S] = {
174 .reg_offset = 0,
175 .mask = S5M8767_IRQ_PWR1S_MASK,
176 },
177 [S5M8767_IRQ_JIGR] = {
178 .reg_offset = 0,
179 .mask = S5M8767_IRQ_JIGR_MASK,
180 },
181 [S5M8767_IRQ_JIGF] = {
182 .reg_offset = 0,
183 .mask = S5M8767_IRQ_JIGF_MASK,
184 },
185 [S5M8767_IRQ_LOWBAT2] = {
186 .reg_offset = 0,
187 .mask = S5M8767_IRQ_LOWBAT2_MASK,
188 },
189 [S5M8767_IRQ_LOWBAT1] = {
190 .reg_offset = 0,
191 .mask = S5M8767_IRQ_LOWBAT1_MASK,
192 },
193 [S5M8767_IRQ_MRB] = {
194 .reg_offset = 1,
195 .mask = S5M8767_IRQ_MRB_MASK,
196 },
197 [S5M8767_IRQ_DVSOK2] = {
198 .reg_offset = 1,
199 .mask = S5M8767_IRQ_DVSOK2_MASK,
200 },
201 [S5M8767_IRQ_DVSOK3] = {
202 .reg_offset = 1,
203 .mask = S5M8767_IRQ_DVSOK3_MASK,
204 },
205 [S5M8767_IRQ_DVSOK4] = {
206 .reg_offset = 1,
207 .mask = S5M8767_IRQ_DVSOK4_MASK,
208 },
209 [S5M8767_IRQ_RTC60S] = {
210 .reg_offset = 2,
211 .mask = S5M8767_IRQ_RTC60S_MASK,
212 },
213 [S5M8767_IRQ_RTCA1] = {
214 .reg_offset = 2,
215 .mask = S5M8767_IRQ_RTCA1_MASK,
216 },
217 [S5M8767_IRQ_RTCA2] = {
218 .reg_offset = 2,
219 .mask = S5M8767_IRQ_RTCA2_MASK,
220 },
221 [S5M8767_IRQ_SMPL] = {
222 .reg_offset = 2,
223 .mask = S5M8767_IRQ_SMPL_MASK,
224 },
225 [S5M8767_IRQ_RTC1S] = {
226 .reg_offset = 2,
227 .mask = S5M8767_IRQ_RTC1S_MASK,
228 },
229 [S5M8767_IRQ_WTSR] = {
230 .reg_offset = 2,
231 .mask = S5M8767_IRQ_WTSR_MASK,
232 },
233};
234
235static const struct regmap_irq s5m8763_irqs[] = {
236 [S5M8763_IRQ_DCINF] = {
237 .reg_offset = 0,
238 .mask = S5M8763_IRQ_DCINF_MASK,
239 },
240 [S5M8763_IRQ_DCINR] = {
241 .reg_offset = 0,
242 .mask = S5M8763_IRQ_DCINR_MASK,
243 },
244 [S5M8763_IRQ_JIGF] = {
245 .reg_offset = 0,
246 .mask = S5M8763_IRQ_JIGF_MASK,
247 },
248 [S5M8763_IRQ_JIGR] = {
249 .reg_offset = 0,
250 .mask = S5M8763_IRQ_JIGR_MASK,
251 },
252 [S5M8763_IRQ_PWRONF] = {
253 .reg_offset = 0,
254 .mask = S5M8763_IRQ_PWRONF_MASK,
255 },
256 [S5M8763_IRQ_PWRONR] = {
257 .reg_offset = 0,
258 .mask = S5M8763_IRQ_PWRONR_MASK,
259 },
260 [S5M8763_IRQ_WTSREVNT] = {
261 .reg_offset = 1,
262 .mask = S5M8763_IRQ_WTSREVNT_MASK,
263 },
264 [S5M8763_IRQ_SMPLEVNT] = {
265 .reg_offset = 1,
266 .mask = S5M8763_IRQ_SMPLEVNT_MASK,
267 },
268 [S5M8763_IRQ_ALARM1] = {
269 .reg_offset = 1,
270 .mask = S5M8763_IRQ_ALARM1_MASK,
271 },
272 [S5M8763_IRQ_ALARM0] = {
273 .reg_offset = 1,
274 .mask = S5M8763_IRQ_ALARM0_MASK,
275 },
276 [S5M8763_IRQ_ONKEY1S] = {
277 .reg_offset = 2,
278 .mask = S5M8763_IRQ_ONKEY1S_MASK,
279 },
280 [S5M8763_IRQ_TOPOFFR] = {
281 .reg_offset = 2,
282 .mask = S5M8763_IRQ_TOPOFFR_MASK,
283 },
284 [S5M8763_IRQ_DCINOVPR] = {
285 .reg_offset = 2,
286 .mask = S5M8763_IRQ_DCINOVPR_MASK,
287 },
288 [S5M8763_IRQ_CHGRSTF] = {
289 .reg_offset = 2,
290 .mask = S5M8763_IRQ_CHGRSTF_MASK,
291 },
292 [S5M8763_IRQ_DONER] = {
293 .reg_offset = 2,
294 .mask = S5M8763_IRQ_DONER_MASK,
295 },
296 [S5M8763_IRQ_CHGFAULT] = {
297 .reg_offset = 2,
298 .mask = S5M8763_IRQ_CHGFAULT_MASK,
299 },
300 [S5M8763_IRQ_LOBAT1] = {
301 .reg_offset = 3,
302 .mask = S5M8763_IRQ_LOBAT1_MASK,
303 },
304 [S5M8763_IRQ_LOBAT2] = {
305 .reg_offset = 3,
306 .mask = S5M8763_IRQ_LOBAT2_MASK,
307 },
308};
309
310static const struct regmap_irq_chip s2mps11_irq_chip = {
311 .name = "s2mps11",
312 .irqs = s2mps11_irqs,
313 .num_irqs = ARRAY_SIZE(s2mps11_irqs),
314 .num_regs = 3,
315 .status_base = S2MPS11_REG_INT1,
316 .mask_base = S2MPS11_REG_INT1M,
317 .ack_base = S2MPS11_REG_INT1,
318};
319
320static const struct regmap_irq_chip s2mps14_irq_chip = {
321 .name = "s2mps14",
322 .irqs = s2mps14_irqs,
323 .num_irqs = ARRAY_SIZE(s2mps14_irqs),
324 .num_regs = 3,
325 .status_base = S2MPS14_REG_INT1,
326 .mask_base = S2MPS14_REG_INT1M,
327 .ack_base = S2MPS14_REG_INT1,
328};
329
330static const struct regmap_irq_chip s5m8767_irq_chip = {
331 .name = "s5m8767",
332 .irqs = s5m8767_irqs,
333 .num_irqs = ARRAY_SIZE(s5m8767_irqs),
334 .num_regs = 3,
335 .status_base = S5M8767_REG_INT1,
336 .mask_base = S5M8767_REG_INT1M,
337 .ack_base = S5M8767_REG_INT1,
338};
339
340static const struct regmap_irq_chip s5m8763_irq_chip = {
341 .name = "s5m8763",
342 .irqs = s5m8763_irqs,
343 .num_irqs = ARRAY_SIZE(s5m8763_irqs),
344 .num_regs = 4,
345 .status_base = S5M8763_REG_IRQ1,
346 .mask_base = S5M8763_REG_IRQM1,
347 .ack_base = S5M8763_REG_IRQ1,
348};
349
350int sec_irq_init(struct sec_pmic_dev *sec_pmic)
351{
352 int ret = 0;
353 int type = sec_pmic->device_type;
354
355 if (!sec_pmic->irq) {
356 dev_warn(sec_pmic->dev,
357 "No interrupt specified, no interrupts\n");
358 sec_pmic->irq_base = 0;
359 return 0;
360 }
361
362 switch (type) {
363 case S5M8763X:
364 ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
365 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
366 sec_pmic->irq_base, &s5m8763_irq_chip,
367 &sec_pmic->irq_data);
368 break;
369 case S5M8767X:
370 ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
371 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
372 sec_pmic->irq_base, &s5m8767_irq_chip,
373 &sec_pmic->irq_data);
374 break;
375 case S2MPS11X:
376 ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
377 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
378 sec_pmic->irq_base, &s2mps11_irq_chip,
379 &sec_pmic->irq_data);
380 break;
381 case S2MPS14X:
382 ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
383 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
384 sec_pmic->irq_base, &s2mps14_irq_chip,
385 &sec_pmic->irq_data);
386 break;
387 default:
388 dev_err(sec_pmic->dev, "Unknown device type %d\n",
389 sec_pmic->device_type);
390 return -EINVAL;
391 }
392
393 if (ret != 0) {
394 dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
395 return ret;
396 }
397
398 return 0;
399}
400
401void sec_irq_exit(struct sec_pmic_dev *sec_pmic)
402{
403 regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data);
404}