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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/delay.h>
10#include <linux/hwspinlock.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/platform_device.h>
22#include <linux/syscore_ops.h>
23
24#include <dt-bindings/interrupt-controller/arm-gic.h>
25
26#define IRQS_PER_BANK 32
27
28#define HWSPNLCK_TIMEOUT 1000 /* usec */
29
30struct stm32_exti_bank {
31 u32 imr_ofst;
32 u32 emr_ofst;
33 u32 rtsr_ofst;
34 u32 ftsr_ofst;
35 u32 swier_ofst;
36 u32 rpr_ofst;
37 u32 fpr_ofst;
38 u32 trg_ofst;
39};
40
41#define UNDEF_REG ~0
42
43struct stm32_exti_drv_data {
44 const struct stm32_exti_bank **exti_banks;
45 const u8 *desc_irqs;
46 u32 bank_nr;
47};
48
49struct stm32_exti_chip_data {
50 struct stm32_exti_host_data *host_data;
51 const struct stm32_exti_bank *reg_bank;
52 struct raw_spinlock rlock;
53 u32 wake_active;
54 u32 mask_cache;
55 u32 rtsr_cache;
56 u32 ftsr_cache;
57};
58
59struct stm32_exti_host_data {
60 void __iomem *base;
61 struct stm32_exti_chip_data *chips_data;
62 const struct stm32_exti_drv_data *drv_data;
63 struct hwspinlock *hwlock;
64};
65
66static struct stm32_exti_host_data *stm32_host_data;
67
68static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
69 .imr_ofst = 0x00,
70 .emr_ofst = 0x04,
71 .rtsr_ofst = 0x08,
72 .ftsr_ofst = 0x0C,
73 .swier_ofst = 0x10,
74 .rpr_ofst = 0x14,
75 .fpr_ofst = UNDEF_REG,
76 .trg_ofst = UNDEF_REG,
77};
78
79static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
80 &stm32f4xx_exti_b1,
81};
82
83static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
84 .exti_banks = stm32f4xx_exti_banks,
85 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
86};
87
88static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
89 .imr_ofst = 0x80,
90 .emr_ofst = 0x84,
91 .rtsr_ofst = 0x00,
92 .ftsr_ofst = 0x04,
93 .swier_ofst = 0x08,
94 .rpr_ofst = 0x88,
95 .fpr_ofst = UNDEF_REG,
96 .trg_ofst = UNDEF_REG,
97};
98
99static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
100 .imr_ofst = 0x90,
101 .emr_ofst = 0x94,
102 .rtsr_ofst = 0x20,
103 .ftsr_ofst = 0x24,
104 .swier_ofst = 0x28,
105 .rpr_ofst = 0x98,
106 .fpr_ofst = UNDEF_REG,
107 .trg_ofst = UNDEF_REG,
108};
109
110static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
111 .imr_ofst = 0xA0,
112 .emr_ofst = 0xA4,
113 .rtsr_ofst = 0x40,
114 .ftsr_ofst = 0x44,
115 .swier_ofst = 0x48,
116 .rpr_ofst = 0xA8,
117 .fpr_ofst = UNDEF_REG,
118 .trg_ofst = UNDEF_REG,
119};
120
121static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
122 &stm32h7xx_exti_b1,
123 &stm32h7xx_exti_b2,
124 &stm32h7xx_exti_b3,
125};
126
127static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
128 .exti_banks = stm32h7xx_exti_banks,
129 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
130};
131
132static const struct stm32_exti_bank stm32mp1_exti_b1 = {
133 .imr_ofst = 0x80,
134 .emr_ofst = UNDEF_REG,
135 .rtsr_ofst = 0x00,
136 .ftsr_ofst = 0x04,
137 .swier_ofst = 0x08,
138 .rpr_ofst = 0x0C,
139 .fpr_ofst = 0x10,
140 .trg_ofst = 0x3EC,
141};
142
143static const struct stm32_exti_bank stm32mp1_exti_b2 = {
144 .imr_ofst = 0x90,
145 .emr_ofst = UNDEF_REG,
146 .rtsr_ofst = 0x20,
147 .ftsr_ofst = 0x24,
148 .swier_ofst = 0x28,
149 .rpr_ofst = 0x2C,
150 .fpr_ofst = 0x30,
151 .trg_ofst = 0x3E8,
152};
153
154static const struct stm32_exti_bank stm32mp1_exti_b3 = {
155 .imr_ofst = 0xA0,
156 .emr_ofst = UNDEF_REG,
157 .rtsr_ofst = 0x40,
158 .ftsr_ofst = 0x44,
159 .swier_ofst = 0x48,
160 .rpr_ofst = 0x4C,
161 .fpr_ofst = 0x50,
162 .trg_ofst = 0x3E4,
163};
164
165static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
166 &stm32mp1_exti_b1,
167 &stm32mp1_exti_b2,
168 &stm32mp1_exti_b3,
169};
170
171static struct irq_chip stm32_exti_h_chip;
172static struct irq_chip stm32_exti_h_chip_direct;
173
174#define EXTI_INVALID_IRQ U8_MAX
175#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
176
177/*
178 * Use some intentionally tricky logic here to initialize the whole array to
179 * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate
180 * that we "know" that there are overrides in this structure, and we'll need to
181 * disable that warning from W=1 builds.
182 */
183__diag_push();
184__diag_ignore_all("-Woverride-init",
185 "logic to initialize all and then override some is OK");
186
187static const u8 stm32mp1_desc_irq[] = {
188 /* default value */
189 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
190
191 [0] = 6,
192 [1] = 7,
193 [2] = 8,
194 [3] = 9,
195 [4] = 10,
196 [5] = 23,
197 [6] = 64,
198 [7] = 65,
199 [8] = 66,
200 [9] = 67,
201 [10] = 40,
202 [11] = 42,
203 [12] = 76,
204 [13] = 77,
205 [14] = 121,
206 [15] = 127,
207 [16] = 1,
208 [19] = 3,
209 [21] = 31,
210 [22] = 33,
211 [23] = 72,
212 [24] = 95,
213 [25] = 107,
214 [26] = 37,
215 [27] = 38,
216 [28] = 39,
217 [29] = 71,
218 [30] = 52,
219 [31] = 53,
220 [32] = 82,
221 [33] = 83,
222 [46] = 151,
223 [47] = 93,
224 [48] = 138,
225 [50] = 139,
226 [52] = 140,
227 [53] = 141,
228 [54] = 135,
229 [61] = 100,
230 [65] = 144,
231 [68] = 143,
232 [70] = 62,
233 [73] = 129,
234};
235
236static const u8 stm32mp13_desc_irq[] = {
237 /* default value */
238 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
239
240 [0] = 6,
241 [1] = 7,
242 [2] = 8,
243 [3] = 9,
244 [4] = 10,
245 [5] = 24,
246 [6] = 65,
247 [7] = 66,
248 [8] = 67,
249 [9] = 68,
250 [10] = 41,
251 [11] = 43,
252 [12] = 77,
253 [13] = 78,
254 [14] = 106,
255 [15] = 109,
256 [16] = 1,
257 [19] = 3,
258 [21] = 32,
259 [22] = 34,
260 [23] = 73,
261 [24] = 93,
262 [25] = 114,
263 [26] = 38,
264 [27] = 39,
265 [28] = 40,
266 [29] = 72,
267 [30] = 53,
268 [31] = 54,
269 [32] = 83,
270 [33] = 84,
271 [44] = 96,
272 [47] = 92,
273 [48] = 116,
274 [50] = 117,
275 [52] = 118,
276 [53] = 119,
277 [68] = 63,
278 [70] = 98,
279};
280
281__diag_pop();
282
283static const struct stm32_exti_drv_data stm32mp1_drv_data = {
284 .exti_banks = stm32mp1_exti_banks,
285 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
286 .desc_irqs = stm32mp1_desc_irq,
287};
288
289static const struct stm32_exti_drv_data stm32mp13_drv_data = {
290 .exti_banks = stm32mp1_exti_banks,
291 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
292 .desc_irqs = stm32mp13_desc_irq,
293};
294
295static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
296{
297 struct stm32_exti_chip_data *chip_data = gc->private;
298 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
299 unsigned long pending;
300
301 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
302 if (stm32_bank->fpr_ofst != UNDEF_REG)
303 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
304
305 return pending;
306}
307
308static void stm32_irq_handler(struct irq_desc *desc)
309{
310 struct irq_domain *domain = irq_desc_get_handler_data(desc);
311 struct irq_chip *chip = irq_desc_get_chip(desc);
312 unsigned int nbanks = domain->gc->num_chips;
313 struct irq_chip_generic *gc;
314 unsigned long pending;
315 int n, i, irq_base = 0;
316
317 chained_irq_enter(chip, desc);
318
319 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
320 gc = irq_get_domain_generic_chip(domain, irq_base);
321
322 while ((pending = stm32_exti_pending(gc))) {
323 for_each_set_bit(n, &pending, IRQS_PER_BANK)
324 generic_handle_domain_irq(domain, irq_base + n);
325 }
326 }
327
328 chained_irq_exit(chip, desc);
329}
330
331static int stm32_exti_set_type(struct irq_data *d,
332 unsigned int type, u32 *rtsr, u32 *ftsr)
333{
334 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
335
336 switch (type) {
337 case IRQ_TYPE_EDGE_RISING:
338 *rtsr |= mask;
339 *ftsr &= ~mask;
340 break;
341 case IRQ_TYPE_EDGE_FALLING:
342 *rtsr &= ~mask;
343 *ftsr |= mask;
344 break;
345 case IRQ_TYPE_EDGE_BOTH:
346 *rtsr |= mask;
347 *ftsr |= mask;
348 break;
349 default:
350 return -EINVAL;
351 }
352
353 return 0;
354}
355
356static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
357{
358 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
359 struct stm32_exti_chip_data *chip_data = gc->private;
360 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
361 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
362 u32 rtsr, ftsr;
363 int err;
364
365 irq_gc_lock(gc);
366
367 if (hwlock) {
368 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
369 if (err) {
370 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
371 goto unlock;
372 }
373 }
374
375 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
376 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
377
378 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
379 if (err)
380 goto unspinlock;
381
382 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
383 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
384
385unspinlock:
386 if (hwlock)
387 hwspin_unlock_in_atomic(hwlock);
388unlock:
389 irq_gc_unlock(gc);
390
391 return err;
392}
393
394static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
395 u32 wake_active)
396{
397 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
398 void __iomem *base = chip_data->host_data->base;
399
400 /* save rtsr, ftsr registers */
401 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
402 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
403
404 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
405}
406
407static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
408 u32 mask_cache)
409{
410 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
411 void __iomem *base = chip_data->host_data->base;
412
413 /* restore rtsr, ftsr, registers */
414 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
415 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
416
417 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
418}
419
420static void stm32_irq_suspend(struct irq_chip_generic *gc)
421{
422 struct stm32_exti_chip_data *chip_data = gc->private;
423
424 irq_gc_lock(gc);
425 stm32_chip_suspend(chip_data, gc->wake_active);
426 irq_gc_unlock(gc);
427}
428
429static void stm32_irq_resume(struct irq_chip_generic *gc)
430{
431 struct stm32_exti_chip_data *chip_data = gc->private;
432
433 irq_gc_lock(gc);
434 stm32_chip_resume(chip_data, gc->mask_cache);
435 irq_gc_unlock(gc);
436}
437
438static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
439 unsigned int nr_irqs, void *data)
440{
441 struct irq_fwspec *fwspec = data;
442 irq_hw_number_t hwirq;
443
444 hwirq = fwspec->param[0];
445
446 irq_map_generic_chip(d, virq, hwirq);
447
448 return 0;
449}
450
451static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
452 unsigned int nr_irqs)
453{
454 struct irq_data *data = irq_domain_get_irq_data(d, virq);
455
456 irq_domain_reset_irq_data(data);
457}
458
459static const struct irq_domain_ops irq_exti_domain_ops = {
460 .map = irq_map_generic_chip,
461 .alloc = stm32_exti_alloc,
462 .free = stm32_exti_free,
463 .xlate = irq_domain_xlate_twocell,
464};
465
466static void stm32_irq_ack(struct irq_data *d)
467{
468 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
469 struct stm32_exti_chip_data *chip_data = gc->private;
470 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
471
472 irq_gc_lock(gc);
473
474 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
475 if (stm32_bank->fpr_ofst != UNDEF_REG)
476 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
477
478 irq_gc_unlock(gc);
479}
480
481/* directly set the target bit without reading first. */
482static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
483{
484 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
485 void __iomem *base = chip_data->host_data->base;
486 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
487
488 writel_relaxed(val, base + reg);
489}
490
491static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
492{
493 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
494 void __iomem *base = chip_data->host_data->base;
495 u32 val;
496
497 val = readl_relaxed(base + reg);
498 val |= BIT(d->hwirq % IRQS_PER_BANK);
499 writel_relaxed(val, base + reg);
500
501 return val;
502}
503
504static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
505{
506 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
507 void __iomem *base = chip_data->host_data->base;
508 u32 val;
509
510 val = readl_relaxed(base + reg);
511 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
512 writel_relaxed(val, base + reg);
513
514 return val;
515}
516
517static void stm32_exti_h_eoi(struct irq_data *d)
518{
519 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
520 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
521
522 raw_spin_lock(&chip_data->rlock);
523
524 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
525 if (stm32_bank->fpr_ofst != UNDEF_REG)
526 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
527
528 raw_spin_unlock(&chip_data->rlock);
529
530 if (d->parent_data->chip)
531 irq_chip_eoi_parent(d);
532}
533
534static void stm32_exti_h_mask(struct irq_data *d)
535{
536 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
537 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
538
539 raw_spin_lock(&chip_data->rlock);
540 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
541 raw_spin_unlock(&chip_data->rlock);
542
543 if (d->parent_data->chip)
544 irq_chip_mask_parent(d);
545}
546
547static void stm32_exti_h_unmask(struct irq_data *d)
548{
549 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
550 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
551
552 raw_spin_lock(&chip_data->rlock);
553 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
554 raw_spin_unlock(&chip_data->rlock);
555
556 if (d->parent_data->chip)
557 irq_chip_unmask_parent(d);
558}
559
560static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
561{
562 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
563 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
564 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
565 void __iomem *base = chip_data->host_data->base;
566 u32 rtsr, ftsr;
567 int err;
568
569 raw_spin_lock(&chip_data->rlock);
570
571 if (hwlock) {
572 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
573 if (err) {
574 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
575 goto unlock;
576 }
577 }
578
579 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
580 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
581
582 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
583 if (err)
584 goto unspinlock;
585
586 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
587 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
588
589unspinlock:
590 if (hwlock)
591 hwspin_unlock_in_atomic(hwlock);
592unlock:
593 raw_spin_unlock(&chip_data->rlock);
594
595 return err;
596}
597
598static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
599{
600 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
601 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
602
603 raw_spin_lock(&chip_data->rlock);
604
605 if (on)
606 chip_data->wake_active |= mask;
607 else
608 chip_data->wake_active &= ~mask;
609
610 raw_spin_unlock(&chip_data->rlock);
611
612 return 0;
613}
614
615static int stm32_exti_h_set_affinity(struct irq_data *d,
616 const struct cpumask *dest, bool force)
617{
618 if (d->parent_data->chip)
619 return irq_chip_set_affinity_parent(d, dest, force);
620
621 return IRQ_SET_MASK_OK_DONE;
622}
623
624static int __maybe_unused stm32_exti_h_suspend(void)
625{
626 struct stm32_exti_chip_data *chip_data;
627 int i;
628
629 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
630 chip_data = &stm32_host_data->chips_data[i];
631 raw_spin_lock(&chip_data->rlock);
632 stm32_chip_suspend(chip_data, chip_data->wake_active);
633 raw_spin_unlock(&chip_data->rlock);
634 }
635
636 return 0;
637}
638
639static void __maybe_unused stm32_exti_h_resume(void)
640{
641 struct stm32_exti_chip_data *chip_data;
642 int i;
643
644 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
645 chip_data = &stm32_host_data->chips_data[i];
646 raw_spin_lock(&chip_data->rlock);
647 stm32_chip_resume(chip_data, chip_data->mask_cache);
648 raw_spin_unlock(&chip_data->rlock);
649 }
650}
651
652static struct syscore_ops stm32_exti_h_syscore_ops = {
653#ifdef CONFIG_PM_SLEEP
654 .suspend = stm32_exti_h_suspend,
655 .resume = stm32_exti_h_resume,
656#endif
657};
658
659static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
660{
661 stm32_host_data = host_data;
662 register_syscore_ops(&stm32_exti_h_syscore_ops);
663}
664
665static void stm32_exti_h_syscore_deinit(void)
666{
667 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
668}
669
670static int stm32_exti_h_retrigger(struct irq_data *d)
671{
672 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
673 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
674 void __iomem *base = chip_data->host_data->base;
675 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
676
677 writel_relaxed(mask, base + stm32_bank->swier_ofst);
678
679 return 0;
680}
681
682static struct irq_chip stm32_exti_h_chip = {
683 .name = "stm32-exti-h",
684 .irq_eoi = stm32_exti_h_eoi,
685 .irq_mask = stm32_exti_h_mask,
686 .irq_unmask = stm32_exti_h_unmask,
687 .irq_retrigger = stm32_exti_h_retrigger,
688 .irq_set_type = stm32_exti_h_set_type,
689 .irq_set_wake = stm32_exti_h_set_wake,
690 .flags = IRQCHIP_MASK_ON_SUSPEND,
691 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
692};
693
694static struct irq_chip stm32_exti_h_chip_direct = {
695 .name = "stm32-exti-h-direct",
696 .irq_eoi = irq_chip_eoi_parent,
697 .irq_ack = irq_chip_ack_parent,
698 .irq_mask = stm32_exti_h_mask,
699 .irq_unmask = stm32_exti_h_unmask,
700 .irq_retrigger = irq_chip_retrigger_hierarchy,
701 .irq_set_type = irq_chip_set_type_parent,
702 .irq_set_wake = stm32_exti_h_set_wake,
703 .flags = IRQCHIP_MASK_ON_SUSPEND,
704 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
705};
706
707static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
708 unsigned int virq,
709 unsigned int nr_irqs, void *data)
710{
711 struct stm32_exti_host_data *host_data = dm->host_data;
712 struct stm32_exti_chip_data *chip_data;
713 u8 desc_irq;
714 struct irq_fwspec *fwspec = data;
715 struct irq_fwspec p_fwspec;
716 irq_hw_number_t hwirq;
717 int bank;
718 u32 event_trg;
719 struct irq_chip *chip;
720
721 hwirq = fwspec->param[0];
722 if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
723 return -EINVAL;
724
725 bank = hwirq / IRQS_PER_BANK;
726 chip_data = &host_data->chips_data[bank];
727
728 event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
729 chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
730 &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
731
732 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
733
734 if (!host_data->drv_data->desc_irqs)
735 return -EINVAL;
736
737 desc_irq = host_data->drv_data->desc_irqs[hwirq];
738 if (desc_irq != EXTI_INVALID_IRQ) {
739 p_fwspec.fwnode = dm->parent->fwnode;
740 p_fwspec.param_count = 3;
741 p_fwspec.param[0] = GIC_SPI;
742 p_fwspec.param[1] = desc_irq;
743 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
744
745 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
746 }
747
748 return 0;
749}
750
751static struct
752stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
753 struct device_node *node)
754{
755 struct stm32_exti_host_data *host_data;
756
757 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
758 if (!host_data)
759 return NULL;
760
761 host_data->drv_data = dd;
762 host_data->chips_data = kcalloc(dd->bank_nr,
763 sizeof(struct stm32_exti_chip_data),
764 GFP_KERNEL);
765 if (!host_data->chips_data)
766 goto free_host_data;
767
768 host_data->base = of_iomap(node, 0);
769 if (!host_data->base) {
770 pr_err("%pOF: Unable to map registers\n", node);
771 goto free_chips_data;
772 }
773
774 stm32_host_data = host_data;
775
776 return host_data;
777
778free_chips_data:
779 kfree(host_data->chips_data);
780free_host_data:
781 kfree(host_data);
782
783 return NULL;
784}
785
786static struct
787stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
788 u32 bank_idx,
789 struct device_node *node)
790{
791 const struct stm32_exti_bank *stm32_bank;
792 struct stm32_exti_chip_data *chip_data;
793 void __iomem *base = h_data->base;
794
795 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
796 chip_data = &h_data->chips_data[bank_idx];
797 chip_data->host_data = h_data;
798 chip_data->reg_bank = stm32_bank;
799
800 raw_spin_lock_init(&chip_data->rlock);
801
802 /*
803 * This IP has no reset, so after hot reboot we should
804 * clear registers to avoid residue
805 */
806 writel_relaxed(0, base + stm32_bank->imr_ofst);
807 if (stm32_bank->emr_ofst != UNDEF_REG)
808 writel_relaxed(0, base + stm32_bank->emr_ofst);
809
810 pr_info("%pOF: bank%d\n", node, bank_idx);
811
812 return chip_data;
813}
814
815static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
816 struct device_node *node)
817{
818 struct stm32_exti_host_data *host_data;
819 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
820 int nr_irqs, ret, i;
821 struct irq_chip_generic *gc;
822 struct irq_domain *domain;
823
824 host_data = stm32_exti_host_init(drv_data, node);
825 if (!host_data)
826 return -ENOMEM;
827
828 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
829 &irq_exti_domain_ops, NULL);
830 if (!domain) {
831 pr_err("%pOFn: Could not register interrupt domain.\n",
832 node);
833 ret = -ENOMEM;
834 goto out_unmap;
835 }
836
837 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
838 handle_edge_irq, clr, 0, 0);
839 if (ret) {
840 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
841 node);
842 goto out_free_domain;
843 }
844
845 for (i = 0; i < drv_data->bank_nr; i++) {
846 const struct stm32_exti_bank *stm32_bank;
847 struct stm32_exti_chip_data *chip_data;
848
849 stm32_bank = drv_data->exti_banks[i];
850 chip_data = stm32_exti_chip_init(host_data, i, node);
851
852 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
853
854 gc->reg_base = host_data->base;
855 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
856 gc->chip_types->chip.irq_ack = stm32_irq_ack;
857 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
858 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
859 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
860 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
861 gc->suspend = stm32_irq_suspend;
862 gc->resume = stm32_irq_resume;
863 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
864
865 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
866 gc->private = (void *)chip_data;
867 }
868
869 nr_irqs = of_irq_count(node);
870 for (i = 0; i < nr_irqs; i++) {
871 unsigned int irq = irq_of_parse_and_map(node, i);
872
873 irq_set_handler_data(irq, domain);
874 irq_set_chained_handler(irq, stm32_irq_handler);
875 }
876
877 return 0;
878
879out_free_domain:
880 irq_domain_remove(domain);
881out_unmap:
882 iounmap(host_data->base);
883 kfree(host_data->chips_data);
884 kfree(host_data);
885 return ret;
886}
887
888static const struct irq_domain_ops stm32_exti_h_domain_ops = {
889 .alloc = stm32_exti_h_domain_alloc,
890 .free = irq_domain_free_irqs_common,
891 .xlate = irq_domain_xlate_twocell,
892};
893
894static void stm32_exti_remove_irq(void *data)
895{
896 struct irq_domain *domain = data;
897
898 irq_domain_remove(domain);
899}
900
901static int stm32_exti_remove(struct platform_device *pdev)
902{
903 stm32_exti_h_syscore_deinit();
904 return 0;
905}
906
907static int stm32_exti_probe(struct platform_device *pdev)
908{
909 int ret, i;
910 struct device *dev = &pdev->dev;
911 struct device_node *np = dev->of_node;
912 struct irq_domain *parent_domain, *domain;
913 struct stm32_exti_host_data *host_data;
914 const struct stm32_exti_drv_data *drv_data;
915
916 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
917 if (!host_data)
918 return -ENOMEM;
919
920 /* check for optional hwspinlock which may be not available yet */
921 ret = of_hwspin_lock_get_id(np, 0);
922 if (ret == -EPROBE_DEFER)
923 /* hwspinlock framework not yet ready */
924 return ret;
925
926 if (ret >= 0) {
927 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
928 if (!host_data->hwlock) {
929 dev_err(dev, "Failed to request hwspinlock\n");
930 return -EINVAL;
931 }
932 } else if (ret != -ENOENT) {
933 /* note: ENOENT is a valid case (means 'no hwspinlock') */
934 dev_err(dev, "Failed to get hwspinlock\n");
935 return ret;
936 }
937
938 /* initialize host_data */
939 drv_data = of_device_get_match_data(dev);
940 if (!drv_data) {
941 dev_err(dev, "no of match data\n");
942 return -ENODEV;
943 }
944 host_data->drv_data = drv_data;
945
946 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
947 sizeof(*host_data->chips_data),
948 GFP_KERNEL);
949 if (!host_data->chips_data)
950 return -ENOMEM;
951
952 host_data->base = devm_platform_ioremap_resource(pdev, 0);
953 if (IS_ERR(host_data->base))
954 return PTR_ERR(host_data->base);
955
956 for (i = 0; i < drv_data->bank_nr; i++)
957 stm32_exti_chip_init(host_data, i, np);
958
959 parent_domain = irq_find_host(of_irq_find_parent(np));
960 if (!parent_domain) {
961 dev_err(dev, "GIC interrupt-parent not found\n");
962 return -EINVAL;
963 }
964
965 domain = irq_domain_add_hierarchy(parent_domain, 0,
966 drv_data->bank_nr * IRQS_PER_BANK,
967 np, &stm32_exti_h_domain_ops,
968 host_data);
969
970 if (!domain) {
971 dev_err(dev, "Could not register exti domain\n");
972 return -ENOMEM;
973 }
974
975 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
976 if (ret)
977 return ret;
978
979 stm32_exti_h_syscore_init(host_data);
980
981 return 0;
982}
983
984/* platform driver only for MP1 */
985static const struct of_device_id stm32_exti_ids[] = {
986 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
987 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
988 {},
989};
990MODULE_DEVICE_TABLE(of, stm32_exti_ids);
991
992static struct platform_driver stm32_exti_driver = {
993 .probe = stm32_exti_probe,
994 .remove = stm32_exti_remove,
995 .driver = {
996 .name = "stm32_exti",
997 .of_match_table = stm32_exti_ids,
998 },
999};
1000
1001static int __init stm32_exti_arch_init(void)
1002{
1003 return platform_driver_register(&stm32_exti_driver);
1004}
1005
1006static void __exit stm32_exti_arch_exit(void)
1007{
1008 return platform_driver_unregister(&stm32_exti_driver);
1009}
1010
1011arch_initcall(stm32_exti_arch_init);
1012module_exit(stm32_exti_arch_exit);
1013
1014/* no platform driver for F4 and H7 */
1015static int __init stm32f4_exti_of_init(struct device_node *np,
1016 struct device_node *parent)
1017{
1018 return stm32_exti_init(&stm32f4xx_drv_data, np);
1019}
1020
1021IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
1022
1023static int __init stm32h7_exti_of_init(struct device_node *np,
1024 struct device_node *parent)
1025{
1026 return stm32_exti_init(&stm32h7xx_drv_data, np);
1027}
1028
1029IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);