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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11
12#include <linux/bits.h>
13#include <linux/compiler_types.h>
14#include <linux/completion.h>
15#include <linux/dev_printk.h>
16#include <linux/errno.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/types.h>
20
21#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
22 I2C_FUNC_SMBUS_BYTE | \
23 I2C_FUNC_SMBUS_BYTE_DATA | \
24 I2C_FUNC_SMBUS_WORD_DATA | \
25 I2C_FUNC_SMBUS_BLOCK_DATA | \
26 I2C_FUNC_SMBUS_I2C_BLOCK)
27
28#define DW_IC_CON_MASTER BIT(0)
29#define DW_IC_CON_SPEED_STD (1 << 1)
30#define DW_IC_CON_SPEED_FAST (2 << 1)
31#define DW_IC_CON_SPEED_HIGH (3 << 1)
32#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
33#define DW_IC_CON_10BITADDR_SLAVE BIT(3)
34#define DW_IC_CON_10BITADDR_MASTER BIT(4)
35#define DW_IC_CON_RESTART_EN BIT(5)
36#define DW_IC_CON_SLAVE_DISABLE BIT(6)
37#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
38#define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
39#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
40#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
41
42#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
43#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
44
45/*
46 * Registers offset
47 */
48#define DW_IC_CON 0x00
49#define DW_IC_TAR 0x04
50#define DW_IC_SAR 0x08
51#define DW_IC_DATA_CMD 0x10
52#define DW_IC_SS_SCL_HCNT 0x14
53#define DW_IC_SS_SCL_LCNT 0x18
54#define DW_IC_FS_SCL_HCNT 0x1c
55#define DW_IC_FS_SCL_LCNT 0x20
56#define DW_IC_HS_SCL_HCNT 0x24
57#define DW_IC_HS_SCL_LCNT 0x28
58#define DW_IC_INTR_STAT 0x2c
59#define DW_IC_INTR_MASK 0x30
60#define DW_IC_RAW_INTR_STAT 0x34
61#define DW_IC_RX_TL 0x38
62#define DW_IC_TX_TL 0x3c
63#define DW_IC_CLR_INTR 0x40
64#define DW_IC_CLR_RX_UNDER 0x44
65#define DW_IC_CLR_RX_OVER 0x48
66#define DW_IC_CLR_TX_OVER 0x4c
67#define DW_IC_CLR_RD_REQ 0x50
68#define DW_IC_CLR_TX_ABRT 0x54
69#define DW_IC_CLR_RX_DONE 0x58
70#define DW_IC_CLR_ACTIVITY 0x5c
71#define DW_IC_CLR_STOP_DET 0x60
72#define DW_IC_CLR_START_DET 0x64
73#define DW_IC_CLR_GEN_CALL 0x68
74#define DW_IC_ENABLE 0x6c
75#define DW_IC_STATUS 0x70
76#define DW_IC_TXFLR 0x74
77#define DW_IC_RXFLR 0x78
78#define DW_IC_SDA_HOLD 0x7c
79#define DW_IC_TX_ABRT_SOURCE 0x80
80#define DW_IC_ENABLE_STATUS 0x9c
81#define DW_IC_CLR_RESTART_DET 0xa8
82#define DW_IC_COMP_PARAM_1 0xf4
83#define DW_IC_COMP_VERSION 0xf8
84#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */
85#define DW_IC_COMP_TYPE 0xfc
86#define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */
87
88#define DW_IC_INTR_RX_UNDER BIT(0)
89#define DW_IC_INTR_RX_OVER BIT(1)
90#define DW_IC_INTR_RX_FULL BIT(2)
91#define DW_IC_INTR_TX_OVER BIT(3)
92#define DW_IC_INTR_TX_EMPTY BIT(4)
93#define DW_IC_INTR_RD_REQ BIT(5)
94#define DW_IC_INTR_TX_ABRT BIT(6)
95#define DW_IC_INTR_RX_DONE BIT(7)
96#define DW_IC_INTR_ACTIVITY BIT(8)
97#define DW_IC_INTR_STOP_DET BIT(9)
98#define DW_IC_INTR_START_DET BIT(10)
99#define DW_IC_INTR_GEN_CALL BIT(11)
100#define DW_IC_INTR_RESTART_DET BIT(12)
101#define DW_IC_INTR_MST_ON_HOLD BIT(13)
102
103#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
104 DW_IC_INTR_TX_ABRT | \
105 DW_IC_INTR_STOP_DET)
106#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
107 DW_IC_INTR_TX_EMPTY)
108#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
109 DW_IC_INTR_RX_UNDER | \
110 DW_IC_INTR_RD_REQ)
111
112#define DW_IC_ENABLE_ABORT BIT(1)
113
114#define DW_IC_STATUS_ACTIVITY BIT(0)
115#define DW_IC_STATUS_TFE BIT(2)
116#define DW_IC_STATUS_RFNE BIT(3)
117#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
118#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
119
120#define DW_IC_SDA_HOLD_RX_SHIFT 16
121#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
122
123#define DW_IC_ERR_TX_ABRT 0x1
124
125#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
126
127#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
128#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
129
130/*
131 * Sofware status flags
132 */
133#define STATUS_ACTIVE BIT(0)
134#define STATUS_WRITE_IN_PROGRESS BIT(1)
135#define STATUS_READ_IN_PROGRESS BIT(2)
136#define STATUS_MASK GENMASK(2, 0)
137
138/*
139 * operation modes
140 */
141#define DW_IC_MASTER 0
142#define DW_IC_SLAVE 1
143
144/*
145 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
146 *
147 * Only expected abort codes are listed here
148 * refer to the datasheet for the full list
149 */
150#define ABRT_7B_ADDR_NOACK 0
151#define ABRT_10ADDR1_NOACK 1
152#define ABRT_10ADDR2_NOACK 2
153#define ABRT_TXDATA_NOACK 3
154#define ABRT_GCALL_NOACK 4
155#define ABRT_GCALL_READ 5
156#define ABRT_SBYTE_ACKDET 7
157#define ABRT_SBYTE_NORSTRT 9
158#define ABRT_10B_RD_NORSTRT 10
159#define ABRT_MASTER_DIS 11
160#define ARB_LOST 12
161#define ABRT_SLAVE_FLUSH_TXFIFO 13
162#define ABRT_SLAVE_ARBLOST 14
163#define ABRT_SLAVE_RD_INTX 15
164
165#define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
166#define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
167#define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK)
168#define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK)
169#define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK)
170#define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ)
171#define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET)
172#define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT)
173#define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT)
174#define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS)
175#define DW_IC_TX_ARB_LOST BIT(ARB_LOST)
176#define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX)
177#define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
178#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
179
180#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
181 DW_IC_TX_ABRT_10ADDR1_NOACK | \
182 DW_IC_TX_ABRT_10ADDR2_NOACK | \
183 DW_IC_TX_ABRT_TXDATA_NOACK | \
184 DW_IC_TX_ABRT_GCALL_NOACK)
185
186struct clk;
187struct device;
188struct reset_control;
189
190/**
191 * struct dw_i2c_dev - private i2c-designware data
192 * @dev: driver model device node
193 * @map: IO registers map
194 * @sysmap: System controller registers map
195 * @base: IO registers pointer
196 * @ext: Extended IO registers pointer
197 * @cmd_complete: tx completion indicator
198 * @clk: input reference clock
199 * @pclk: clock required to access the registers
200 * @rst: optional reset for the controller
201 * @slave: represent an I2C slave device
202 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
203 * @cmd_err: run time hadware error code
204 * @msgs: points to an array of messages currently being transferred
205 * @msgs_num: the number of elements in msgs
206 * @msg_write_idx: the element index of the current tx message in the msgs array
207 * @tx_buf_len: the length of the current tx buffer
208 * @tx_buf: the current tx buffer
209 * @msg_read_idx: the element index of the current rx message in the msgs array
210 * @rx_buf_len: the length of the current rx buffer
211 * @rx_buf: the current rx buffer
212 * @msg_err: error status of the current transfer
213 * @status: i2c master status, one of STATUS_*
214 * @abort_source: copy of the TX_ABRT_SOURCE register
215 * @irq: interrupt number for the i2c master
216 * @flags: platform specific flags like type of IO accessors or model
217 * @adapter: i2c subsystem adapter node
218 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
219 * @master_cfg: configuration for the master device
220 * @slave_cfg: configuration for the slave device
221 * @tx_fifo_depth: depth of the hardware tx fifo
222 * @rx_fifo_depth: depth of the hardware rx fifo
223 * @rx_outstanding: current master-rx elements in tx fifo
224 * @timings: bus clock frequency, SDA hold and other timings
225 * @sda_hold_time: SDA hold value
226 * @ss_hcnt: standard speed HCNT value
227 * @ss_lcnt: standard speed LCNT value
228 * @fs_hcnt: fast speed HCNT value
229 * @fs_lcnt: fast speed LCNT value
230 * @fp_hcnt: fast plus HCNT value
231 * @fp_lcnt: fast plus LCNT value
232 * @hs_hcnt: high speed HCNT value
233 * @hs_lcnt: high speed LCNT value
234 * @acquire_lock: function to acquire a hardware lock on the bus
235 * @release_lock: function to release a hardware lock on the bus
236 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's
237 * -1 if there is no semaphore.
238 * @shared_with_punit: true if this bus is shared with the SoCs PUNIT
239 * @disable: function to disable the controller
240 * @init: function to initialize the I2C hardware
241 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
242 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
243 * @rinfo: I²C GPIO recovery information
244 *
245 * HCNT and LCNT parameters can be used if the platform knows more accurate
246 * values than the one computed based only on the input clock frequency.
247 * Leave them to be %0 if not used.
248 */
249struct dw_i2c_dev {
250 struct device *dev;
251 struct regmap *map;
252 struct regmap *sysmap;
253 void __iomem *base;
254 void __iomem *ext;
255 struct completion cmd_complete;
256 struct clk *clk;
257 struct clk *pclk;
258 struct reset_control *rst;
259 struct i2c_client *slave;
260 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
261 int cmd_err;
262 struct i2c_msg *msgs;
263 int msgs_num;
264 int msg_write_idx;
265 u32 tx_buf_len;
266 u8 *tx_buf;
267 int msg_read_idx;
268 u32 rx_buf_len;
269 u8 *rx_buf;
270 int msg_err;
271 unsigned int status;
272 unsigned int abort_source;
273 int irq;
274 u32 flags;
275 struct i2c_adapter adapter;
276 u32 functionality;
277 u32 master_cfg;
278 u32 slave_cfg;
279 unsigned int tx_fifo_depth;
280 unsigned int rx_fifo_depth;
281 int rx_outstanding;
282 struct i2c_timings timings;
283 u32 sda_hold_time;
284 u16 ss_hcnt;
285 u16 ss_lcnt;
286 u16 fs_hcnt;
287 u16 fs_lcnt;
288 u16 fp_hcnt;
289 u16 fp_lcnt;
290 u16 hs_hcnt;
291 u16 hs_lcnt;
292 int (*acquire_lock)(void);
293 void (*release_lock)(void);
294 int semaphore_idx;
295 bool shared_with_punit;
296 void (*disable)(struct dw_i2c_dev *dev);
297 int (*init)(struct dw_i2c_dev *dev);
298 int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
299 int mode;
300 struct i2c_bus_recovery_info rinfo;
301};
302
303#define ACCESS_INTR_MASK BIT(0)
304#define ACCESS_NO_IRQ_SUSPEND BIT(1)
305#define ARBITRATION_SEMAPHORE BIT(2)
306
307#define MODEL_MSCC_OCELOT BIT(8)
308#define MODEL_BAIKAL_BT1 BIT(9)
309#define MODEL_AMD_NAVI_GPU BIT(10)
310#define MODEL_WANGXUN_SP BIT(11)
311#define MODEL_MASK GENMASK(11, 8)
312
313/*
314 * Enable UCSI interrupt by writing 0xd at register
315 * offset 0x474 specified in hardware specification.
316 */
317#define AMD_UCSI_INTR_REG 0x474
318#define AMD_UCSI_INTR_EN 0xd
319
320#define TXGBE_TX_FIFO_DEPTH 4
321#define TXGBE_RX_FIFO_DEPTH 0
322
323struct i2c_dw_semaphore_callbacks {
324 int (*probe)(struct dw_i2c_dev *dev);
325 void (*remove)(struct dw_i2c_dev *dev);
326};
327
328int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
329u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
330u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
331int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
332u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
333int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
334int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
335void i2c_dw_release_lock(struct dw_i2c_dev *dev);
336int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
337int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
338int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
339u32 i2c_dw_func(struct i2c_adapter *adap);
340void i2c_dw_disable(struct dw_i2c_dev *dev);
341
342static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
343{
344 dev->status |= STATUS_ACTIVE;
345 regmap_write(dev->map, DW_IC_ENABLE, 1);
346}
347
348static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
349{
350 regmap_write(dev->map, DW_IC_ENABLE, 0);
351 dev->status &= ~STATUS_ACTIVE;
352}
353
354void __i2c_dw_disable(struct dw_i2c_dev *dev);
355
356extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
357extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
358
359#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
360extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
361extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
362#else
363static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
364static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
365#endif
366
367static inline int i2c_dw_probe(struct dw_i2c_dev *dev)
368{
369 switch (dev->mode) {
370 case DW_IC_SLAVE:
371 return i2c_dw_probe_slave(dev);
372 case DW_IC_MASTER:
373 return i2c_dw_probe_master(dev);
374 default:
375 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
376 return -EINVAL;
377 }
378}
379
380static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
381{
382 if (i2c_detect_slave_mode(dev->dev))
383 i2c_dw_configure_slave(dev);
384 else
385 i2c_dw_configure_master(dev);
386}
387
388#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
389int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
390#endif
391
392#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
393int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
394#endif
395
396int i2c_dw_validate_speed(struct dw_i2c_dev *dev);
397void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev);
398
399#if IS_ENABLED(CONFIG_ACPI)
400int i2c_dw_acpi_configure(struct device *device);
401#else
402static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; }
403#endif
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28
29
30#define DW_IC_CON_MASTER 0x1
31#define DW_IC_CON_SPEED_STD 0x2
32#define DW_IC_CON_SPEED_FAST 0x4
33#define DW_IC_CON_10BITADDR_MASTER 0x10
34#define DW_IC_CON_RESTART_EN 0x20
35#define DW_IC_CON_SLAVE_DISABLE 0x40
36
37
38/**
39 * struct dw_i2c_dev - private i2c-designware data
40 * @dev: driver model device node
41 * @base: IO registers pointer
42 * @cmd_complete: tx completion indicator
43 * @lock: protect this struct and IO registers
44 * @clk: input reference clock
45 * @cmd_err: run time hadware error code
46 * @msgs: points to an array of messages currently being transfered
47 * @msgs_num: the number of elements in msgs
48 * @msg_write_idx: the element index of the current tx message in the msgs
49 * array
50 * @tx_buf_len: the length of the current tx buffer
51 * @tx_buf: the current tx buffer
52 * @msg_read_idx: the element index of the current rx message in the msgs
53 * array
54 * @rx_buf_len: the length of the current rx buffer
55 * @rx_buf: the current rx buffer
56 * @msg_err: error status of the current transfer
57 * @status: i2c master status, one of STATUS_*
58 * @abort_source: copy of the TX_ABRT_SOURCE register
59 * @irq: interrupt number for the i2c master
60 * @adapter: i2c subsystem adapter node
61 * @tx_fifo_depth: depth of the hardware tx fifo
62 * @rx_fifo_depth: depth of the hardware rx fifo
63 * @rx_outstanding: current master-rx elements in tx fifo
64 * @ss_hcnt: standard speed HCNT value
65 * @ss_lcnt: standard speed LCNT value
66 * @fs_hcnt: fast speed HCNT value
67 * @fs_lcnt: fast speed LCNT value
68 *
69 * HCNT and LCNT parameters can be used if the platform knows more accurate
70 * values than the one computed based only on the input clock frequency.
71 * Leave them to be %0 if not used.
72 */
73struct dw_i2c_dev {
74 struct device *dev;
75 void __iomem *base;
76 struct completion cmd_complete;
77 struct mutex lock;
78 struct clk *clk;
79 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
80 struct dw_pci_controller *controller;
81 int cmd_err;
82 struct i2c_msg *msgs;
83 int msgs_num;
84 int msg_write_idx;
85 u32 tx_buf_len;
86 u8 *tx_buf;
87 int msg_read_idx;
88 u32 rx_buf_len;
89 u8 *rx_buf;
90 int msg_err;
91 unsigned int status;
92 u32 abort_source;
93 int irq;
94 u32 accessor_flags;
95 struct i2c_adapter adapter;
96 u32 functionality;
97 u32 master_cfg;
98 unsigned int tx_fifo_depth;
99 unsigned int rx_fifo_depth;
100 int rx_outstanding;
101 u32 sda_hold_time;
102 u32 sda_falling_time;
103 u32 scl_falling_time;
104 u16 ss_hcnt;
105 u16 ss_lcnt;
106 u16 fs_hcnt;
107 u16 fs_lcnt;
108};
109
110#define ACCESS_SWAP 0x00000001
111#define ACCESS_16BIT 0x00000002
112
113extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
114extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
115extern int i2c_dw_init(struct dw_i2c_dev *dev);
116extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
117 int num);
118extern u32 i2c_dw_func(struct i2c_adapter *adap);
119extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
120extern void i2c_dw_enable(struct dw_i2c_dev *dev);
121extern u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev);
122extern void i2c_dw_disable(struct dw_i2c_dev *dev);
123extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
124extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
125extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);