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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver For Marvell Two-channel DMA Engine
4 *
5 * Copyright: Marvell International Ltd.
6 */
7
8#include <linux/err.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/dma-mapping.h>
14#include <linux/slab.h>
15#include <linux/dmaengine.h>
16#include <linux/platform_device.h>
17#include <linux/property.h>
18#include <linux/device.h>
19#include <linux/genalloc.h>
20#include <linux/of_dma.h>
21
22#include "dmaengine.h"
23
24/*
25 * Two-Channel DMA registers
26 */
27#define TDBCR 0x00 /* Byte Count */
28#define TDSAR 0x10 /* Src Addr */
29#define TDDAR 0x20 /* Dst Addr */
30#define TDNDPR 0x30 /* Next Desc */
31#define TDCR 0x40 /* Control */
32#define TDCP 0x60 /* Priority*/
33#define TDCDPR 0x70 /* Current Desc */
34#define TDIMR 0x80 /* Int Mask */
35#define TDISR 0xa0 /* Int Status */
36
37/* Two-Channel DMA Control Register */
38#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
39#define TDCR_SSZ_12_BITS (0x1 << 22)
40#define TDCR_SSZ_16_BITS (0x2 << 22)
41#define TDCR_SSZ_20_BITS (0x3 << 22)
42#define TDCR_SSZ_24_BITS (0x4 << 22)
43#define TDCR_SSZ_32_BITS (0x5 << 22)
44#define TDCR_SSZ_SHIFT (0x1 << 22)
45#define TDCR_SSZ_MASK (0x7 << 22)
46#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
47#define TDCR_ABR (0x1 << 20) /* Channel Abort */
48#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
49#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
50#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
51#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
52#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
53#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
54#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
55#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
56#define TDCR_BURSTSZ_4B (0x0 << 6)
57#define TDCR_BURSTSZ_8B (0x1 << 6)
58#define TDCR_BURSTSZ_16B (0x3 << 6)
59#define TDCR_BURSTSZ_32B (0x6 << 6)
60#define TDCR_BURSTSZ_64B (0x7 << 6)
61#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
62#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
63#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
64#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
65#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
66#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
67#define TDCR_BURSTSZ_128B (0x5 << 6)
68#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
69#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
70#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
71#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
72#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
73#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
74#define TDCR_DSTDESCCONT (0x1 << 1)
75#define TDCR_SRCDESTCONT (0x1 << 0)
76
77/* Two-Channel DMA Int Mask Register */
78#define TDIMR_COMP (0x1 << 0)
79
80/* Two-Channel DMA Int Status Register */
81#define TDISR_COMP (0x1 << 0)
82
83/*
84 * Two-Channel DMA Descriptor Struct
85 * NOTE: desc's buf must be aligned to 16 bytes.
86 */
87struct mmp_tdma_desc {
88 u32 byte_cnt;
89 u32 src_addr;
90 u32 dst_addr;
91 u32 nxt_desc;
92};
93
94enum mmp_tdma_type {
95 MMP_AUD_TDMA = 0,
96 PXA910_SQU,
97};
98
99#define TDMA_MAX_XFER_BYTES SZ_64K
100
101struct mmp_tdma_chan {
102 struct device *dev;
103 struct dma_chan chan;
104 struct dma_async_tx_descriptor desc;
105 struct tasklet_struct tasklet;
106
107 struct mmp_tdma_desc *desc_arr;
108 dma_addr_t desc_arr_phys;
109 int desc_num;
110 enum dma_transfer_direction dir;
111 dma_addr_t dev_addr;
112 u32 burst_sz;
113 enum dma_slave_buswidth buswidth;
114 enum dma_status status;
115 struct dma_slave_config slave_config;
116
117 int idx;
118 enum mmp_tdma_type type;
119 int irq;
120 void __iomem *reg_base;
121
122 size_t buf_len;
123 size_t period_len;
124 size_t pos;
125
126 struct gen_pool *pool;
127};
128
129#define TDMA_CHANNEL_NUM 2
130struct mmp_tdma_device {
131 struct device *dev;
132 void __iomem *base;
133 struct dma_device device;
134 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
135};
136
137#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
138
139static int mmp_tdma_config_write(struct dma_chan *chan,
140 enum dma_transfer_direction dir,
141 struct dma_slave_config *dmaengine_cfg);
142
143static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
144{
145 writel(phys, tdmac->reg_base + TDNDPR);
146 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
147 tdmac->reg_base + TDCR);
148}
149
150static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
151{
152 if (enable)
153 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
154 else
155 writel(0, tdmac->reg_base + TDIMR);
156}
157
158static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
159{
160 /* enable dma chan */
161 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
162 tdmac->reg_base + TDCR);
163 tdmac->status = DMA_IN_PROGRESS;
164}
165
166static int mmp_tdma_disable_chan(struct dma_chan *chan)
167{
168 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
169 u32 tdcr;
170
171 tdcr = readl(tdmac->reg_base + TDCR);
172 tdcr |= TDCR_ABR;
173 tdcr &= ~TDCR_CHANEN;
174 writel(tdcr, tdmac->reg_base + TDCR);
175
176 tdmac->status = DMA_COMPLETE;
177
178 return 0;
179}
180
181static int mmp_tdma_resume_chan(struct dma_chan *chan)
182{
183 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
184
185 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
186 tdmac->reg_base + TDCR);
187 tdmac->status = DMA_IN_PROGRESS;
188
189 return 0;
190}
191
192static int mmp_tdma_pause_chan(struct dma_chan *chan)
193{
194 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
195
196 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
197 tdmac->reg_base + TDCR);
198 tdmac->status = DMA_PAUSED;
199
200 return 0;
201}
202
203static int mmp_tdma_config_chan(struct dma_chan *chan)
204{
205 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
206 unsigned int tdcr = 0;
207
208 mmp_tdma_disable_chan(chan);
209
210 if (tdmac->dir == DMA_MEM_TO_DEV)
211 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
212 else if (tdmac->dir == DMA_DEV_TO_MEM)
213 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
214
215 if (tdmac->type == MMP_AUD_TDMA) {
216 tdcr |= TDCR_PACKMOD;
217
218 switch (tdmac->burst_sz) {
219 case 4:
220 tdcr |= TDCR_BURSTSZ_4B;
221 break;
222 case 8:
223 tdcr |= TDCR_BURSTSZ_8B;
224 break;
225 case 16:
226 tdcr |= TDCR_BURSTSZ_16B;
227 break;
228 case 32:
229 tdcr |= TDCR_BURSTSZ_32B;
230 break;
231 case 64:
232 tdcr |= TDCR_BURSTSZ_64B;
233 break;
234 case 128:
235 tdcr |= TDCR_BURSTSZ_128B;
236 break;
237 default:
238 dev_err(tdmac->dev, "unknown burst size.\n");
239 return -EINVAL;
240 }
241
242 switch (tdmac->buswidth) {
243 case DMA_SLAVE_BUSWIDTH_1_BYTE:
244 tdcr |= TDCR_SSZ_8_BITS;
245 break;
246 case DMA_SLAVE_BUSWIDTH_2_BYTES:
247 tdcr |= TDCR_SSZ_16_BITS;
248 break;
249 case DMA_SLAVE_BUSWIDTH_4_BYTES:
250 tdcr |= TDCR_SSZ_32_BITS;
251 break;
252 default:
253 dev_err(tdmac->dev, "unknown bus size.\n");
254 return -EINVAL;
255 }
256 } else if (tdmac->type == PXA910_SQU) {
257 tdcr |= TDCR_SSPMOD;
258
259 switch (tdmac->burst_sz) {
260 case 1:
261 tdcr |= TDCR_BURSTSZ_SQU_1B;
262 break;
263 case 2:
264 tdcr |= TDCR_BURSTSZ_SQU_2B;
265 break;
266 case 4:
267 tdcr |= TDCR_BURSTSZ_SQU_4B;
268 break;
269 case 8:
270 tdcr |= TDCR_BURSTSZ_SQU_8B;
271 break;
272 case 16:
273 tdcr |= TDCR_BURSTSZ_SQU_16B;
274 break;
275 case 32:
276 tdcr |= TDCR_BURSTSZ_SQU_32B;
277 break;
278 default:
279 dev_err(tdmac->dev, "unknown burst size.\n");
280 return -EINVAL;
281 }
282 }
283
284 writel(tdcr, tdmac->reg_base + TDCR);
285 return 0;
286}
287
288static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
289{
290 u32 reg = readl(tdmac->reg_base + TDISR);
291
292 if (reg & TDISR_COMP) {
293 /* clear irq */
294 reg &= ~TDISR_COMP;
295 writel(reg, tdmac->reg_base + TDISR);
296
297 return 0;
298 }
299 return -EAGAIN;
300}
301
302static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac)
303{
304 size_t reg;
305
306 if (tdmac->idx == 0) {
307 reg = __raw_readl(tdmac->reg_base + TDSAR);
308 reg -= tdmac->desc_arr[0].src_addr;
309 } else if (tdmac->idx == 1) {
310 reg = __raw_readl(tdmac->reg_base + TDDAR);
311 reg -= tdmac->desc_arr[0].dst_addr;
312 } else
313 return -EINVAL;
314
315 return reg;
316}
317
318static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
319{
320 struct mmp_tdma_chan *tdmac = dev_id;
321
322 if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
323 tasklet_schedule(&tdmac->tasklet);
324 return IRQ_HANDLED;
325 } else
326 return IRQ_NONE;
327}
328
329static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
330{
331 struct mmp_tdma_device *tdev = dev_id;
332 int i, ret;
333 int irq_num = 0;
334
335 for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
336 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
337
338 ret = mmp_tdma_chan_handler(irq, tdmac);
339 if (ret == IRQ_HANDLED)
340 irq_num++;
341 }
342
343 if (irq_num)
344 return IRQ_HANDLED;
345 else
346 return IRQ_NONE;
347}
348
349static void dma_do_tasklet(struct tasklet_struct *t)
350{
351 struct mmp_tdma_chan *tdmac = from_tasklet(tdmac, t, tasklet);
352
353 dmaengine_desc_get_callback_invoke(&tdmac->desc, NULL);
354}
355
356static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
357{
358 struct gen_pool *gpool;
359 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
360
361 gpool = tdmac->pool;
362 if (gpool && tdmac->desc_arr)
363 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
364 size);
365 tdmac->desc_arr = NULL;
366 if (tdmac->status == DMA_ERROR)
367 tdmac->status = DMA_COMPLETE;
368
369 return;
370}
371
372static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
373{
374 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
375
376 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
377
378 return 0;
379}
380
381static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
382{
383 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
384 int ret;
385
386 dma_async_tx_descriptor_init(&tdmac->desc, chan);
387 tdmac->desc.tx_submit = mmp_tdma_tx_submit;
388
389 if (tdmac->irq) {
390 ret = devm_request_irq(tdmac->dev, tdmac->irq,
391 mmp_tdma_chan_handler, 0, "tdma", tdmac);
392 if (ret)
393 return ret;
394 }
395 return 1;
396}
397
398static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
399{
400 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
401
402 if (tdmac->irq)
403 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
404 mmp_tdma_free_descriptor(tdmac);
405 return;
406}
407
408static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
409{
410 struct gen_pool *gpool;
411 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
412
413 gpool = tdmac->pool;
414 if (!gpool)
415 return NULL;
416
417 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
418
419 return tdmac->desc_arr;
420}
421
422static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
423 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
424 size_t period_len, enum dma_transfer_direction direction,
425 unsigned long flags)
426{
427 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
428 struct mmp_tdma_desc *desc;
429 int num_periods = buf_len / period_len;
430 int i = 0, buf = 0;
431
432 if (!is_slave_direction(direction)) {
433 dev_err(tdmac->dev, "unsupported transfer direction\n");
434 return NULL;
435 }
436
437 if (tdmac->status != DMA_COMPLETE) {
438 dev_err(tdmac->dev, "controller busy");
439 return NULL;
440 }
441
442 if (period_len > TDMA_MAX_XFER_BYTES) {
443 dev_err(tdmac->dev,
444 "maximum period size exceeded: %zu > %d\n",
445 period_len, TDMA_MAX_XFER_BYTES);
446 goto err_out;
447 }
448
449 tdmac->status = DMA_IN_PROGRESS;
450 tdmac->desc_num = num_periods;
451 desc = mmp_tdma_alloc_descriptor(tdmac);
452 if (!desc)
453 goto err_out;
454
455 if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
456 goto err_out;
457
458 while (buf < buf_len) {
459 desc = &tdmac->desc_arr[i];
460
461 if (i + 1 == num_periods)
462 desc->nxt_desc = tdmac->desc_arr_phys;
463 else
464 desc->nxt_desc = tdmac->desc_arr_phys +
465 sizeof(*desc) * (i + 1);
466
467 if (direction == DMA_MEM_TO_DEV) {
468 desc->src_addr = dma_addr;
469 desc->dst_addr = tdmac->dev_addr;
470 } else {
471 desc->src_addr = tdmac->dev_addr;
472 desc->dst_addr = dma_addr;
473 }
474 desc->byte_cnt = period_len;
475 dma_addr += period_len;
476 buf += period_len;
477 i++;
478 }
479
480 /* enable interrupt */
481 if (flags & DMA_PREP_INTERRUPT)
482 mmp_tdma_enable_irq(tdmac, true);
483
484 tdmac->buf_len = buf_len;
485 tdmac->period_len = period_len;
486 tdmac->pos = 0;
487
488 return &tdmac->desc;
489
490err_out:
491 tdmac->status = DMA_ERROR;
492 return NULL;
493}
494
495static int mmp_tdma_terminate_all(struct dma_chan *chan)
496{
497 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
498
499 mmp_tdma_disable_chan(chan);
500 /* disable interrupt */
501 mmp_tdma_enable_irq(tdmac, false);
502
503 return 0;
504}
505
506static int mmp_tdma_config(struct dma_chan *chan,
507 struct dma_slave_config *dmaengine_cfg)
508{
509 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
510
511 memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
512
513 return 0;
514}
515
516static int mmp_tdma_config_write(struct dma_chan *chan,
517 enum dma_transfer_direction dir,
518 struct dma_slave_config *dmaengine_cfg)
519{
520 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
521
522 if (dir == DMA_DEV_TO_MEM) {
523 tdmac->dev_addr = dmaengine_cfg->src_addr;
524 tdmac->burst_sz = dmaengine_cfg->src_maxburst;
525 tdmac->buswidth = dmaengine_cfg->src_addr_width;
526 } else {
527 tdmac->dev_addr = dmaengine_cfg->dst_addr;
528 tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
529 tdmac->buswidth = dmaengine_cfg->dst_addr_width;
530 }
531 tdmac->dir = dir;
532
533 return mmp_tdma_config_chan(chan);
534}
535
536static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
537 dma_cookie_t cookie, struct dma_tx_state *txstate)
538{
539 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
540
541 tdmac->pos = mmp_tdma_get_pos(tdmac);
542 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
543 tdmac->buf_len - tdmac->pos);
544
545 return tdmac->status;
546}
547
548static void mmp_tdma_issue_pending(struct dma_chan *chan)
549{
550 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
551
552 mmp_tdma_enable_chan(tdmac);
553}
554
555static void mmp_tdma_remove(struct platform_device *pdev)
556{
557 if (pdev->dev.of_node)
558 of_dma_controller_free(pdev->dev.of_node);
559}
560
561static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
562 int idx, int irq,
563 int type, struct gen_pool *pool)
564{
565 struct mmp_tdma_chan *tdmac;
566
567 if (idx >= TDMA_CHANNEL_NUM) {
568 dev_err(tdev->dev, "too many channels for device!\n");
569 return -EINVAL;
570 }
571
572 /* alloc channel */
573 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
574 if (!tdmac)
575 return -ENOMEM;
576
577 if (irq)
578 tdmac->irq = irq;
579 tdmac->dev = tdev->dev;
580 tdmac->chan.device = &tdev->device;
581 tdmac->idx = idx;
582 tdmac->type = type;
583 tdmac->reg_base = tdev->base + idx * 4;
584 tdmac->pool = pool;
585 tdmac->status = DMA_COMPLETE;
586 tdev->tdmac[tdmac->idx] = tdmac;
587 tasklet_setup(&tdmac->tasklet, dma_do_tasklet);
588
589 /* add the channel to tdma_chan list */
590 list_add_tail(&tdmac->chan.device_node,
591 &tdev->device.channels);
592 return 0;
593}
594
595struct mmp_tdma_filter_param {
596 unsigned int chan_id;
597};
598
599static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
600{
601 struct mmp_tdma_filter_param *param = fn_param;
602
603 if (chan->chan_id != param->chan_id)
604 return false;
605
606 return true;
607}
608
609static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
610 struct of_dma *ofdma)
611{
612 struct mmp_tdma_device *tdev = ofdma->of_dma_data;
613 dma_cap_mask_t mask = tdev->device.cap_mask;
614 struct mmp_tdma_filter_param param;
615
616 if (dma_spec->args_count != 1)
617 return NULL;
618
619 param.chan_id = dma_spec->args[0];
620
621 if (param.chan_id >= TDMA_CHANNEL_NUM)
622 return NULL;
623
624 return __dma_request_channel(&mask, mmp_tdma_filter_fn, ¶m,
625 ofdma->of_node);
626}
627
628static const struct of_device_id mmp_tdma_dt_ids[] = {
629 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
630 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
631 {}
632};
633MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
634
635static int mmp_tdma_probe(struct platform_device *pdev)
636{
637 enum mmp_tdma_type type;
638 struct mmp_tdma_device *tdev;
639 int i, ret;
640 int irq = 0, irq_num = 0;
641 int chan_num = TDMA_CHANNEL_NUM;
642 struct gen_pool *pool = NULL;
643
644 type = (enum mmp_tdma_type)device_get_match_data(&pdev->dev);
645
646 /* always have couple channels */
647 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
648 if (!tdev)
649 return -ENOMEM;
650
651 tdev->dev = &pdev->dev;
652
653 for (i = 0; i < chan_num; i++) {
654 if (platform_get_irq(pdev, i) > 0)
655 irq_num++;
656 }
657
658 tdev->base = devm_platform_ioremap_resource(pdev, 0);
659 if (IS_ERR(tdev->base))
660 return PTR_ERR(tdev->base);
661
662 INIT_LIST_HEAD(&tdev->device.channels);
663
664 pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0);
665 if (!pool) {
666 dev_err(&pdev->dev, "asram pool not available\n");
667 return -ENOMEM;
668 }
669
670 if (irq_num != chan_num) {
671 irq = platform_get_irq(pdev, 0);
672 ret = devm_request_irq(&pdev->dev, irq,
673 mmp_tdma_int_handler, IRQF_SHARED, "tdma", tdev);
674 if (ret)
675 return ret;
676 }
677
678 /* initialize channel parameters */
679 for (i = 0; i < chan_num; i++) {
680 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
681 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
682 if (ret)
683 return ret;
684 }
685
686 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
687 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
688 tdev->device.dev = &pdev->dev;
689 tdev->device.device_alloc_chan_resources =
690 mmp_tdma_alloc_chan_resources;
691 tdev->device.device_free_chan_resources =
692 mmp_tdma_free_chan_resources;
693 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
694 tdev->device.device_tx_status = mmp_tdma_tx_status;
695 tdev->device.device_issue_pending = mmp_tdma_issue_pending;
696 tdev->device.device_config = mmp_tdma_config;
697 tdev->device.device_pause = mmp_tdma_pause_chan;
698 tdev->device.device_resume = mmp_tdma_resume_chan;
699 tdev->device.device_terminate_all = mmp_tdma_terminate_all;
700 tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
701
702 tdev->device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
703 if (type == MMP_AUD_TDMA) {
704 tdev->device.max_burst = SZ_128;
705 tdev->device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
706 tdev->device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
707 } else if (type == PXA910_SQU) {
708 tdev->device.max_burst = SZ_32;
709 }
710 tdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
711 tdev->device.descriptor_reuse = true;
712
713 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
714 platform_set_drvdata(pdev, tdev);
715
716 ret = dmaenginem_async_device_register(&tdev->device);
717 if (ret) {
718 dev_err(tdev->device.dev, "unable to register\n");
719 return ret;
720 }
721
722 ret = of_dma_controller_register(pdev->dev.of_node,
723 mmp_tdma_xlate, tdev);
724 if (ret) {
725 dev_err(tdev->device.dev, "failed to register controller\n");
726 return ret;
727 }
728
729 dev_info(tdev->device.dev, "initialized\n");
730 return 0;
731}
732
733static struct platform_driver mmp_tdma_driver = {
734 .driver = {
735 .name = "mmp-tdma",
736 .of_match_table = mmp_tdma_dt_ids,
737 },
738 .probe = mmp_tdma_probe,
739 .remove_new = mmp_tdma_remove,
740};
741
742module_platform_driver(mmp_tdma_driver);
743
744MODULE_LICENSE("GPL");
745MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
746MODULE_ALIAS("platform:mmp-tdma");
747MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
748MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
1/*
2 * Driver For Marvell Two-channel DMA Engine
3 *
4 * Copyright: Marvell International Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 */
11
12#include <linux/err.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/dma-mapping.h>
18#include <linux/slab.h>
19#include <linux/dmaengine.h>
20#include <linux/platform_device.h>
21#include <linux/device.h>
22#include <mach/regs-icu.h>
23#include <linux/platform_data/dma-mmp_tdma.h>
24#include <linux/of_device.h>
25#include <linux/of_dma.h>
26
27#include "dmaengine.h"
28
29/*
30 * Two-Channel DMA registers
31 */
32#define TDBCR 0x00 /* Byte Count */
33#define TDSAR 0x10 /* Src Addr */
34#define TDDAR 0x20 /* Dst Addr */
35#define TDNDPR 0x30 /* Next Desc */
36#define TDCR 0x40 /* Control */
37#define TDCP 0x60 /* Priority*/
38#define TDCDPR 0x70 /* Current Desc */
39#define TDIMR 0x80 /* Int Mask */
40#define TDISR 0xa0 /* Int Status */
41
42/* Two-Channel DMA Control Register */
43#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
44#define TDCR_SSZ_12_BITS (0x1 << 22)
45#define TDCR_SSZ_16_BITS (0x2 << 22)
46#define TDCR_SSZ_20_BITS (0x3 << 22)
47#define TDCR_SSZ_24_BITS (0x4 << 22)
48#define TDCR_SSZ_32_BITS (0x5 << 22)
49#define TDCR_SSZ_SHIFT (0x1 << 22)
50#define TDCR_SSZ_MASK (0x7 << 22)
51#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
52#define TDCR_ABR (0x1 << 20) /* Channel Abort */
53#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
54#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
55#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
56#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
57#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
58#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
59#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
60#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
61#define TDCR_BURSTSZ_4B (0x0 << 6)
62#define TDCR_BURSTSZ_8B (0x1 << 6)
63#define TDCR_BURSTSZ_16B (0x3 << 6)
64#define TDCR_BURSTSZ_32B (0x6 << 6)
65#define TDCR_BURSTSZ_64B (0x7 << 6)
66#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
67#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
68#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
69#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
70#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
71#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
72#define TDCR_BURSTSZ_128B (0x5 << 6)
73#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
74#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
75#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
76#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
77#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
78#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
79#define TDCR_DSTDESCCONT (0x1 << 1)
80#define TDCR_SRCDESTCONT (0x1 << 0)
81
82/* Two-Channel DMA Int Mask Register */
83#define TDIMR_COMP (0x1 << 0)
84
85/* Two-Channel DMA Int Status Register */
86#define TDISR_COMP (0x1 << 0)
87
88/*
89 * Two-Channel DMA Descriptor Struct
90 * NOTE: desc's buf must be aligned to 16 bytes.
91 */
92struct mmp_tdma_desc {
93 u32 byte_cnt;
94 u32 src_addr;
95 u32 dst_addr;
96 u32 nxt_desc;
97};
98
99enum mmp_tdma_type {
100 MMP_AUD_TDMA = 0,
101 PXA910_SQU,
102};
103
104#define TDMA_ALIGNMENT 3
105#define TDMA_MAX_XFER_BYTES SZ_64K
106
107struct mmp_tdma_chan {
108 struct device *dev;
109 struct dma_chan chan;
110 struct dma_async_tx_descriptor desc;
111 struct tasklet_struct tasklet;
112
113 struct mmp_tdma_desc *desc_arr;
114 phys_addr_t desc_arr_phys;
115 int desc_num;
116 enum dma_transfer_direction dir;
117 dma_addr_t dev_addr;
118 u32 burst_sz;
119 enum dma_slave_buswidth buswidth;
120 enum dma_status status;
121
122 int idx;
123 enum mmp_tdma_type type;
124 int irq;
125 void __iomem *reg_base;
126
127 size_t buf_len;
128 size_t period_len;
129 size_t pos;
130
131 struct gen_pool *pool;
132};
133
134#define TDMA_CHANNEL_NUM 2
135struct mmp_tdma_device {
136 struct device *dev;
137 void __iomem *base;
138 struct dma_device device;
139 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
140};
141
142#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
143
144static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
145{
146 writel(phys, tdmac->reg_base + TDNDPR);
147 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
148 tdmac->reg_base + TDCR);
149}
150
151static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
152{
153 /* enable irq */
154 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
155 /* enable dma chan */
156 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
157 tdmac->reg_base + TDCR);
158 tdmac->status = DMA_IN_PROGRESS;
159}
160
161static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
162{
163 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
164 tdmac->reg_base + TDCR);
165
166 /* disable irq */
167 writel(0, tdmac->reg_base + TDIMR);
168
169 tdmac->status = DMA_COMPLETE;
170}
171
172static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
173{
174 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
175 tdmac->reg_base + TDCR);
176 tdmac->status = DMA_IN_PROGRESS;
177}
178
179static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
180{
181 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
182 tdmac->reg_base + TDCR);
183 tdmac->status = DMA_PAUSED;
184}
185
186static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
187{
188 unsigned int tdcr = 0;
189
190 mmp_tdma_disable_chan(tdmac);
191
192 if (tdmac->dir == DMA_MEM_TO_DEV)
193 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
194 else if (tdmac->dir == DMA_DEV_TO_MEM)
195 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
196
197 if (tdmac->type == MMP_AUD_TDMA) {
198 tdcr |= TDCR_PACKMOD;
199
200 switch (tdmac->burst_sz) {
201 case 4:
202 tdcr |= TDCR_BURSTSZ_4B;
203 break;
204 case 8:
205 tdcr |= TDCR_BURSTSZ_8B;
206 break;
207 case 16:
208 tdcr |= TDCR_BURSTSZ_16B;
209 break;
210 case 32:
211 tdcr |= TDCR_BURSTSZ_32B;
212 break;
213 case 64:
214 tdcr |= TDCR_BURSTSZ_64B;
215 break;
216 case 128:
217 tdcr |= TDCR_BURSTSZ_128B;
218 break;
219 default:
220 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
221 return -EINVAL;
222 }
223
224 switch (tdmac->buswidth) {
225 case DMA_SLAVE_BUSWIDTH_1_BYTE:
226 tdcr |= TDCR_SSZ_8_BITS;
227 break;
228 case DMA_SLAVE_BUSWIDTH_2_BYTES:
229 tdcr |= TDCR_SSZ_16_BITS;
230 break;
231 case DMA_SLAVE_BUSWIDTH_4_BYTES:
232 tdcr |= TDCR_SSZ_32_BITS;
233 break;
234 default:
235 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
236 return -EINVAL;
237 }
238 } else if (tdmac->type == PXA910_SQU) {
239 tdcr |= TDCR_SSPMOD;
240
241 switch (tdmac->burst_sz) {
242 case 1:
243 tdcr |= TDCR_BURSTSZ_SQU_1B;
244 break;
245 case 2:
246 tdcr |= TDCR_BURSTSZ_SQU_2B;
247 break;
248 case 4:
249 tdcr |= TDCR_BURSTSZ_SQU_4B;
250 break;
251 case 8:
252 tdcr |= TDCR_BURSTSZ_SQU_8B;
253 break;
254 case 16:
255 tdcr |= TDCR_BURSTSZ_SQU_16B;
256 break;
257 case 32:
258 tdcr |= TDCR_BURSTSZ_SQU_32B;
259 break;
260 default:
261 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
262 return -EINVAL;
263 }
264 }
265
266 writel(tdcr, tdmac->reg_base + TDCR);
267 return 0;
268}
269
270static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
271{
272 u32 reg = readl(tdmac->reg_base + TDISR);
273
274 if (reg & TDISR_COMP) {
275 /* clear irq */
276 reg &= ~TDISR_COMP;
277 writel(reg, tdmac->reg_base + TDISR);
278
279 return 0;
280 }
281 return -EAGAIN;
282}
283
284static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
285{
286 struct mmp_tdma_chan *tdmac = dev_id;
287
288 if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
289 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
290 tasklet_schedule(&tdmac->tasklet);
291 return IRQ_HANDLED;
292 } else
293 return IRQ_NONE;
294}
295
296static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
297{
298 struct mmp_tdma_device *tdev = dev_id;
299 int i, ret;
300 int irq_num = 0;
301
302 for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
303 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
304
305 ret = mmp_tdma_chan_handler(irq, tdmac);
306 if (ret == IRQ_HANDLED)
307 irq_num++;
308 }
309
310 if (irq_num)
311 return IRQ_HANDLED;
312 else
313 return IRQ_NONE;
314}
315
316static void dma_do_tasklet(unsigned long data)
317{
318 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
319
320 if (tdmac->desc.callback)
321 tdmac->desc.callback(tdmac->desc.callback_param);
322
323}
324
325static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
326{
327 struct gen_pool *gpool;
328 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
329
330 gpool = tdmac->pool;
331 if (tdmac->desc_arr)
332 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
333 size);
334 tdmac->desc_arr = NULL;
335
336 return;
337}
338
339static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
340{
341 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
342
343 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
344
345 return 0;
346}
347
348static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
349{
350 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
351 int ret;
352
353 dma_async_tx_descriptor_init(&tdmac->desc, chan);
354 tdmac->desc.tx_submit = mmp_tdma_tx_submit;
355
356 if (tdmac->irq) {
357 ret = devm_request_irq(tdmac->dev, tdmac->irq,
358 mmp_tdma_chan_handler, 0, "tdma", tdmac);
359 if (ret)
360 return ret;
361 }
362 return 1;
363}
364
365static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
366{
367 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
368
369 if (tdmac->irq)
370 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
371 mmp_tdma_free_descriptor(tdmac);
372 return;
373}
374
375struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
376{
377 struct gen_pool *gpool;
378 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
379
380 gpool = tdmac->pool;
381 if (!gpool)
382 return NULL;
383
384 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
385
386 return tdmac->desc_arr;
387}
388
389static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
390 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
391 size_t period_len, enum dma_transfer_direction direction,
392 unsigned long flags, void *context)
393{
394 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
395 struct mmp_tdma_desc *desc;
396 int num_periods = buf_len / period_len;
397 int i = 0, buf = 0;
398
399 if (tdmac->status != DMA_COMPLETE)
400 return NULL;
401
402 if (period_len > TDMA_MAX_XFER_BYTES) {
403 dev_err(tdmac->dev,
404 "maximum period size exceeded: %d > %d\n",
405 period_len, TDMA_MAX_XFER_BYTES);
406 goto err_out;
407 }
408
409 tdmac->status = DMA_IN_PROGRESS;
410 tdmac->desc_num = num_periods;
411 desc = mmp_tdma_alloc_descriptor(tdmac);
412 if (!desc)
413 goto err_out;
414
415 while (buf < buf_len) {
416 desc = &tdmac->desc_arr[i];
417
418 if (i + 1 == num_periods)
419 desc->nxt_desc = tdmac->desc_arr_phys;
420 else
421 desc->nxt_desc = tdmac->desc_arr_phys +
422 sizeof(*desc) * (i + 1);
423
424 if (direction == DMA_MEM_TO_DEV) {
425 desc->src_addr = dma_addr;
426 desc->dst_addr = tdmac->dev_addr;
427 } else {
428 desc->src_addr = tdmac->dev_addr;
429 desc->dst_addr = dma_addr;
430 }
431 desc->byte_cnt = period_len;
432 dma_addr += period_len;
433 buf += period_len;
434 i++;
435 }
436
437 tdmac->buf_len = buf_len;
438 tdmac->period_len = period_len;
439 tdmac->pos = 0;
440
441 return &tdmac->desc;
442
443err_out:
444 tdmac->status = DMA_ERROR;
445 return NULL;
446}
447
448static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
449 unsigned long arg)
450{
451 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
452 struct dma_slave_config *dmaengine_cfg = (void *)arg;
453 int ret = 0;
454
455 switch (cmd) {
456 case DMA_TERMINATE_ALL:
457 mmp_tdma_disable_chan(tdmac);
458 break;
459 case DMA_PAUSE:
460 mmp_tdma_pause_chan(tdmac);
461 break;
462 case DMA_RESUME:
463 mmp_tdma_resume_chan(tdmac);
464 break;
465 case DMA_SLAVE_CONFIG:
466 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
467 tdmac->dev_addr = dmaengine_cfg->src_addr;
468 tdmac->burst_sz = dmaengine_cfg->src_maxburst;
469 tdmac->buswidth = dmaengine_cfg->src_addr_width;
470 } else {
471 tdmac->dev_addr = dmaengine_cfg->dst_addr;
472 tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
473 tdmac->buswidth = dmaengine_cfg->dst_addr_width;
474 }
475 tdmac->dir = dmaengine_cfg->direction;
476 return mmp_tdma_config_chan(tdmac);
477 default:
478 ret = -ENOSYS;
479 }
480
481 return ret;
482}
483
484static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
485 dma_cookie_t cookie, struct dma_tx_state *txstate)
486{
487 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
488
489 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
490 tdmac->buf_len - tdmac->pos);
491
492 return tdmac->status;
493}
494
495static void mmp_tdma_issue_pending(struct dma_chan *chan)
496{
497 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
498
499 mmp_tdma_enable_chan(tdmac);
500}
501
502static int mmp_tdma_remove(struct platform_device *pdev)
503{
504 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
505
506 dma_async_device_unregister(&tdev->device);
507 return 0;
508}
509
510static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
511 int idx, int irq,
512 int type, struct gen_pool *pool)
513{
514 struct mmp_tdma_chan *tdmac;
515
516 if (idx >= TDMA_CHANNEL_NUM) {
517 dev_err(tdev->dev, "too many channels for device!\n");
518 return -EINVAL;
519 }
520
521 /* alloc channel */
522 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
523 if (!tdmac) {
524 dev_err(tdev->dev, "no free memory for DMA channels!\n");
525 return -ENOMEM;
526 }
527 if (irq)
528 tdmac->irq = irq;
529 tdmac->dev = tdev->dev;
530 tdmac->chan.device = &tdev->device;
531 tdmac->idx = idx;
532 tdmac->type = type;
533 tdmac->reg_base = tdev->base + idx * 4;
534 tdmac->pool = pool;
535 tdmac->status = DMA_COMPLETE;
536 tdev->tdmac[tdmac->idx] = tdmac;
537 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
538
539 /* add the channel to tdma_chan list */
540 list_add_tail(&tdmac->chan.device_node,
541 &tdev->device.channels);
542 return 0;
543}
544
545struct mmp_tdma_filter_param {
546 struct device_node *of_node;
547 unsigned int chan_id;
548};
549
550static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
551{
552 struct mmp_tdma_filter_param *param = fn_param;
553 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
554 struct dma_device *pdma_device = tdmac->chan.device;
555
556 if (pdma_device->dev->of_node != param->of_node)
557 return false;
558
559 if (chan->chan_id != param->chan_id)
560 return false;
561
562 return true;
563}
564
565struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
566 struct of_dma *ofdma)
567{
568 struct mmp_tdma_device *tdev = ofdma->of_dma_data;
569 dma_cap_mask_t mask = tdev->device.cap_mask;
570 struct mmp_tdma_filter_param param;
571
572 if (dma_spec->args_count != 1)
573 return NULL;
574
575 param.of_node = ofdma->of_node;
576 param.chan_id = dma_spec->args[0];
577
578 if (param.chan_id >= TDMA_CHANNEL_NUM)
579 return NULL;
580
581 return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m);
582}
583
584static struct of_device_id mmp_tdma_dt_ids[] = {
585 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
586 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
587 {}
588};
589MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
590
591static int mmp_tdma_probe(struct platform_device *pdev)
592{
593 enum mmp_tdma_type type;
594 const struct of_device_id *of_id;
595 struct mmp_tdma_device *tdev;
596 struct resource *iores;
597 int i, ret;
598 int irq = 0, irq_num = 0;
599 int chan_num = TDMA_CHANNEL_NUM;
600 struct gen_pool *pool;
601
602 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
603 if (of_id)
604 type = (enum mmp_tdma_type) of_id->data;
605 else
606 type = platform_get_device_id(pdev)->driver_data;
607
608 /* always have couple channels */
609 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
610 if (!tdev)
611 return -ENOMEM;
612
613 tdev->dev = &pdev->dev;
614
615 for (i = 0; i < chan_num; i++) {
616 if (platform_get_irq(pdev, i) > 0)
617 irq_num++;
618 }
619
620 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
621 tdev->base = devm_ioremap_resource(&pdev->dev, iores);
622 if (IS_ERR(tdev->base))
623 return PTR_ERR(tdev->base);
624
625 INIT_LIST_HEAD(&tdev->device.channels);
626
627 if (pdev->dev.of_node)
628 pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0);
629 else
630 pool = sram_get_gpool("asram");
631 if (!pool) {
632 dev_err(&pdev->dev, "asram pool not available\n");
633 return -ENOMEM;
634 }
635
636 if (irq_num != chan_num) {
637 irq = platform_get_irq(pdev, 0);
638 ret = devm_request_irq(&pdev->dev, irq,
639 mmp_tdma_int_handler, 0, "tdma", tdev);
640 if (ret)
641 return ret;
642 }
643
644 /* initialize channel parameters */
645 for (i = 0; i < chan_num; i++) {
646 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
647 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
648 if (ret)
649 return ret;
650 }
651
652 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
653 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
654 tdev->device.dev = &pdev->dev;
655 tdev->device.device_alloc_chan_resources =
656 mmp_tdma_alloc_chan_resources;
657 tdev->device.device_free_chan_resources =
658 mmp_tdma_free_chan_resources;
659 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
660 tdev->device.device_tx_status = mmp_tdma_tx_status;
661 tdev->device.device_issue_pending = mmp_tdma_issue_pending;
662 tdev->device.device_control = mmp_tdma_control;
663 tdev->device.copy_align = TDMA_ALIGNMENT;
664
665 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
666 platform_set_drvdata(pdev, tdev);
667
668 ret = dma_async_device_register(&tdev->device);
669 if (ret) {
670 dev_err(tdev->device.dev, "unable to register\n");
671 return ret;
672 }
673
674 if (pdev->dev.of_node) {
675 ret = of_dma_controller_register(pdev->dev.of_node,
676 mmp_tdma_xlate, tdev);
677 if (ret) {
678 dev_err(tdev->device.dev,
679 "failed to register controller\n");
680 dma_async_device_unregister(&tdev->device);
681 }
682 }
683
684 dev_info(tdev->device.dev, "initialized\n");
685 return 0;
686}
687
688static const struct platform_device_id mmp_tdma_id_table[] = {
689 { "mmp-adma", MMP_AUD_TDMA },
690 { "pxa910-squ", PXA910_SQU },
691 { },
692};
693
694static struct platform_driver mmp_tdma_driver = {
695 .driver = {
696 .name = "mmp-tdma",
697 .owner = THIS_MODULE,
698 .of_match_table = mmp_tdma_dt_ids,
699 },
700 .id_table = mmp_tdma_id_table,
701 .probe = mmp_tdma_probe,
702 .remove = mmp_tdma_remove,
703};
704
705module_platform_driver(mmp_tdma_driver);
706
707MODULE_LICENSE("GPL");
708MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
709MODULE_ALIAS("platform:mmp-tdma");
710MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
711MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");