1/*
  2 *
  3 * Copyright (C) 2007 Google, Inc.
  4 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
  5 *
  6 * This software is licensed under the terms of the GNU General Public
  7 * License version 2, as published by the Free Software Foundation, and
  8 * may be copied, distributed, and modified under those terms.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 *
 15 */
 16
 17#include <linux/clocksource.h>
 18#include <linux/clockchips.h>
 19#include <linux/cpu.h>
 20#include <linux/init.h>
 21#include <linux/interrupt.h>
 22#include <linux/irq.h>
 23#include <linux/io.h>
 24#include <linux/of.h>
 25#include <linux/of_address.h>
 26#include <linux/of_irq.h>
 27#include <linux/sched_clock.h>
 28
 29#define TIMER_MATCH_VAL			0x0000
 30#define TIMER_COUNT_VAL			0x0004
 31#define TIMER_ENABLE			0x0008
 32#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
 33#define TIMER_ENABLE_EN			BIT(0)
 34#define TIMER_CLEAR			0x000C
 35#define DGT_CLK_CTL			0x10
 36#define DGT_CLK_CTL_DIV_4		0x3
 37#define TIMER_STS_GPT0_CLR_PEND		BIT(10)
 38
 39#define GPT_HZ 32768
 40
 41#define MSM_DGT_SHIFT 5
 42
 43static void __iomem *event_base;
 44static void __iomem *sts_base;
 45
 46static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 47{
 48	struct clock_event_device *evt = dev_id;
 49	/* Stop the timer tick */
 50	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
 51		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 52		ctrl &= ~TIMER_ENABLE_EN;
 53		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 54	}
 55	evt->event_handler(evt);
 56	return IRQ_HANDLED;
 57}
 58
 59static int msm_timer_set_next_event(unsigned long cycles,
 60				    struct clock_event_device *evt)
 61{
 62	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 63
 64	ctrl &= ~TIMER_ENABLE_EN;
 65	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 66
 67	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
 68	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
 69
 70	if (sts_base)
 71		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
 72			cpu_relax();
 73
 74	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
 75	return 0;
 76}
 77
 78static void msm_timer_set_mode(enum clock_event_mode mode,
 79			      struct clock_event_device *evt)
 80{
 81	u32 ctrl;
 82
 83	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 84	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
 85
 86	switch (mode) {
 87	case CLOCK_EVT_MODE_RESUME:
 88	case CLOCK_EVT_MODE_PERIODIC:
 89		break;
 90	case CLOCK_EVT_MODE_ONESHOT:
 91		/* Timer is enabled in set_next_event */
 92		break;
 93	case CLOCK_EVT_MODE_UNUSED:
 94	case CLOCK_EVT_MODE_SHUTDOWN:
 95		break;
 96	}
 97	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 98}
 99
100static struct clock_event_device __percpu *msm_evt;
101
102static void __iomem *source_base;
103
104static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
105{
106	return readl_relaxed(source_base + TIMER_COUNT_VAL);
107}
108
109static struct clocksource msm_clocksource = {
110	.name	= "dg_timer",
111	.rating	= 300,
112	.read	= msm_read_timer_count,
113	.mask	= CLOCKSOURCE_MASK(32),
114	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
115};
116
117static int msm_timer_irq;
118static int msm_timer_has_ppi;
119
120static int msm_local_timer_setup(struct clock_event_device *evt)
121{
122	int cpu = smp_processor_id();
123	int err;
124
125	evt->irq = msm_timer_irq;
126	evt->name = "msm_timer";
127	evt->features = CLOCK_EVT_FEAT_ONESHOT;
128	evt->rating = 200;
129	evt->set_mode = msm_timer_set_mode;
130	evt->set_next_event = msm_timer_set_next_event;
131	evt->cpumask = cpumask_of(cpu);
132
133	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
134
135	if (msm_timer_has_ppi) {
136		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
137	} else {
138		err = request_irq(evt->irq, msm_timer_interrupt,
139				IRQF_TIMER | IRQF_NOBALANCING |
140				IRQF_TRIGGER_RISING, "gp_timer", evt);
141		if (err)
142			pr_err("request_irq failed\n");
143	}
144
145	return 0;
146}
147
148static void msm_local_timer_stop(struct clock_event_device *evt)
149{
150	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
151	disable_percpu_irq(evt->irq);
152}
153
154static int msm_timer_cpu_notify(struct notifier_block *self,
155					   unsigned long action, void *hcpu)
156{
157	/*
158	 * Grab cpu pointer in each case to avoid spurious
159	 * preemptible warnings
160	 */
161	switch (action & ~CPU_TASKS_FROZEN) {
162	case CPU_STARTING:
163		msm_local_timer_setup(this_cpu_ptr(msm_evt));
164		break;
165	case CPU_DYING:
166		msm_local_timer_stop(this_cpu_ptr(msm_evt));
167		break;
168	}
169
170	return NOTIFY_OK;
171}
172
173static struct notifier_block msm_timer_cpu_nb = {
174	.notifier_call = msm_timer_cpu_notify,
175};
176
177static u64 notrace msm_sched_clock_read(void)
178{
179	return msm_clocksource.read(&msm_clocksource);
180}
181
182static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
183				  bool percpu)
184{
185	struct clocksource *cs = &msm_clocksource;
186	int res = 0;
187
188	msm_timer_irq = irq;
189	msm_timer_has_ppi = percpu;
190
191	msm_evt = alloc_percpu(struct clock_event_device);
192	if (!msm_evt) {
193		pr_err("memory allocation failed for clockevents\n");
194		goto err;
195	}
196
197	if (percpu)
198		res = request_percpu_irq(irq, msm_timer_interrupt,
199					 "gp_timer", msm_evt);
200
201	if (res) {
202		pr_err("request_percpu_irq failed\n");
203	} else {
204		res = register_cpu_notifier(&msm_timer_cpu_nb);
205		if (res) {
206			free_percpu_irq(irq, msm_evt);
207			goto err;
208		}
209
210		/* Immediately configure the timer on the boot CPU */
211		msm_local_timer_setup(__this_cpu_ptr(msm_evt));
212	}
213
214err:
215	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
216	res = clocksource_register_hz(cs, dgt_hz);
217	if (res)
218		pr_err("clocksource_register failed\n");
219	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
220}
221
222#ifdef CONFIG_ARCH_QCOM
223static void __init msm_dt_timer_init(struct device_node *np)
224{
225	u32 freq;
226	int irq;
227	struct resource res;
228	u32 percpu_offset;
229	void __iomem *base;
230	void __iomem *cpu0_base;
231
232	base = of_iomap(np, 0);
233	if (!base) {
234		pr_err("Failed to map event base\n");
235		return;
236	}
237
238	/* We use GPT0 for the clockevent */
239	irq = irq_of_parse_and_map(np, 1);
240	if (irq <= 0) {
241		pr_err("Can't get irq\n");
242		return;
243	}
244
245	/* We use CPU0's DGT for the clocksource */
246	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
247		percpu_offset = 0;
248
249	if (of_address_to_resource(np, 0, &res)) {
250		pr_err("Failed to parse DGT resource\n");
251		return;
252	}
253
254	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
255	if (!cpu0_base) {
256		pr_err("Failed to map source base\n");
257		return;
258	}
259
260	if (of_property_read_u32(np, "clock-frequency", &freq)) {
261		pr_err("Unknown frequency\n");
262		return;
263	}
264
265	event_base = base + 0x4;
266	sts_base = base + 0x88;
267	source_base = cpu0_base + 0x24;
268	freq /= 4;
269	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
270
271	msm_timer_init(freq, 32, irq, !!percpu_offset);
272}
273CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
274CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
275#else
276
277static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
278				u32 sts)
279{
280	void __iomem *base;
281
282	base = ioremap(addr, SZ_256);
283	if (!base) {
284		pr_err("Failed to map timer base\n");
285		return -ENOMEM;
286	}
287	event_base = base + event;
288	source_base = base + source;
289	if (sts)
290		sts_base = base + sts;
291
292	return 0;
293}
294
295static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
296{
297	/*
298	 * Shift timer count down by a constant due to unreliable lower bits
299	 * on some targets.
300	 */
301	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
302}
303
304void __init msm7x01_timer_init(void)
305{
306	struct clocksource *cs = &msm_clocksource;
307
308	if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
309		return;
310	cs->read = msm_read_timer_count_shift;
311	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
312	/* 600 KHz */
313	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
314			false);
315}
316
317void __init msm7x30_timer_init(void)
318{
319	if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
320		return;
321	msm_timer_init(24576000 / 4, 32, 1, false);
322}
323
324void __init qsd8x50_timer_init(void)
325{
326	if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
327		return;
328	msm_timer_init(19200000 / 4, 32, 7, false);
329}
330#endif