Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DaVinci DA850 AHCI SATA platform driver
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/pm.h>
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/libata.h>
12#include <linux/ahci_platform.h>
13#include "ahci.h"
14
15#define DRV_NAME "ahci_da850"
16#define HARDRESET_RETRIES 5
17
18/* SATA PHY Control Register offset from AHCI base */
19#define SATA_P0PHYCR_REG 0x178
20
21#define SATA_PHY_MPY(x) ((x) << 0)
22#define SATA_PHY_LOS(x) ((x) << 6)
23#define SATA_PHY_RXCDR(x) ((x) << 10)
24#define SATA_PHY_RXEQ(x) ((x) << 13)
25#define SATA_PHY_TXSWING(x) ((x) << 19)
26#define SATA_PHY_ENPLL(x) ((x) << 31)
27
28static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
29 void __iomem *ahci_base, u32 mpy)
30{
31 unsigned int val;
32
33 /* Enable SATA clock receiver */
34 val = readl(pwrdn_reg);
35 val &= ~BIT(0);
36 writel(val, pwrdn_reg);
37
38 val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
39 SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
40
41 writel(val, ahci_base + SATA_P0PHYCR_REG);
42}
43
44static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
45{
46 u32 pll_output = 1500000000, needed;
47
48 /*
49 * We need to determine the value of the multiplier (MPY) bits.
50 * In order to include the 12.5 multiplier we need to first divide
51 * the refclk rate by ten.
52 *
53 * __div64_32() turned out to be unreliable, sometimes returning
54 * false results.
55 */
56 WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
57 needed = pll_output / (refclk_rate / 10);
58
59 /*
60 * What we have now is (multiplier * 10).
61 *
62 * Let's determine the actual register value we need to write.
63 */
64
65 switch (needed) {
66 case 50:
67 return 0x1;
68 case 60:
69 return 0x2;
70 case 80:
71 return 0x4;
72 case 100:
73 return 0x5;
74 case 120:
75 return 0x6;
76 case 125:
77 return 0x7;
78 case 150:
79 return 0x8;
80 case 200:
81 return 0x9;
82 case 250:
83 return 0xa;
84 default:
85 /*
86 * We should have divided evenly - if not, return an invalid
87 * value.
88 */
89 return 0;
90 }
91}
92
93static int ahci_da850_softreset(struct ata_link *link,
94 unsigned int *class, unsigned long deadline)
95{
96 int pmp, ret;
97
98 pmp = sata_srst_pmp(link);
99
100 /*
101 * There's an issue with the SATA controller on da850 SoCs: if we
102 * enable Port Multiplier support, but the drive is connected directly
103 * to the board, it can't be detected. As a workaround: if PMP is
104 * enabled, we first call ahci_do_softreset() and pass it the result of
105 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
106 */
107 ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
108 if (pmp && ret == -EBUSY)
109 return ahci_do_softreset(link, class, 0,
110 deadline, ahci_check_ready);
111
112 return ret;
113}
114
115static int ahci_da850_hardreset(struct ata_link *link,
116 unsigned int *class, unsigned long deadline)
117{
118 int ret, retry = HARDRESET_RETRIES;
119 bool online;
120
121 /*
122 * In order to correctly service the LCD controller of the da850 SoC,
123 * we increased the PLL0 frequency to 456MHz from the default 300MHz.
124 *
125 * This made the SATA controller unstable and the hardreset operation
126 * does not always succeed the first time. Before really giving up to
127 * bring up the link, retry the reset a couple times.
128 */
129 do {
130 ret = ahci_do_hardreset(link, class, deadline, &online);
131 if (online)
132 return ret;
133 } while (retry--);
134
135 return ret;
136}
137
138static struct ata_port_operations ahci_da850_port_ops = {
139 .inherits = &ahci_platform_ops,
140 .softreset = ahci_da850_softreset,
141 /*
142 * No need to override .pmp_softreset - it's only used for actual
143 * PMP-enabled ports.
144 */
145 .hardreset = ahci_da850_hardreset,
146 .pmp_hardreset = ahci_da850_hardreset,
147};
148
149static const struct ata_port_info ahci_da850_port_info = {
150 .flags = AHCI_FLAG_COMMON,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_da850_port_ops,
154};
155
156static const struct scsi_host_template ahci_platform_sht = {
157 AHCI_SHT(DRV_NAME),
158};
159
160static int ahci_da850_probe(struct platform_device *pdev)
161{
162 struct device *dev = &pdev->dev;
163 struct ahci_host_priv *hpriv;
164 void __iomem *pwrdn_reg;
165 struct resource *res;
166 u32 mpy;
167 int rc;
168
169 hpriv = ahci_platform_get_resources(pdev, 0);
170 if (IS_ERR(hpriv))
171 return PTR_ERR(hpriv);
172
173 /*
174 * Internally ahci_platform_get_resources() calls the bulk clocks
175 * get method or falls back to using a single clk_get_optional().
176 * This AHCI SATA controller uses two clocks: functional clock
177 * with "fck" connection id and external reference clock with
178 * "refclk" id. If we haven't got all of them re-try the clocks
179 * getting procedure with the explicitly specified ids.
180 */
181 if (hpriv->n_clks < 2) {
182 hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
183 if (!hpriv->clks)
184 return -ENOMEM;
185
186 hpriv->clks[0].id = "fck";
187 hpriv->clks[1].id = "refclk";
188 hpriv->n_clks = 2;
189
190 rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
191 if (rc)
192 return rc;
193 }
194
195 mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
196 if (mpy == 0) {
197 dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
198 return -EINVAL;
199 }
200
201 rc = ahci_platform_enable_resources(hpriv);
202 if (rc)
203 return rc;
204
205 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
206 if (!res) {
207 rc = -ENODEV;
208 goto disable_resources;
209 }
210
211 pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
212 if (!pwrdn_reg) {
213 rc = -ENOMEM;
214 goto disable_resources;
215 }
216
217 da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
218
219 rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
220 &ahci_platform_sht);
221 if (rc)
222 goto disable_resources;
223
224 return 0;
225disable_resources:
226 ahci_platform_disable_resources(hpriv);
227 return rc;
228}
229
230static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
231 ahci_platform_resume);
232
233static const struct of_device_id ahci_da850_of_match[] = {
234 { .compatible = "ti,da850-ahci", },
235 { /* sentinel */ }
236};
237MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
238
239static struct platform_driver ahci_da850_driver = {
240 .probe = ahci_da850_probe,
241 .remove_new = ata_platform_remove_one,
242 .driver = {
243 .name = DRV_NAME,
244 .of_match_table = ahci_da850_of_match,
245 .pm = &ahci_da850_pm_ops,
246 },
247};
248module_platform_driver(ahci_da850_driver);
249
250MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
251MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
252MODULE_LICENSE("GPL");
1/*
2 * DaVinci DA850 AHCI SATA platform driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2, or (at your option)
7 * any later version.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pm.h>
13#include <linux/device.h>
14#include <linux/platform_device.h>
15#include <linux/libata.h>
16#include <linux/ahci_platform.h>
17#include "ahci.h"
18
19/* SATA PHY Control Register offset from AHCI base */
20#define SATA_P0PHYCR_REG 0x178
21
22#define SATA_PHY_MPY(x) ((x) << 0)
23#define SATA_PHY_LOS(x) ((x) << 6)
24#define SATA_PHY_RXCDR(x) ((x) << 10)
25#define SATA_PHY_RXEQ(x) ((x) << 13)
26#define SATA_PHY_TXSWING(x) ((x) << 19)
27#define SATA_PHY_ENPLL(x) ((x) << 31)
28
29/*
30 * The multiplier needed for 1.5GHz PLL output.
31 *
32 * NOTE: This is currently hardcoded to be suitable for 100MHz crystal
33 * frequency (which is used by DA850 EVM board) and may need to be changed
34 * if you would like to use this driver on some other board.
35 */
36#define DA850_SATA_CLK_MULTIPLIER 7
37
38static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
39 void __iomem *ahci_base)
40{
41 unsigned int val;
42
43 /* Enable SATA clock receiver */
44 val = readl(pwrdn_reg);
45 val &= ~BIT(0);
46 writel(val, pwrdn_reg);
47
48 val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) |
49 SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) |
50 SATA_PHY_ENPLL(1);
51
52 writel(val, ahci_base + SATA_P0PHYCR_REG);
53}
54
55static const struct ata_port_info ahci_da850_port_info = {
56 .flags = AHCI_FLAG_COMMON,
57 .pio_mask = ATA_PIO4,
58 .udma_mask = ATA_UDMA6,
59 .port_ops = &ahci_platform_ops,
60};
61
62static int ahci_da850_probe(struct platform_device *pdev)
63{
64 struct device *dev = &pdev->dev;
65 struct ahci_host_priv *hpriv;
66 struct resource *res;
67 void __iomem *pwrdn_reg;
68 int rc;
69
70 hpriv = ahci_platform_get_resources(pdev);
71 if (IS_ERR(hpriv))
72 return PTR_ERR(hpriv);
73
74 rc = ahci_platform_enable_resources(hpriv);
75 if (rc)
76 return rc;
77
78 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
79 if (!res)
80 goto disable_resources;
81
82 pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
83 if (!pwrdn_reg)
84 goto disable_resources;
85
86 da850_sata_init(dev, pwrdn_reg, hpriv->mmio);
87
88 rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info, 0, 0);
89 if (rc)
90 goto disable_resources;
91
92 return 0;
93disable_resources:
94 ahci_platform_disable_resources(hpriv);
95 return rc;
96}
97
98static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
99 ahci_platform_resume);
100
101static struct platform_driver ahci_da850_driver = {
102 .probe = ahci_da850_probe,
103 .remove = ata_platform_remove_one,
104 .driver = {
105 .name = "ahci_da850",
106 .owner = THIS_MODULE,
107 .pm = &ahci_da850_pm_ops,
108 },
109};
110module_platform_driver(ahci_da850_driver);
111
112MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
113MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
114MODULE_LICENSE("GPL");