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v6.8
 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright IBM Corp. 1999, 2010
 4 *
 5 *   Author(s):	Hartmut Penner <hp@de.ibm.com>
 6 *		Martin Schwidefsky <schwidefsky@de.ibm.com>
 7 *		Rob van der Heij <rvdhei@iae.nl>
 
 8 *
 9 */
10
11#include <linux/init.h>
12#include <linux/linkage.h>
13#include <asm/asm-offsets.h>
14#include <asm/thread_info.h>
15#include <asm/page.h>
16#include <asm/ptrace.h>
17
18__HEAD
19SYM_CODE_START(startup_continue)
20	larl	%r1,tod_clock_base
21	mvc	0(16,%r1),__LC_BOOT_CLOCK
 
 
 
 
 
 
22#
23# Setup stack
24#
25	larl	%r14,init_task
 
 
26	stg	%r14,__LC_CURRENT
27	larl	%r15,init_thread_union+STACK_INIT_OFFSET
28	stg	%r15,__LC_KERNEL_STACK
29	brasl	%r14,sclp_early_adjust_va	# allow sclp_early_printk
30	brasl	%r14,startup_init		# s390 specific early init
31	brasl	%r14,start_kernel		# common init code
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
32#
33# We returned from start_kernel ?!? PANIK
34#
35	basr	%r13,0
36	lpswe	dw_psw-.(%r13)		# load disabled wait psw
37SYM_CODE_END(startup_continue)
38
39	.balign	16
40SYM_DATA_LOCAL(dw_psw,	.quad 0x0002000180000000,0x0000000000000000)
 
v3.15
 
  1/*
  2 * Copyright IBM Corp. 1999, 2010
  3 *
  4 *   Author(s):	Hartmut Penner <hp@de.ibm.com>
  5 *		Martin Schwidefsky <schwidefsky@de.ibm.com>
  6 *		Rob van der Heij <rvdhei@iae.nl>
  7 *		Heiko Carstens <heiko.carstens@de.ibm.com>
  8 *
  9 */
 10
 11#include <linux/init.h>
 12#include <linux/linkage.h>
 13#include <asm/asm-offsets.h>
 14#include <asm/thread_info.h>
 15#include <asm/page.h>
 
 16
 17__HEAD
 18ENTRY(startup_continue)
 19	larl	%r1,sched_clock_base_cc
 20	mvc	0(8,%r1),__LC_LAST_UPDATE_CLOCK
 21	larl	%r13,.LPG1		# get base
 22	lctlg	%c0,%c15,.Lctl-.LPG1(%r13)	# load control registers
 23	lg	%r12,.Lparmaddr-.LPG1(%r13)	# pointer to parameter area
 24					# move IPL device to lowcore
 25	lghi	%r0,__LC_PASTE
 26	stg	%r0,__LC_VDSO_PER_CPU
 27#
 28# Setup stack
 29#
 30	larl	%r15,init_thread_union
 31	stg	%r15,__LC_THREAD_INFO	# cache thread info in lowcore
 32	lg	%r14,__TI_task(%r15)	# cache current in lowcore
 33	stg	%r14,__LC_CURRENT
 34	aghi	%r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
 35	stg	%r15,__LC_KERNEL_STACK	# set end of kernel stack
 36	aghi	%r15,-160
 37#
 38# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
 39# and create a kernel NSS if the SAVESYS= parm is defined
 40#
 41	brasl	%r14,startup_init
 42	lpswe	.Lentry-.LPG1(13)	# jump to _stext in primary-space,
 43					# virtual and never return ...
 44	.align	16
 45.LPG1:
 46.Lentry:.quad	0x0000000180000000,_stext
 47.Lctl:	.quad	0x04040000		# cr0: AFP registers & secondary space
 48	.quad	0			# cr1: primary space segment table
 49	.quad	.Lduct			# cr2: dispatchable unit control table
 50	.quad	0			# cr3: instruction authorization
 51	.quad	0			# cr4: instruction authorization
 52	.quad	.Lduct			# cr5: primary-aste origin
 53	.quad	0			# cr6:	I/O interrupts
 54	.quad	0			# cr7:	secondary space segment table
 55	.quad	0			# cr8:	access registers translation
 56	.quad	0			# cr9:	tracing off
 57	.quad	0			# cr10: tracing off
 58	.quad	0			# cr11: tracing off
 59	.quad	0			# cr12: tracing off
 60	.quad	0			# cr13: home space segment table
 61	.quad	0xc0000000		# cr14: machine check handling off
 62	.quad	.Llinkage_stack		# cr15: linkage stack operations
 63.Lpcmsk:.quad	0x0000000180000000
 64.L4malign:.quad 0xffffffffffc00000
 65.Lscan2g:.quad	0x80000000 + 0x20000 - 8	# 2GB + 128K - 8
 66.Lnop:	.long	0x07000700
 67.Lparmaddr:
 68	.quad	PARMAREA
 69	.align	64
 70.Lduct: .long	0,.Laste,.Laste,0,.Lduald,0,0,0
 71	.long	0,0,0,0,0,0,0,0
 72.Laste:	.quad	0,0xffffffffffffffff,0,0,0,0,0,0
 73	.align	128
 74.Lduald:.rept	8
 75	.long	0x80000000,0,0,0	# invalid access-list entries
 76	.endr
 77.Llinkage_stack:
 78	.long	0,0,0x89000000,0,0,0,0x8a000000,0
 79
 80ENTRY(_ehead)
 81
 82	.org	0x100000 - 0x11000	# head.o ends at 0x11000
 83#
 84# startup-code, running in absolute addressing mode
 85#
 86ENTRY(_stext)
 87	basr	%r13,0			# get base
 88.LPG3:
 89# check control registers
 90	stctg	%c0,%c15,0(%r15)
 91	oi	6(%r15),0x60		# enable sigp emergency & external call
 92	oi	4(%r15),0x10		# switch on low address proctection
 93	lctlg	%c0,%c15,0(%r15)
 94
 95	lam	0,15,.Laregs-.LPG3(%r13)	# load acrs needed by uaccess
 96	brasl	%r14,start_kernel	# go to C code
 97#
 98# We returned from start_kernel ?!? PANIK
 99#
100	basr	%r13,0
101	lpswe	.Ldw-.(%r13)		# load disabled wait psw
 
102
103	.align	8
104.Ldw:	.quad	0x0002000180000000,0x0000000000000000
105.Laregs:.long	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0