1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * ICS backend for OPAL managed interrupts.
  4 *
  5 * Copyright 2011 IBM Corp.
 
 
 
 
 
  6 */
  7
  8#undef DEBUG
  9
 10#include <linux/types.h>
 11#include <linux/kernel.h>
 12#include <linux/irq.h>
 13#include <linux/smp.h>
 14#include <linux/interrupt.h>
 15#include <linux/init.h>
 16#include <linux/cpu.h>
 17#include <linux/of.h>
 18#include <linux/spinlock.h>
 19#include <linux/msi.h>
 20
 
 21#include <asm/smp.h>
 22#include <asm/machdep.h>
 23#include <asm/irq.h>
 24#include <asm/errno.h>
 25#include <asm/xics.h>
 26#include <asm/opal.h>
 27#include <asm/firmware.h>
 28
 29static int ics_opal_mangle_server(int server)
 30{
 31	/* No link for now */
 32	return server << 2;
 33}
 34
 35static int ics_opal_unmangle_server(int server)
 36{
 37	/* No link for now */
 38	return server >> 2;
 39}
 40
 41static void ics_opal_unmask_irq(struct irq_data *d)
 42{
 43	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 44	int64_t rc;
 45	int server;
 46
 47	pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 48
 49	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 50		return;
 51
 52	server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
 53	server = ics_opal_mangle_server(server);
 54
 55	rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
 56	if (rc != OPAL_SUCCESS)
 57		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
 58		       " error %lld\n",
 59		       __func__, d->irq, hw_irq, server, rc);
 60}
 61
 62static unsigned int ics_opal_startup(struct irq_data *d)
 63{
 
 
 
 
 
 
 
 
 
 
 
 64	ics_opal_unmask_irq(d);
 65	return 0;
 66}
 67
 68static void ics_opal_mask_real_irq(unsigned int hw_irq)
 69{
 70	int server = ics_opal_mangle_server(xics_default_server);
 71	int64_t rc;
 72
 73	if (hw_irq == XICS_IPI)
 74		return;
 75
 76	/* Have to set XIVE to 0xff to be able to remove a slot */
 77	rc = opal_set_xive(hw_irq, server, 0xff);
 78	if (rc != OPAL_SUCCESS)
 79		pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
 80		       __func__, hw_irq, rc);
 81}
 82
 83static void ics_opal_mask_irq(struct irq_data *d)
 84{
 85	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 86
 87	pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 88
 89	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 90		return;
 91	ics_opal_mask_real_irq(hw_irq);
 92}
 93
 94static int ics_opal_set_affinity(struct irq_data *d,
 95				 const struct cpumask *cpumask,
 96				 bool force)
 97{
 98	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 99	__be16 oserver;
100	int16_t server;
101	int8_t priority;
102	int64_t rc;
103	int wanted_server;
104
105	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
106		return -1;
107
108	rc = opal_get_xive(hw_irq, &oserver, &priority);
109	if (rc != OPAL_SUCCESS) {
110		pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
111		       __func__, d->irq, hw_irq, rc);
112		return -1;
113	}
 
114
115	wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
116	if (wanted_server < 0) {
117		pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
118			__func__, cpumask_pr_args(cpumask), d->irq);
 
 
119		return -1;
120	}
121	server = ics_opal_mangle_server(wanted_server);
122
123	pr_debug("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
124		 d->irq, hw_irq, wanted_server, server);
125
126	rc = opal_set_xive(hw_irq, server, priority);
127	if (rc != OPAL_SUCCESS) {
128		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
129		       " error %lld\n",
130		       __func__, d->irq, hw_irq, server, rc);
131		return -1;
132	}
133	return IRQ_SET_MASK_OK;
134}
135
136static struct irq_chip ics_opal_irq_chip = {
137	.name = "OPAL ICS",
138	.irq_startup = ics_opal_startup,
139	.irq_mask = ics_opal_mask_irq,
140	.irq_unmask = ics_opal_unmask_irq,
141	.irq_eoi = NULL, /* Patched at init time */
142	.irq_set_affinity = ics_opal_set_affinity,
143	.irq_set_type = xics_set_irq_type,
144	.irq_retrigger = xics_retrigger,
145};
146
 
 
 
 
147static int ics_opal_host_match(struct ics *ics, struct device_node *node)
148{
149	return 1;
150}
151
152static int ics_opal_check(struct ics *ics, unsigned int hw_irq)
 
 
 
 
 
 
 
 
153{
 
154	int64_t rc;
155	__be16 server;
156	int8_t priority;
157
158	if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
159		return -EINVAL;
160
161	/* Check if HAL knows about this interrupt */
162	rc = opal_get_xive(hw_irq, &server, &priority);
163	if (rc != OPAL_SUCCESS)
164		return -ENXIO;
165
 
 
 
166	return 0;
167}
168
169static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
170{
171	int64_t rc;
172	__be16 server;
173	int8_t priority;
174
175	/* Check if HAL knows about this interrupt */
176	rc = opal_get_xive(vec, &server, &priority);
177	if (rc != OPAL_SUCCESS)
178		return;
179
180	ics_opal_mask_real_irq(vec);
181}
182
183static long ics_opal_get_server(struct ics *ics, unsigned long vec)
184{
185	int64_t rc;
186	__be16 server;
187	int8_t priority;
188
189	/* Check if HAL knows about this interrupt */
190	rc = opal_get_xive(vec, &server, &priority);
191	if (rc != OPAL_SUCCESS)
192		return -1;
193	return ics_opal_unmangle_server(be16_to_cpu(server));
194}
195
196/* Only one global & state struct ics */
197static struct ics ics_hal = {
198	.check		= ics_opal_check,
199	.mask_unknown	= ics_opal_mask_unknown,
200	.get_server	= ics_opal_get_server,
201	.host_match	= ics_opal_host_match,
202	.chip		= &ics_opal_irq_chip,
203};
204
205int __init ics_opal_init(void)
206{
207	if (!firmware_has_feature(FW_FEATURE_OPAL))
208		return -ENODEV;
209
210	/* We need to patch our irq chip's EOI to point to the
211	 * right ICP
212	 */
213	ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
214
215	/* Register ourselves */
216	xics_register_ics(&ics_hal);
217
218	pr_info("ICS OPAL backend registered\n");
219
220	return 0;
221}

 
  1/*
  2 * ICS backend for OPAL managed interrupts.
  3 *
  4 * Copyright 2011 IBM Corp.
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License
  8 * as published by the Free Software Foundation; either version
  9 * 2 of the License, or (at your option) any later version.
 10 */
 11
 12#undef DEBUG
 13
 14#include <linux/types.h>
 15#include <linux/kernel.h>
 16#include <linux/irq.h>
 17#include <linux/smp.h>
 18#include <linux/interrupt.h>
 19#include <linux/init.h>
 20#include <linux/cpu.h>
 21#include <linux/of.h>
 22#include <linux/spinlock.h>
 23#include <linux/msi.h>
 24
 25#include <asm/prom.h>
 26#include <asm/smp.h>
 27#include <asm/machdep.h>
 28#include <asm/irq.h>
 29#include <asm/errno.h>
 30#include <asm/xics.h>
 31#include <asm/opal.h>
 32#include <asm/firmware.h>
 33
 34static int ics_opal_mangle_server(int server)
 35{
 36	/* No link for now */
 37	return server << 2;
 38}
 39
 40static int ics_opal_unmangle_server(int server)
 41{
 42	/* No link for now */
 43	return server >> 2;
 44}
 45
 46static void ics_opal_unmask_irq(struct irq_data *d)
 47{
 48	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 49	int64_t rc;
 50	int server;
 51
 52	pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
 53
 54	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
 55		return;
 56
 57	server = xics_get_irq_server(d->irq, d->affinity, 0);
 58	server = ics_opal_mangle_server(server);
 59
 60	rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
 61	if (rc != OPAL_SUCCESS)
 62		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
 63		       " error %lld\n",
 64		       __func__, d->irq, hw_irq, server, rc);
 65}
 66
 67static unsigned int ics_opal_startup(struct irq_data *d)
 68{
 69#ifdef CONFIG_PCI_MSI
 70	/*
 71	 * The generic MSI code returns with the interrupt disabled on the
 72	 * card, using the MSI mask bits. Firmware doesn't appear to unmask
 73	 * at that level, so we do it here by hand.
 74	 */
 75	if (d->msi_desc)
 76		unmask_msi_irq(d);
 77#endif
 78
 79	/* unmask it */
 80	ics_opal_unmask_irq(d);
 81	return 0;
 82}
 83
 84static void ics_opal_mask_real_irq(unsigned int hw_irq)
 85{
 86	int server = ics_opal_mangle_server(xics_default_server);
 87	int64_t rc;
 88
 89	if (hw_irq == XICS_IPI)
 90		return;
 91
 92	/* Have to set XIVE to 0xff to be able to remove a slot */
 93	rc = opal_set_xive(hw_irq, server, 0xff);
 94	if (rc != OPAL_SUCCESS)
 95		pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
 96		       __func__, hw_irq, rc);
 97}
 98
 99static void ics_opal_mask_irq(struct irq_data *d)
100{
101	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
102
103	pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
104
105	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
106		return;
107	ics_opal_mask_real_irq(hw_irq);
108}
109
110static int ics_opal_set_affinity(struct irq_data *d,
111				 const struct cpumask *cpumask,
112				 bool force)
113{
114	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
115	__be16 oserver;
116	int16_t server;
117	int8_t priority;
118	int64_t rc;
119	int wanted_server;
120
121	if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
122		return -1;
123
124	rc = opal_get_xive(hw_irq, &oserver, &priority);
125	if (rc != OPAL_SUCCESS) {
126		pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
127		       __func__, d->irq, hw_irq, rc);
128		return -1;
129	}
130	server = be16_to_cpu(oserver);
131
132	wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
133	if (wanted_server < 0) {
134		char cpulist[128];
135		cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
136		pr_warning("%s: No online cpus in the mask %s for irq %d\n",
137			   __func__, cpulist, d->irq);
138		return -1;
139	}
140	server = ics_opal_mangle_server(wanted_server);
141
142	pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
143		 d->irq, hw_irq, wanted_server, server);
144
145	rc = opal_set_xive(hw_irq, server, priority);
146	if (rc != OPAL_SUCCESS) {
147		pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
148		       " error %lld\n",
149		       __func__, d->irq, hw_irq, server, rc);
150		return -1;
151	}
152	return IRQ_SET_MASK_OK;
153}
154
155static struct irq_chip ics_opal_irq_chip = {
156	.name = "OPAL ICS",
157	.irq_startup = ics_opal_startup,
158	.irq_mask = ics_opal_mask_irq,
159	.irq_unmask = ics_opal_unmask_irq,
160	.irq_eoi = NULL, /* Patched at init time */
161	.irq_set_affinity = ics_opal_set_affinity
 
 
162};
163
164static int ics_opal_map(struct ics *ics, unsigned int virq);
165static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
166static long ics_opal_get_server(struct ics *ics, unsigned long vec);
167
168static int ics_opal_host_match(struct ics *ics, struct device_node *node)
169{
170	return 1;
171}
172
173/* Only one global & state struct ics */
174static struct ics ics_hal = {
175	.map		= ics_opal_map,
176	.mask_unknown	= ics_opal_mask_unknown,
177	.get_server	= ics_opal_get_server,
178	.host_match	= ics_opal_host_match,
179};
180
181static int ics_opal_map(struct ics *ics, unsigned int virq)
182{
183	unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
184	int64_t rc;
185	__be16 server;
186	int8_t priority;
187
188	if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
189		return -EINVAL;
190
191	/* Check if HAL knows about this interrupt */
192	rc = opal_get_xive(hw_irq, &server, &priority);
193	if (rc != OPAL_SUCCESS)
194		return -ENXIO;
195
196	irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
197	irq_set_chip_data(virq, &ics_hal);
198
199	return 0;
200}
201
202static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
203{
204	int64_t rc;
205	__be16 server;
206	int8_t priority;
207
208	/* Check if HAL knows about this interrupt */
209	rc = opal_get_xive(vec, &server, &priority);
210	if (rc != OPAL_SUCCESS)
211		return;
212
213	ics_opal_mask_real_irq(vec);
214}
215
216static long ics_opal_get_server(struct ics *ics, unsigned long vec)
217{
218	int64_t rc;
219	__be16 server;
220	int8_t priority;
221
222	/* Check if HAL knows about this interrupt */
223	rc = opal_get_xive(vec, &server, &priority);
224	if (rc != OPAL_SUCCESS)
225		return -1;
226	return ics_opal_unmangle_server(be16_to_cpu(server));
227}
 
 
 
 
 
 
 
 
 
228
229int __init ics_opal_init(void)
230{
231	if (!firmware_has_feature(FW_FEATURE_OPAL))
232		return -ENODEV;
233
234	/* We need to patch our irq chip's EOI to point to the
235	 * right ICP
236	 */
237	ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
238
239	/* Register ourselves */
240	xics_register_ics(&ics_hal);
241
242	pr_info("ICS OPAL backend registered\n");
243
244	return 0;
245}