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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 *
5 * Rewrite, cleanup, new allocation schemes, virtual merging:
6 * Copyright (C) 2004 Olof Johansson, IBM Corporation
7 * and Ben. Herrenschmidt, IBM Corporation
8 *
9 * Dynamic DMA mapping support, bus-independent parts.
10 */
11
12
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/slab.h>
16#include <linux/mm.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/bitmap.h>
21#include <linux/iommu-helper.h>
22#include <linux/crash_dump.h>
23#include <linux/hash.h>
24#include <linux/fault-inject.h>
25#include <linux/pci.h>
26#include <linux/iommu.h>
27#include <linux/sched.h>
28#include <linux/debugfs.h>
29#include <asm/io.h>
30#include <asm/iommu.h>
31#include <asm/pci-bridge.h>
32#include <asm/machdep.h>
33#include <asm/kdump.h>
34#include <asm/fadump.h>
35#include <asm/vio.h>
36#include <asm/tce.h>
37#include <asm/mmu_context.h>
38#include <asm/ppc-pci.h>
39
40#define DBG(...)
41
42#ifdef CONFIG_IOMMU_DEBUGFS
43static int iommu_debugfs_weight_get(void *data, u64 *val)
44{
45 struct iommu_table *tbl = data;
46 *val = bitmap_weight(tbl->it_map, tbl->it_size);
47 return 0;
48}
49DEFINE_DEBUGFS_ATTRIBUTE(iommu_debugfs_fops_weight, iommu_debugfs_weight_get, NULL, "%llu\n");
50
51static void iommu_debugfs_add(struct iommu_table *tbl)
52{
53 char name[10];
54 struct dentry *liobn_entry;
55
56 sprintf(name, "%08lx", tbl->it_index);
57 liobn_entry = debugfs_create_dir(name, iommu_debugfs_dir);
58
59 debugfs_create_file_unsafe("weight", 0400, liobn_entry, tbl, &iommu_debugfs_fops_weight);
60 debugfs_create_ulong("it_size", 0400, liobn_entry, &tbl->it_size);
61 debugfs_create_ulong("it_page_shift", 0400, liobn_entry, &tbl->it_page_shift);
62 debugfs_create_ulong("it_reserved_start", 0400, liobn_entry, &tbl->it_reserved_start);
63 debugfs_create_ulong("it_reserved_end", 0400, liobn_entry, &tbl->it_reserved_end);
64 debugfs_create_ulong("it_indirect_levels", 0400, liobn_entry, &tbl->it_indirect_levels);
65 debugfs_create_ulong("it_level_size", 0400, liobn_entry, &tbl->it_level_size);
66}
67
68static void iommu_debugfs_del(struct iommu_table *tbl)
69{
70 char name[10];
71
72 sprintf(name, "%08lx", tbl->it_index);
73 debugfs_lookup_and_remove(name, iommu_debugfs_dir);
74}
75#else
76static void iommu_debugfs_add(struct iommu_table *tbl){}
77static void iommu_debugfs_del(struct iommu_table *tbl){}
78#endif
79
80static int novmerge;
81
82static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
83
84static int __init setup_iommu(char *str)
85{
86 if (!strcmp(str, "novmerge"))
87 novmerge = 1;
88 else if (!strcmp(str, "vmerge"))
89 novmerge = 0;
90 return 1;
91}
92
93__setup("iommu=", setup_iommu);
94
95static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
96
97/*
98 * We precalculate the hash to avoid doing it on every allocation.
99 *
100 * The hash is important to spread CPUs across all the pools. For example,
101 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
102 * with 4 pools all primary threads would map to the same pool.
103 */
104static int __init setup_iommu_pool_hash(void)
105{
106 unsigned int i;
107
108 for_each_possible_cpu(i)
109 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
110
111 return 0;
112}
113subsys_initcall(setup_iommu_pool_hash);
114
115#ifdef CONFIG_FAIL_IOMMU
116
117static DECLARE_FAULT_ATTR(fail_iommu);
118
119static int __init setup_fail_iommu(char *str)
120{
121 return setup_fault_attr(&fail_iommu, str);
122}
123__setup("fail_iommu=", setup_fail_iommu);
124
125static bool should_fail_iommu(struct device *dev)
126{
127 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
128}
129
130static int __init fail_iommu_debugfs(void)
131{
132 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
133 NULL, &fail_iommu);
134
135 return PTR_ERR_OR_ZERO(dir);
136}
137late_initcall(fail_iommu_debugfs);
138
139static ssize_t fail_iommu_show(struct device *dev,
140 struct device_attribute *attr, char *buf)
141{
142 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
143}
144
145static ssize_t fail_iommu_store(struct device *dev,
146 struct device_attribute *attr, const char *buf,
147 size_t count)
148{
149 int i;
150
151 if (count > 0 && sscanf(buf, "%d", &i) > 0)
152 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
153
154 return count;
155}
156
157static DEVICE_ATTR_RW(fail_iommu);
158
159static int fail_iommu_bus_notify(struct notifier_block *nb,
160 unsigned long action, void *data)
161{
162 struct device *dev = data;
163
164 if (action == BUS_NOTIFY_ADD_DEVICE) {
165 if (device_create_file(dev, &dev_attr_fail_iommu))
166 pr_warn("Unable to create IOMMU fault injection sysfs "
167 "entries\n");
168 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
169 device_remove_file(dev, &dev_attr_fail_iommu);
170 }
171
172 return 0;
173}
174
175/*
176 * PCI and VIO buses need separate notifier_block structs, since they're linked
177 * list nodes. Sharing a notifier_block would mean that any notifiers later
178 * registered for PCI buses would also get called by VIO buses and vice versa.
179 */
180static struct notifier_block fail_iommu_pci_bus_notifier = {
181 .notifier_call = fail_iommu_bus_notify
182};
183
184#ifdef CONFIG_IBMVIO
185static struct notifier_block fail_iommu_vio_bus_notifier = {
186 .notifier_call = fail_iommu_bus_notify
187};
188#endif
189
190static int __init fail_iommu_setup(void)
191{
192#ifdef CONFIG_PCI
193 bus_register_notifier(&pci_bus_type, &fail_iommu_pci_bus_notifier);
194#endif
195#ifdef CONFIG_IBMVIO
196 bus_register_notifier(&vio_bus_type, &fail_iommu_vio_bus_notifier);
197#endif
198
199 return 0;
200}
201/*
202 * Must execute after PCI and VIO subsystem have initialised but before
203 * devices are probed.
204 */
205arch_initcall(fail_iommu_setup);
206#else
207static inline bool should_fail_iommu(struct device *dev)
208{
209 return false;
210}
211#endif
212
213static unsigned long iommu_range_alloc(struct device *dev,
214 struct iommu_table *tbl,
215 unsigned long npages,
216 unsigned long *handle,
217 unsigned long mask,
218 unsigned int align_order)
219{
220 unsigned long n, end, start;
221 unsigned long limit;
222 int largealloc = npages > 15;
223 int pass = 0;
224 unsigned long align_mask;
225 unsigned long flags;
226 unsigned int pool_nr;
227 struct iommu_pool *pool;
228
229 align_mask = (1ull << align_order) - 1;
230
231 /* This allocator was derived from x86_64's bit string search */
232
233 /* Sanity check */
234 if (unlikely(npages == 0)) {
235 if (printk_ratelimit())
236 WARN_ON(1);
237 return DMA_MAPPING_ERROR;
238 }
239
240 if (should_fail_iommu(dev))
241 return DMA_MAPPING_ERROR;
242
243 /*
244 * We don't need to disable preemption here because any CPU can
245 * safely use any IOMMU pool.
246 */
247 pool_nr = raw_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
248
249 if (largealloc)
250 pool = &(tbl->large_pool);
251 else
252 pool = &(tbl->pools[pool_nr]);
253
254 spin_lock_irqsave(&(pool->lock), flags);
255
256again:
257 if ((pass == 0) && handle && *handle &&
258 (*handle >= pool->start) && (*handle < pool->end))
259 start = *handle;
260 else
261 start = pool->hint;
262
263 limit = pool->end;
264
265 /* The case below can happen if we have a small segment appended
266 * to a large, or when the previous alloc was at the very end of
267 * the available space. If so, go back to the initial start.
268 */
269 if (start >= limit)
270 start = pool->start;
271
272 if (limit + tbl->it_offset > mask) {
273 limit = mask - tbl->it_offset + 1;
274 /* If we're constrained on address range, first try
275 * at the masked hint to avoid O(n) search complexity,
276 * but on second pass, start at 0 in pool 0.
277 */
278 if ((start & mask) >= limit || pass > 0) {
279 spin_unlock(&(pool->lock));
280 pool = &(tbl->pools[0]);
281 spin_lock(&(pool->lock));
282 start = pool->start;
283 } else {
284 start &= mask;
285 }
286 }
287
288 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
289 dma_get_seg_boundary_nr_pages(dev, tbl->it_page_shift),
290 align_mask);
291 if (n == -1) {
292 if (likely(pass == 0)) {
293 /* First try the pool from the start */
294 pool->hint = pool->start;
295 pass++;
296 goto again;
297
298 } else if (pass <= tbl->nr_pools) {
299 /* Now try scanning all the other pools */
300 spin_unlock(&(pool->lock));
301 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
302 pool = &tbl->pools[pool_nr];
303 spin_lock(&(pool->lock));
304 pool->hint = pool->start;
305 pass++;
306 goto again;
307
308 } else if (pass == tbl->nr_pools + 1) {
309 /* Last resort: try largepool */
310 spin_unlock(&pool->lock);
311 pool = &tbl->large_pool;
312 spin_lock(&pool->lock);
313 pool->hint = pool->start;
314 pass++;
315 goto again;
316
317 } else {
318 /* Give up */
319 spin_unlock_irqrestore(&(pool->lock), flags);
320 return DMA_MAPPING_ERROR;
321 }
322 }
323
324 end = n + npages;
325
326 /* Bump the hint to a new block for small allocs. */
327 if (largealloc) {
328 /* Don't bump to new block to avoid fragmentation */
329 pool->hint = end;
330 } else {
331 /* Overflow will be taken care of at the next allocation */
332 pool->hint = (end + tbl->it_blocksize - 1) &
333 ~(tbl->it_blocksize - 1);
334 }
335
336 /* Update handle for SG allocations */
337 if (handle)
338 *handle = end;
339
340 spin_unlock_irqrestore(&(pool->lock), flags);
341
342 return n;
343}
344
345static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
346 void *page, unsigned int npages,
347 enum dma_data_direction direction,
348 unsigned long mask, unsigned int align_order,
349 unsigned long attrs)
350{
351 unsigned long entry;
352 dma_addr_t ret = DMA_MAPPING_ERROR;
353 int build_fail;
354
355 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
356
357 if (unlikely(entry == DMA_MAPPING_ERROR))
358 return DMA_MAPPING_ERROR;
359
360 entry += tbl->it_offset; /* Offset into real TCE table */
361 ret = entry << tbl->it_page_shift; /* Set the return dma address */
362
363 /* Put the TCEs in the HW table */
364 build_fail = tbl->it_ops->set(tbl, entry, npages,
365 (unsigned long)page &
366 IOMMU_PAGE_MASK(tbl), direction, attrs);
367
368 /* tbl->it_ops->set() only returns non-zero for transient errors.
369 * Clean up the table bitmap in this case and return
370 * DMA_MAPPING_ERROR. For all other errors the functionality is
371 * not altered.
372 */
373 if (unlikely(build_fail)) {
374 __iommu_free(tbl, ret, npages);
375 return DMA_MAPPING_ERROR;
376 }
377
378 /* Flush/invalidate TLB caches if necessary */
379 if (tbl->it_ops->flush)
380 tbl->it_ops->flush(tbl);
381
382 /* Make sure updates are seen by hardware */
383 mb();
384
385 return ret;
386}
387
388static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
389 unsigned int npages)
390{
391 unsigned long entry, free_entry;
392
393 entry = dma_addr >> tbl->it_page_shift;
394 free_entry = entry - tbl->it_offset;
395
396 if (((free_entry + npages) > tbl->it_size) ||
397 (entry < tbl->it_offset)) {
398 if (printk_ratelimit()) {
399 printk(KERN_INFO "iommu_free: invalid entry\n");
400 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
401 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
402 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
403 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
404 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
405 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
406 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
407 WARN_ON(1);
408 }
409
410 return false;
411 }
412
413 return true;
414}
415
416static struct iommu_pool *get_pool(struct iommu_table *tbl,
417 unsigned long entry)
418{
419 struct iommu_pool *p;
420 unsigned long largepool_start = tbl->large_pool.start;
421
422 /* The large pool is the last pool at the top of the table */
423 if (entry >= largepool_start) {
424 p = &tbl->large_pool;
425 } else {
426 unsigned int pool_nr = entry / tbl->poolsize;
427
428 BUG_ON(pool_nr > tbl->nr_pools);
429 p = &tbl->pools[pool_nr];
430 }
431
432 return p;
433}
434
435static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
436 unsigned int npages)
437{
438 unsigned long entry, free_entry;
439 unsigned long flags;
440 struct iommu_pool *pool;
441
442 entry = dma_addr >> tbl->it_page_shift;
443 free_entry = entry - tbl->it_offset;
444
445 pool = get_pool(tbl, free_entry);
446
447 if (!iommu_free_check(tbl, dma_addr, npages))
448 return;
449
450 tbl->it_ops->clear(tbl, entry, npages);
451
452 spin_lock_irqsave(&(pool->lock), flags);
453 bitmap_clear(tbl->it_map, free_entry, npages);
454 spin_unlock_irqrestore(&(pool->lock), flags);
455}
456
457static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
458 unsigned int npages)
459{
460 __iommu_free(tbl, dma_addr, npages);
461
462 /* Make sure TLB cache is flushed if the HW needs it. We do
463 * not do an mb() here on purpose, it is not needed on any of
464 * the current platforms.
465 */
466 if (tbl->it_ops->flush)
467 tbl->it_ops->flush(tbl);
468}
469
470int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
471 struct scatterlist *sglist, int nelems,
472 unsigned long mask, enum dma_data_direction direction,
473 unsigned long attrs)
474{
475 dma_addr_t dma_next = 0, dma_addr;
476 struct scatterlist *s, *outs, *segstart;
477 int outcount, incount, i, build_fail = 0;
478 unsigned int align;
479 unsigned long handle;
480 unsigned int max_seg_size;
481
482 BUG_ON(direction == DMA_NONE);
483
484 if ((nelems == 0) || !tbl)
485 return -EINVAL;
486
487 outs = s = segstart = &sglist[0];
488 outcount = 1;
489 incount = nelems;
490 handle = 0;
491
492 /* Init first segment length for backout at failure */
493 outs->dma_length = 0;
494
495 DBG("sg mapping %d elements:\n", nelems);
496
497 max_seg_size = dma_get_max_seg_size(dev);
498 for_each_sg(sglist, s, nelems, i) {
499 unsigned long vaddr, npages, entry, slen;
500
501 slen = s->length;
502 /* Sanity check */
503 if (slen == 0) {
504 dma_next = 0;
505 continue;
506 }
507 /* Allocate iommu entries for that segment */
508 vaddr = (unsigned long) sg_virt(s);
509 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
510 align = 0;
511 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
512 (vaddr & ~PAGE_MASK) == 0)
513 align = PAGE_SHIFT - tbl->it_page_shift;
514 entry = iommu_range_alloc(dev, tbl, npages, &handle,
515 mask >> tbl->it_page_shift, align);
516
517 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
518
519 /* Handle failure */
520 if (unlikely(entry == DMA_MAPPING_ERROR)) {
521 if (!(attrs & DMA_ATTR_NO_WARN) &&
522 printk_ratelimit())
523 dev_info(dev, "iommu_alloc failed, tbl %p "
524 "vaddr %lx npages %lu\n", tbl, vaddr,
525 npages);
526 goto failure;
527 }
528
529 /* Convert entry to a dma_addr_t */
530 entry += tbl->it_offset;
531 dma_addr = entry << tbl->it_page_shift;
532 dma_addr |= (vaddr & ~IOMMU_PAGE_MASK(tbl));
533
534 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
535 npages, entry, dma_addr);
536
537 /* Insert into HW table */
538 build_fail = tbl->it_ops->set(tbl, entry, npages,
539 vaddr & IOMMU_PAGE_MASK(tbl),
540 direction, attrs);
541 if(unlikely(build_fail))
542 goto failure;
543
544 /* If we are in an open segment, try merging */
545 if (segstart != s) {
546 DBG(" - trying merge...\n");
547 /* We cannot merge if:
548 * - allocated dma_addr isn't contiguous to previous allocation
549 */
550 if (novmerge || (dma_addr != dma_next) ||
551 (outs->dma_length + s->length > max_seg_size)) {
552 /* Can't merge: create a new segment */
553 segstart = s;
554 outcount++;
555 outs = sg_next(outs);
556 DBG(" can't merge, new segment.\n");
557 } else {
558 outs->dma_length += s->length;
559 DBG(" merged, new len: %ux\n", outs->dma_length);
560 }
561 }
562
563 if (segstart == s) {
564 /* This is a new segment, fill entries */
565 DBG(" - filling new segment.\n");
566 outs->dma_address = dma_addr;
567 outs->dma_length = slen;
568 }
569
570 /* Calculate next page pointer for contiguous check */
571 dma_next = dma_addr + slen;
572
573 DBG(" - dma next is: %lx\n", dma_next);
574 }
575
576 /* Flush/invalidate TLB caches if necessary */
577 if (tbl->it_ops->flush)
578 tbl->it_ops->flush(tbl);
579
580 DBG("mapped %d elements:\n", outcount);
581
582 /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
583 * next entry of the sglist if we didn't fill the list completely
584 */
585 if (outcount < incount) {
586 outs = sg_next(outs);
587 outs->dma_length = 0;
588 }
589
590 /* Make sure updates are seen by hardware */
591 mb();
592
593 return outcount;
594
595 failure:
596 for_each_sg(sglist, s, nelems, i) {
597 if (s->dma_length != 0) {
598 unsigned long vaddr, npages;
599
600 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
601 npages = iommu_num_pages(s->dma_address, s->dma_length,
602 IOMMU_PAGE_SIZE(tbl));
603 __iommu_free(tbl, vaddr, npages);
604 s->dma_length = 0;
605 }
606 if (s == outs)
607 break;
608 }
609 return -EIO;
610}
611
612
613void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
614 int nelems, enum dma_data_direction direction,
615 unsigned long attrs)
616{
617 struct scatterlist *sg;
618
619 BUG_ON(direction == DMA_NONE);
620
621 if (!tbl)
622 return;
623
624 sg = sglist;
625 while (nelems--) {
626 unsigned int npages;
627 dma_addr_t dma_handle = sg->dma_address;
628
629 if (sg->dma_length == 0)
630 break;
631 npages = iommu_num_pages(dma_handle, sg->dma_length,
632 IOMMU_PAGE_SIZE(tbl));
633 __iommu_free(tbl, dma_handle, npages);
634 sg = sg_next(sg);
635 }
636
637 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
638 * do not do an mb() here, the affected platforms do not need it
639 * when freeing.
640 */
641 if (tbl->it_ops->flush)
642 tbl->it_ops->flush(tbl);
643}
644
645static void iommu_table_clear(struct iommu_table *tbl)
646{
647 /*
648 * In case of firmware assisted dump system goes through clean
649 * reboot process at the time of system crash. Hence it's safe to
650 * clear the TCE entries if firmware assisted dump is active.
651 */
652 if (!is_kdump_kernel() || is_fadump_active()) {
653 /* Clear the table in case firmware left allocations in it */
654 tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
655 return;
656 }
657
658#ifdef CONFIG_CRASH_DUMP
659 if (tbl->it_ops->get) {
660 unsigned long index, tceval, tcecount = 0;
661
662 /* Reserve the existing mappings left by the first kernel. */
663 for (index = 0; index < tbl->it_size; index++) {
664 tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
665 /*
666 * Freed TCE entry contains 0x7fffffffffffffff on JS20
667 */
668 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
669 __set_bit(index, tbl->it_map);
670 tcecount++;
671 }
672 }
673
674 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
675 printk(KERN_WARNING "TCE table is full; freeing ");
676 printk(KERN_WARNING "%d entries for the kdump boot\n",
677 KDUMP_MIN_TCE_ENTRIES);
678 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
679 index < tbl->it_size; index++)
680 __clear_bit(index, tbl->it_map);
681 }
682 }
683#endif
684}
685
686static void iommu_table_reserve_pages(struct iommu_table *tbl,
687 unsigned long res_start, unsigned long res_end)
688{
689 int i;
690
691 WARN_ON_ONCE(res_end < res_start);
692 /*
693 * Reserve page 0 so it will not be used for any mappings.
694 * This avoids buggy drivers that consider page 0 to be invalid
695 * to crash the machine or even lose data.
696 */
697 if (tbl->it_offset == 0)
698 set_bit(0, tbl->it_map);
699
700 if (res_start < tbl->it_offset)
701 res_start = tbl->it_offset;
702
703 if (res_end > (tbl->it_offset + tbl->it_size))
704 res_end = tbl->it_offset + tbl->it_size;
705
706 /* Check if res_start..res_end is a valid range in the table */
707 if (res_start >= res_end) {
708 tbl->it_reserved_start = tbl->it_offset;
709 tbl->it_reserved_end = tbl->it_offset;
710 return;
711 }
712
713 tbl->it_reserved_start = res_start;
714 tbl->it_reserved_end = res_end;
715
716 for (i = tbl->it_reserved_start; i < tbl->it_reserved_end; ++i)
717 set_bit(i - tbl->it_offset, tbl->it_map);
718}
719
720/*
721 * Build a iommu_table structure. This contains a bit map which
722 * is used to manage allocation of the tce space.
723 */
724struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid,
725 unsigned long res_start, unsigned long res_end)
726{
727 unsigned long sz;
728 static int welcomed = 0;
729 unsigned int i;
730 struct iommu_pool *p;
731
732 BUG_ON(!tbl->it_ops);
733
734 /* number of bytes needed for the bitmap */
735 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
736
737 tbl->it_map = vzalloc_node(sz, nid);
738 if (!tbl->it_map) {
739 pr_err("%s: Can't allocate %ld bytes\n", __func__, sz);
740 return NULL;
741 }
742
743 iommu_table_reserve_pages(tbl, res_start, res_end);
744
745 /* We only split the IOMMU table if we have 1GB or more of space */
746 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
747 tbl->nr_pools = IOMMU_NR_POOLS;
748 else
749 tbl->nr_pools = 1;
750
751 /* We reserve the top 1/4 of the table for large allocations */
752 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
753
754 for (i = 0; i < tbl->nr_pools; i++) {
755 p = &tbl->pools[i];
756 spin_lock_init(&(p->lock));
757 p->start = tbl->poolsize * i;
758 p->hint = p->start;
759 p->end = p->start + tbl->poolsize;
760 }
761
762 p = &tbl->large_pool;
763 spin_lock_init(&(p->lock));
764 p->start = tbl->poolsize * i;
765 p->hint = p->start;
766 p->end = tbl->it_size;
767
768 iommu_table_clear(tbl);
769
770 if (!welcomed) {
771 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
772 novmerge ? "disabled" : "enabled");
773 welcomed = 1;
774 }
775
776 iommu_debugfs_add(tbl);
777
778 return tbl;
779}
780
781bool iommu_table_in_use(struct iommu_table *tbl)
782{
783 unsigned long start = 0, end;
784
785 /* ignore reserved bit0 */
786 if (tbl->it_offset == 0)
787 start = 1;
788
789 /* Simple case with no reserved MMIO32 region */
790 if (!tbl->it_reserved_start && !tbl->it_reserved_end)
791 return find_next_bit(tbl->it_map, tbl->it_size, start) != tbl->it_size;
792
793 end = tbl->it_reserved_start - tbl->it_offset;
794 if (find_next_bit(tbl->it_map, end, start) != end)
795 return true;
796
797 start = tbl->it_reserved_end - tbl->it_offset;
798 end = tbl->it_size;
799 return find_next_bit(tbl->it_map, end, start) != end;
800}
801
802static void iommu_table_free(struct kref *kref)
803{
804 struct iommu_table *tbl;
805
806 tbl = container_of(kref, struct iommu_table, it_kref);
807
808 if (tbl->it_ops->free)
809 tbl->it_ops->free(tbl);
810
811 if (!tbl->it_map) {
812 kfree(tbl);
813 return;
814 }
815
816 iommu_debugfs_del(tbl);
817
818 /* verify that table contains no entries */
819 if (iommu_table_in_use(tbl))
820 pr_warn("%s: Unexpected TCEs\n", __func__);
821
822 /* free bitmap */
823 vfree(tbl->it_map);
824
825 /* free table */
826 kfree(tbl);
827}
828
829struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl)
830{
831 if (kref_get_unless_zero(&tbl->it_kref))
832 return tbl;
833
834 return NULL;
835}
836EXPORT_SYMBOL_GPL(iommu_tce_table_get);
837
838int iommu_tce_table_put(struct iommu_table *tbl)
839{
840 if (WARN_ON(!tbl))
841 return 0;
842
843 return kref_put(&tbl->it_kref, iommu_table_free);
844}
845EXPORT_SYMBOL_GPL(iommu_tce_table_put);
846
847/* Creates TCEs for a user provided buffer. The user buffer must be
848 * contiguous real kernel storage (not vmalloc). The address passed here
849 * comprises a page address and offset into that page. The dma_addr_t
850 * returned will point to the same byte within the page as was passed in.
851 */
852dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
853 struct page *page, unsigned long offset, size_t size,
854 unsigned long mask, enum dma_data_direction direction,
855 unsigned long attrs)
856{
857 dma_addr_t dma_handle = DMA_MAPPING_ERROR;
858 void *vaddr;
859 unsigned long uaddr;
860 unsigned int npages, align;
861
862 BUG_ON(direction == DMA_NONE);
863
864 vaddr = page_address(page) + offset;
865 uaddr = (unsigned long)vaddr;
866
867 if (tbl) {
868 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
869 align = 0;
870 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
871 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
872 align = PAGE_SHIFT - tbl->it_page_shift;
873
874 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
875 mask >> tbl->it_page_shift, align,
876 attrs);
877 if (dma_handle == DMA_MAPPING_ERROR) {
878 if (!(attrs & DMA_ATTR_NO_WARN) &&
879 printk_ratelimit()) {
880 dev_info(dev, "iommu_alloc failed, tbl %p "
881 "vaddr %p npages %d\n", tbl, vaddr,
882 npages);
883 }
884 } else
885 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
886 }
887
888 return dma_handle;
889}
890
891void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
892 size_t size, enum dma_data_direction direction,
893 unsigned long attrs)
894{
895 unsigned int npages;
896
897 BUG_ON(direction == DMA_NONE);
898
899 if (tbl) {
900 npages = iommu_num_pages(dma_handle, size,
901 IOMMU_PAGE_SIZE(tbl));
902 iommu_free(tbl, dma_handle, npages);
903 }
904}
905
906/* Allocates a contiguous real buffer and creates mappings over it.
907 * Returns the virtual address of the buffer and sets dma_handle
908 * to the dma address (mapping) of the first page.
909 */
910void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
911 size_t size, dma_addr_t *dma_handle,
912 unsigned long mask, gfp_t flag, int node)
913{
914 void *ret = NULL;
915 dma_addr_t mapping;
916 unsigned int order;
917 unsigned int nio_pages, io_order;
918 struct page *page;
919 int tcesize = (1 << tbl->it_page_shift);
920
921 size = PAGE_ALIGN(size);
922 order = get_order(size);
923
924 /*
925 * Client asked for way too much space. This is checked later
926 * anyway. It is easier to debug here for the drivers than in
927 * the tce tables.
928 */
929 if (order >= IOMAP_MAX_ORDER) {
930 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
931 size);
932 return NULL;
933 }
934
935 if (!tbl)
936 return NULL;
937
938 /* Alloc enough pages (and possibly more) */
939 page = alloc_pages_node(node, flag, order);
940 if (!page)
941 return NULL;
942 ret = page_address(page);
943 memset(ret, 0, size);
944
945 /* Set up tces to cover the allocated range */
946 nio_pages = IOMMU_PAGE_ALIGN(size, tbl) >> tbl->it_page_shift;
947
948 io_order = get_iommu_order(size, tbl);
949 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
950 mask >> tbl->it_page_shift, io_order, 0);
951 if (mapping == DMA_MAPPING_ERROR) {
952 free_pages((unsigned long)ret, order);
953 return NULL;
954 }
955
956 *dma_handle = mapping | ((u64)ret & (tcesize - 1));
957 return ret;
958}
959
960void iommu_free_coherent(struct iommu_table *tbl, size_t size,
961 void *vaddr, dma_addr_t dma_handle)
962{
963 if (tbl) {
964 unsigned int nio_pages;
965
966 size = PAGE_ALIGN(size);
967 nio_pages = IOMMU_PAGE_ALIGN(size, tbl) >> tbl->it_page_shift;
968 iommu_free(tbl, dma_handle, nio_pages);
969 size = PAGE_ALIGN(size);
970 free_pages((unsigned long)vaddr, get_order(size));
971 }
972}
973
974unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
975{
976 switch (dir) {
977 case DMA_BIDIRECTIONAL:
978 return TCE_PCI_READ | TCE_PCI_WRITE;
979 case DMA_FROM_DEVICE:
980 return TCE_PCI_WRITE;
981 case DMA_TO_DEVICE:
982 return TCE_PCI_READ;
983 default:
984 return 0;
985 }
986}
987EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
988
989#ifdef CONFIG_IOMMU_API
990/*
991 * SPAPR TCE API
992 */
993static void group_release(void *iommu_data)
994{
995 struct iommu_table_group *table_group = iommu_data;
996
997 table_group->group = NULL;
998}
999
1000void iommu_register_group(struct iommu_table_group *table_group,
1001 int pci_domain_number, unsigned long pe_num)
1002{
1003 struct iommu_group *grp;
1004 char *name;
1005
1006 grp = iommu_group_alloc();
1007 if (IS_ERR(grp)) {
1008 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
1009 PTR_ERR(grp));
1010 return;
1011 }
1012 table_group->group = grp;
1013 iommu_group_set_iommudata(grp, table_group, group_release);
1014 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
1015 pci_domain_number, pe_num);
1016 if (!name)
1017 return;
1018 iommu_group_set_name(grp, name);
1019 kfree(name);
1020}
1021
1022enum dma_data_direction iommu_tce_direction(unsigned long tce)
1023{
1024 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
1025 return DMA_BIDIRECTIONAL;
1026 else if (tce & TCE_PCI_READ)
1027 return DMA_TO_DEVICE;
1028 else if (tce & TCE_PCI_WRITE)
1029 return DMA_FROM_DEVICE;
1030 else
1031 return DMA_NONE;
1032}
1033EXPORT_SYMBOL_GPL(iommu_tce_direction);
1034
1035void iommu_flush_tce(struct iommu_table *tbl)
1036{
1037 /* Flush/invalidate TLB caches if necessary */
1038 if (tbl->it_ops->flush)
1039 tbl->it_ops->flush(tbl);
1040
1041 /* Make sure updates are seen by hardware */
1042 mb();
1043}
1044EXPORT_SYMBOL_GPL(iommu_flush_tce);
1045
1046int iommu_tce_check_ioba(unsigned long page_shift,
1047 unsigned long offset, unsigned long size,
1048 unsigned long ioba, unsigned long npages)
1049{
1050 unsigned long mask = (1UL << page_shift) - 1;
1051
1052 if (ioba & mask)
1053 return -EINVAL;
1054
1055 ioba >>= page_shift;
1056 if (ioba < offset)
1057 return -EINVAL;
1058
1059 if ((ioba + 1) > (offset + size))
1060 return -EINVAL;
1061
1062 return 0;
1063}
1064EXPORT_SYMBOL_GPL(iommu_tce_check_ioba);
1065
1066int iommu_tce_check_gpa(unsigned long page_shift, unsigned long gpa)
1067{
1068 unsigned long mask = (1UL << page_shift) - 1;
1069
1070 if (gpa & mask)
1071 return -EINVAL;
1072
1073 return 0;
1074}
1075EXPORT_SYMBOL_GPL(iommu_tce_check_gpa);
1076
1077long iommu_tce_xchg_no_kill(struct mm_struct *mm,
1078 struct iommu_table *tbl,
1079 unsigned long entry, unsigned long *hpa,
1080 enum dma_data_direction *direction)
1081{
1082 long ret;
1083 unsigned long size = 0;
1084
1085 ret = tbl->it_ops->xchg_no_kill(tbl, entry, hpa, direction);
1086 if (!ret && ((*direction == DMA_FROM_DEVICE) ||
1087 (*direction == DMA_BIDIRECTIONAL)) &&
1088 !mm_iommu_is_devmem(mm, *hpa, tbl->it_page_shift,
1089 &size))
1090 SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
1091
1092 return ret;
1093}
1094EXPORT_SYMBOL_GPL(iommu_tce_xchg_no_kill);
1095
1096void iommu_tce_kill(struct iommu_table *tbl,
1097 unsigned long entry, unsigned long pages)
1098{
1099 if (tbl->it_ops->tce_kill)
1100 tbl->it_ops->tce_kill(tbl, entry, pages);
1101}
1102EXPORT_SYMBOL_GPL(iommu_tce_kill);
1103
1104#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
1105static int iommu_take_ownership(struct iommu_table *tbl)
1106{
1107 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1108 int ret = 0;
1109
1110 /*
1111 * VFIO does not control TCE entries allocation and the guest
1112 * can write new TCEs on top of existing ones so iommu_tce_build()
1113 * must be able to release old pages. This functionality
1114 * requires exchange() callback defined so if it is not
1115 * implemented, we disallow taking ownership over the table.
1116 */
1117 if (!tbl->it_ops->xchg_no_kill)
1118 return -EINVAL;
1119
1120 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1121 for (i = 0; i < tbl->nr_pools; i++)
1122 spin_lock_nest_lock(&tbl->pools[i].lock, &tbl->large_pool.lock);
1123
1124 if (iommu_table_in_use(tbl)) {
1125 pr_err("iommu_tce: it_map is not empty");
1126 ret = -EBUSY;
1127 } else {
1128 memset(tbl->it_map, 0xff, sz);
1129 }
1130
1131 for (i = 0; i < tbl->nr_pools; i++)
1132 spin_unlock(&tbl->pools[i].lock);
1133 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1134
1135 return ret;
1136}
1137
1138static void iommu_release_ownership(struct iommu_table *tbl)
1139{
1140 unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1141
1142 spin_lock_irqsave(&tbl->large_pool.lock, flags);
1143 for (i = 0; i < tbl->nr_pools; i++)
1144 spin_lock_nest_lock(&tbl->pools[i].lock, &tbl->large_pool.lock);
1145
1146 memset(tbl->it_map, 0, sz);
1147
1148 iommu_table_reserve_pages(tbl, tbl->it_reserved_start,
1149 tbl->it_reserved_end);
1150
1151 for (i = 0; i < tbl->nr_pools; i++)
1152 spin_unlock(&tbl->pools[i].lock);
1153 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1154}
1155#endif
1156
1157int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
1158{
1159 /*
1160 * The sysfs entries should be populated before
1161 * binding IOMMU group. If sysfs entries isn't
1162 * ready, we simply bail.
1163 */
1164 if (!device_is_registered(dev))
1165 return -ENOENT;
1166
1167 if (device_iommu_mapped(dev)) {
1168 pr_debug("%s: Skipping device %s with iommu group %d\n",
1169 __func__, dev_name(dev),
1170 iommu_group_id(dev->iommu_group));
1171 return -EBUSY;
1172 }
1173
1174 pr_debug("%s: Adding %s to iommu group %d\n",
1175 __func__, dev_name(dev), iommu_group_id(table_group->group));
1176 /*
1177 * This is still not adding devices via the IOMMU bus notifier because
1178 * of pcibios_init() from arch/powerpc/kernel/pci_64.c which calls
1179 * pcibios_scan_phb() first (and this guy adds devices and triggers
1180 * the notifier) and only then it calls pci_bus_add_devices() which
1181 * configures DMA for buses which also creates PEs and IOMMU groups.
1182 */
1183 return iommu_probe_device(dev);
1184}
1185EXPORT_SYMBOL_GPL(iommu_add_device);
1186
1187#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
1188/*
1189 * A simple iommu_table_group_ops which only allows reusing the existing
1190 * iommu_table. This handles VFIO for POWER7 or the nested KVM.
1191 * The ops does not allow creating windows and only allows reusing the existing
1192 * one if it matches table_group->tce32_start/tce32_size/page_shift.
1193 */
1194static unsigned long spapr_tce_get_table_size(__u32 page_shift,
1195 __u64 window_size, __u32 levels)
1196{
1197 unsigned long size;
1198
1199 if (levels > 1)
1200 return ~0U;
1201 size = window_size >> (page_shift - 3);
1202 return size;
1203}
1204
1205static long spapr_tce_create_table(struct iommu_table_group *table_group, int num,
1206 __u32 page_shift, __u64 window_size, __u32 levels,
1207 struct iommu_table **ptbl)
1208{
1209 struct iommu_table *tbl = table_group->tables[0];
1210
1211 if (num > 0)
1212 return -EPERM;
1213
1214 if (tbl->it_page_shift != page_shift ||
1215 tbl->it_size != (window_size >> page_shift) ||
1216 tbl->it_indirect_levels != levels - 1)
1217 return -EINVAL;
1218
1219 *ptbl = iommu_tce_table_get(tbl);
1220 return 0;
1221}
1222
1223static long spapr_tce_set_window(struct iommu_table_group *table_group,
1224 int num, struct iommu_table *tbl)
1225{
1226 return tbl == table_group->tables[num] ? 0 : -EPERM;
1227}
1228
1229static long spapr_tce_unset_window(struct iommu_table_group *table_group, int num)
1230{
1231 return 0;
1232}
1233
1234static long spapr_tce_take_ownership(struct iommu_table_group *table_group)
1235{
1236 int i, j, rc = 0;
1237
1238 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1239 struct iommu_table *tbl = table_group->tables[i];
1240
1241 if (!tbl || !tbl->it_map)
1242 continue;
1243
1244 rc = iommu_take_ownership(tbl);
1245 if (!rc)
1246 continue;
1247
1248 for (j = 0; j < i; ++j)
1249 iommu_release_ownership(table_group->tables[j]);
1250 return rc;
1251 }
1252 return 0;
1253}
1254
1255static void spapr_tce_release_ownership(struct iommu_table_group *table_group)
1256{
1257 int i;
1258
1259 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1260 struct iommu_table *tbl = table_group->tables[i];
1261
1262 if (!tbl)
1263 continue;
1264
1265 iommu_table_clear(tbl);
1266 if (tbl->it_map)
1267 iommu_release_ownership(tbl);
1268 }
1269}
1270
1271struct iommu_table_group_ops spapr_tce_table_group_ops = {
1272 .get_table_size = spapr_tce_get_table_size,
1273 .create_table = spapr_tce_create_table,
1274 .set_window = spapr_tce_set_window,
1275 .unset_window = spapr_tce_unset_window,
1276 .take_ownership = spapr_tce_take_ownership,
1277 .release_ownership = spapr_tce_release_ownership,
1278};
1279
1280/*
1281 * A simple iommu_ops to allow less cruft in generic VFIO code.
1282 */
1283static int
1284spapr_tce_platform_iommu_attach_dev(struct iommu_domain *platform_domain,
1285 struct device *dev)
1286{
1287 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1288 struct iommu_group *grp = iommu_group_get(dev);
1289 struct iommu_table_group *table_group;
1290
1291 /* At first attach the ownership is already set */
1292 if (!domain) {
1293 iommu_group_put(grp);
1294 return 0;
1295 }
1296
1297 table_group = iommu_group_get_iommudata(grp);
1298 /*
1299 * The domain being set to PLATFORM from earlier
1300 * BLOCKED. The table_group ownership has to be released.
1301 */
1302 table_group->ops->release_ownership(table_group);
1303 iommu_group_put(grp);
1304
1305 return 0;
1306}
1307
1308static const struct iommu_domain_ops spapr_tce_platform_domain_ops = {
1309 .attach_dev = spapr_tce_platform_iommu_attach_dev,
1310};
1311
1312static struct iommu_domain spapr_tce_platform_domain = {
1313 .type = IOMMU_DOMAIN_PLATFORM,
1314 .ops = &spapr_tce_platform_domain_ops,
1315};
1316
1317static int
1318spapr_tce_blocked_iommu_attach_dev(struct iommu_domain *platform_domain,
1319 struct device *dev)
1320{
1321 struct iommu_group *grp = iommu_group_get(dev);
1322 struct iommu_table_group *table_group;
1323 int ret = -EINVAL;
1324
1325 /*
1326 * FIXME: SPAPR mixes blocked and platform behaviors, the blocked domain
1327 * also sets the dma_api ops
1328 */
1329 table_group = iommu_group_get_iommudata(grp);
1330 ret = table_group->ops->take_ownership(table_group);
1331 iommu_group_put(grp);
1332
1333 return ret;
1334}
1335
1336static const struct iommu_domain_ops spapr_tce_blocked_domain_ops = {
1337 .attach_dev = spapr_tce_blocked_iommu_attach_dev,
1338};
1339
1340static struct iommu_domain spapr_tce_blocked_domain = {
1341 .type = IOMMU_DOMAIN_BLOCKED,
1342 .ops = &spapr_tce_blocked_domain_ops,
1343};
1344
1345static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap)
1346{
1347 switch (cap) {
1348 case IOMMU_CAP_CACHE_COHERENCY:
1349 return true;
1350 default:
1351 break;
1352 }
1353
1354 return false;
1355}
1356
1357static struct iommu_device *spapr_tce_iommu_probe_device(struct device *dev)
1358{
1359 struct pci_dev *pdev;
1360 struct pci_controller *hose;
1361
1362 if (!dev_is_pci(dev))
1363 return ERR_PTR(-ENODEV);
1364
1365 pdev = to_pci_dev(dev);
1366 hose = pdev->bus->sysdata;
1367
1368 return &hose->iommu;
1369}
1370
1371static void spapr_tce_iommu_release_device(struct device *dev)
1372{
1373}
1374
1375static struct iommu_group *spapr_tce_iommu_device_group(struct device *dev)
1376{
1377 struct pci_controller *hose;
1378 struct pci_dev *pdev;
1379
1380 pdev = to_pci_dev(dev);
1381 hose = pdev->bus->sysdata;
1382
1383 if (!hose->controller_ops.device_group)
1384 return ERR_PTR(-ENOENT);
1385
1386 return hose->controller_ops.device_group(hose, pdev);
1387}
1388
1389static const struct iommu_ops spapr_tce_iommu_ops = {
1390 .default_domain = &spapr_tce_platform_domain,
1391 .blocked_domain = &spapr_tce_blocked_domain,
1392 .capable = spapr_tce_iommu_capable,
1393 .probe_device = spapr_tce_iommu_probe_device,
1394 .release_device = spapr_tce_iommu_release_device,
1395 .device_group = spapr_tce_iommu_device_group,
1396};
1397
1398static struct attribute *spapr_tce_iommu_attrs[] = {
1399 NULL,
1400};
1401
1402static struct attribute_group spapr_tce_iommu_group = {
1403 .name = "spapr-tce-iommu",
1404 .attrs = spapr_tce_iommu_attrs,
1405};
1406
1407static const struct attribute_group *spapr_tce_iommu_groups[] = {
1408 &spapr_tce_iommu_group,
1409 NULL,
1410};
1411
1412void ppc_iommu_register_device(struct pci_controller *phb)
1413{
1414 iommu_device_sysfs_add(&phb->iommu, phb->parent,
1415 spapr_tce_iommu_groups, "iommu-phb%04x",
1416 phb->global_number);
1417 iommu_device_register(&phb->iommu, &spapr_tce_iommu_ops,
1418 phb->parent);
1419}
1420
1421void ppc_iommu_unregister_device(struct pci_controller *phb)
1422{
1423 iommu_device_unregister(&phb->iommu);
1424 iommu_device_sysfs_remove(&phb->iommu);
1425}
1426
1427/*
1428 * This registers IOMMU devices of PHBs. This needs to happen
1429 * after core_initcall(iommu_init) + postcore_initcall(pci_driver_init) and
1430 * before subsys_initcall(iommu_subsys_init).
1431 */
1432static int __init spapr_tce_setup_phb_iommus_initcall(void)
1433{
1434 struct pci_controller *hose;
1435
1436 list_for_each_entry(hose, &hose_list, list_node) {
1437 ppc_iommu_register_device(hose);
1438 }
1439 return 0;
1440}
1441postcore_initcall_sync(spapr_tce_setup_phb_iommus_initcall);
1442#endif
1443
1444#endif /* CONFIG_IOMMU_API */
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 *
4 * Rewrite, cleanup, new allocation schemes, virtual merging:
5 * Copyright (C) 2004 Olof Johansson, IBM Corporation
6 * and Ben. Herrenschmidt, IBM Corporation
7 *
8 * Dynamic DMA mapping support, bus-independent parts.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitmap.h>
34#include <linux/iommu-helper.h>
35#include <linux/crash_dump.h>
36#include <linux/hash.h>
37#include <linux/fault-inject.h>
38#include <linux/pci.h>
39#include <linux/iommu.h>
40#include <linux/sched.h>
41#include <asm/io.h>
42#include <asm/prom.h>
43#include <asm/iommu.h>
44#include <asm/pci-bridge.h>
45#include <asm/machdep.h>
46#include <asm/kdump.h>
47#include <asm/fadump.h>
48#include <asm/vio.h>
49#include <asm/tce.h>
50
51#define DBG(...)
52
53static int novmerge;
54
55static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
56
57static int __init setup_iommu(char *str)
58{
59 if (!strcmp(str, "novmerge"))
60 novmerge = 1;
61 else if (!strcmp(str, "vmerge"))
62 novmerge = 0;
63 return 1;
64}
65
66__setup("iommu=", setup_iommu);
67
68static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
69
70/*
71 * We precalculate the hash to avoid doing it on every allocation.
72 *
73 * The hash is important to spread CPUs across all the pools. For example,
74 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
75 * with 4 pools all primary threads would map to the same pool.
76 */
77static int __init setup_iommu_pool_hash(void)
78{
79 unsigned int i;
80
81 for_each_possible_cpu(i)
82 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
83
84 return 0;
85}
86subsys_initcall(setup_iommu_pool_hash);
87
88#ifdef CONFIG_FAIL_IOMMU
89
90static DECLARE_FAULT_ATTR(fail_iommu);
91
92static int __init setup_fail_iommu(char *str)
93{
94 return setup_fault_attr(&fail_iommu, str);
95}
96__setup("fail_iommu=", setup_fail_iommu);
97
98static bool should_fail_iommu(struct device *dev)
99{
100 return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
101}
102
103static int __init fail_iommu_debugfs(void)
104{
105 struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
106 NULL, &fail_iommu);
107
108 return PTR_ERR_OR_ZERO(dir);
109}
110late_initcall(fail_iommu_debugfs);
111
112static ssize_t fail_iommu_show(struct device *dev,
113 struct device_attribute *attr, char *buf)
114{
115 return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
116}
117
118static ssize_t fail_iommu_store(struct device *dev,
119 struct device_attribute *attr, const char *buf,
120 size_t count)
121{
122 int i;
123
124 if (count > 0 && sscanf(buf, "%d", &i) > 0)
125 dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
126
127 return count;
128}
129
130static DEVICE_ATTR(fail_iommu, S_IRUGO|S_IWUSR, fail_iommu_show,
131 fail_iommu_store);
132
133static int fail_iommu_bus_notify(struct notifier_block *nb,
134 unsigned long action, void *data)
135{
136 struct device *dev = data;
137
138 if (action == BUS_NOTIFY_ADD_DEVICE) {
139 if (device_create_file(dev, &dev_attr_fail_iommu))
140 pr_warn("Unable to create IOMMU fault injection sysfs "
141 "entries\n");
142 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
143 device_remove_file(dev, &dev_attr_fail_iommu);
144 }
145
146 return 0;
147}
148
149static struct notifier_block fail_iommu_bus_notifier = {
150 .notifier_call = fail_iommu_bus_notify
151};
152
153static int __init fail_iommu_setup(void)
154{
155#ifdef CONFIG_PCI
156 bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
157#endif
158#ifdef CONFIG_IBMVIO
159 bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
160#endif
161
162 return 0;
163}
164/*
165 * Must execute after PCI and VIO subsystem have initialised but before
166 * devices are probed.
167 */
168arch_initcall(fail_iommu_setup);
169#else
170static inline bool should_fail_iommu(struct device *dev)
171{
172 return false;
173}
174#endif
175
176static unsigned long iommu_range_alloc(struct device *dev,
177 struct iommu_table *tbl,
178 unsigned long npages,
179 unsigned long *handle,
180 unsigned long mask,
181 unsigned int align_order)
182{
183 unsigned long n, end, start;
184 unsigned long limit;
185 int largealloc = npages > 15;
186 int pass = 0;
187 unsigned long align_mask;
188 unsigned long boundary_size;
189 unsigned long flags;
190 unsigned int pool_nr;
191 struct iommu_pool *pool;
192
193 align_mask = 0xffffffffffffffffl >> (64 - align_order);
194
195 /* This allocator was derived from x86_64's bit string search */
196
197 /* Sanity check */
198 if (unlikely(npages == 0)) {
199 if (printk_ratelimit())
200 WARN_ON(1);
201 return DMA_ERROR_CODE;
202 }
203
204 if (should_fail_iommu(dev))
205 return DMA_ERROR_CODE;
206
207 /*
208 * We don't need to disable preemption here because any CPU can
209 * safely use any IOMMU pool.
210 */
211 pool_nr = __raw_get_cpu_var(iommu_pool_hash) & (tbl->nr_pools - 1);
212
213 if (largealloc)
214 pool = &(tbl->large_pool);
215 else
216 pool = &(tbl->pools[pool_nr]);
217
218 spin_lock_irqsave(&(pool->lock), flags);
219
220again:
221 if ((pass == 0) && handle && *handle &&
222 (*handle >= pool->start) && (*handle < pool->end))
223 start = *handle;
224 else
225 start = pool->hint;
226
227 limit = pool->end;
228
229 /* The case below can happen if we have a small segment appended
230 * to a large, or when the previous alloc was at the very end of
231 * the available space. If so, go back to the initial start.
232 */
233 if (start >= limit)
234 start = pool->start;
235
236 if (limit + tbl->it_offset > mask) {
237 limit = mask - tbl->it_offset + 1;
238 /* If we're constrained on address range, first try
239 * at the masked hint to avoid O(n) search complexity,
240 * but on second pass, start at 0 in pool 0.
241 */
242 if ((start & mask) >= limit || pass > 0) {
243 spin_unlock(&(pool->lock));
244 pool = &(tbl->pools[0]);
245 spin_lock(&(pool->lock));
246 start = pool->start;
247 } else {
248 start &= mask;
249 }
250 }
251
252 if (dev)
253 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
254 1 << tbl->it_page_shift);
255 else
256 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
257 /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
258
259 n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
260 boundary_size >> tbl->it_page_shift, align_mask);
261 if (n == -1) {
262 if (likely(pass == 0)) {
263 /* First try the pool from the start */
264 pool->hint = pool->start;
265 pass++;
266 goto again;
267
268 } else if (pass <= tbl->nr_pools) {
269 /* Now try scanning all the other pools */
270 spin_unlock(&(pool->lock));
271 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
272 pool = &tbl->pools[pool_nr];
273 spin_lock(&(pool->lock));
274 pool->hint = pool->start;
275 pass++;
276 goto again;
277
278 } else {
279 /* Give up */
280 spin_unlock_irqrestore(&(pool->lock), flags);
281 return DMA_ERROR_CODE;
282 }
283 }
284
285 end = n + npages;
286
287 /* Bump the hint to a new block for small allocs. */
288 if (largealloc) {
289 /* Don't bump to new block to avoid fragmentation */
290 pool->hint = end;
291 } else {
292 /* Overflow will be taken care of at the next allocation */
293 pool->hint = (end + tbl->it_blocksize - 1) &
294 ~(tbl->it_blocksize - 1);
295 }
296
297 /* Update handle for SG allocations */
298 if (handle)
299 *handle = end;
300
301 spin_unlock_irqrestore(&(pool->lock), flags);
302
303 return n;
304}
305
306static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
307 void *page, unsigned int npages,
308 enum dma_data_direction direction,
309 unsigned long mask, unsigned int align_order,
310 struct dma_attrs *attrs)
311{
312 unsigned long entry;
313 dma_addr_t ret = DMA_ERROR_CODE;
314 int build_fail;
315
316 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
317
318 if (unlikely(entry == DMA_ERROR_CODE))
319 return DMA_ERROR_CODE;
320
321 entry += tbl->it_offset; /* Offset into real TCE table */
322 ret = entry << tbl->it_page_shift; /* Set the return dma address */
323
324 /* Put the TCEs in the HW table */
325 build_fail = ppc_md.tce_build(tbl, entry, npages,
326 (unsigned long)page &
327 IOMMU_PAGE_MASK(tbl), direction, attrs);
328
329 /* ppc_md.tce_build() only returns non-zero for transient errors.
330 * Clean up the table bitmap in this case and return
331 * DMA_ERROR_CODE. For all other errors the functionality is
332 * not altered.
333 */
334 if (unlikely(build_fail)) {
335 __iommu_free(tbl, ret, npages);
336 return DMA_ERROR_CODE;
337 }
338
339 /* Flush/invalidate TLB caches if necessary */
340 if (ppc_md.tce_flush)
341 ppc_md.tce_flush(tbl);
342
343 /* Make sure updates are seen by hardware */
344 mb();
345
346 return ret;
347}
348
349static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
350 unsigned int npages)
351{
352 unsigned long entry, free_entry;
353
354 entry = dma_addr >> tbl->it_page_shift;
355 free_entry = entry - tbl->it_offset;
356
357 if (((free_entry + npages) > tbl->it_size) ||
358 (entry < tbl->it_offset)) {
359 if (printk_ratelimit()) {
360 printk(KERN_INFO "iommu_free: invalid entry\n");
361 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
362 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
363 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
364 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
365 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
366 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
367 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
368 WARN_ON(1);
369 }
370
371 return false;
372 }
373
374 return true;
375}
376
377static struct iommu_pool *get_pool(struct iommu_table *tbl,
378 unsigned long entry)
379{
380 struct iommu_pool *p;
381 unsigned long largepool_start = tbl->large_pool.start;
382
383 /* The large pool is the last pool at the top of the table */
384 if (entry >= largepool_start) {
385 p = &tbl->large_pool;
386 } else {
387 unsigned int pool_nr = entry / tbl->poolsize;
388
389 BUG_ON(pool_nr > tbl->nr_pools);
390 p = &tbl->pools[pool_nr];
391 }
392
393 return p;
394}
395
396static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
397 unsigned int npages)
398{
399 unsigned long entry, free_entry;
400 unsigned long flags;
401 struct iommu_pool *pool;
402
403 entry = dma_addr >> tbl->it_page_shift;
404 free_entry = entry - tbl->it_offset;
405
406 pool = get_pool(tbl, free_entry);
407
408 if (!iommu_free_check(tbl, dma_addr, npages))
409 return;
410
411 ppc_md.tce_free(tbl, entry, npages);
412
413 spin_lock_irqsave(&(pool->lock), flags);
414 bitmap_clear(tbl->it_map, free_entry, npages);
415 spin_unlock_irqrestore(&(pool->lock), flags);
416}
417
418static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
419 unsigned int npages)
420{
421 __iommu_free(tbl, dma_addr, npages);
422
423 /* Make sure TLB cache is flushed if the HW needs it. We do
424 * not do an mb() here on purpose, it is not needed on any of
425 * the current platforms.
426 */
427 if (ppc_md.tce_flush)
428 ppc_md.tce_flush(tbl);
429}
430
431int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
432 struct scatterlist *sglist, int nelems,
433 unsigned long mask, enum dma_data_direction direction,
434 struct dma_attrs *attrs)
435{
436 dma_addr_t dma_next = 0, dma_addr;
437 struct scatterlist *s, *outs, *segstart;
438 int outcount, incount, i, build_fail = 0;
439 unsigned int align;
440 unsigned long handle;
441 unsigned int max_seg_size;
442
443 BUG_ON(direction == DMA_NONE);
444
445 if ((nelems == 0) || !tbl)
446 return 0;
447
448 outs = s = segstart = &sglist[0];
449 outcount = 1;
450 incount = nelems;
451 handle = 0;
452
453 /* Init first segment length for backout at failure */
454 outs->dma_length = 0;
455
456 DBG("sg mapping %d elements:\n", nelems);
457
458 max_seg_size = dma_get_max_seg_size(dev);
459 for_each_sg(sglist, s, nelems, i) {
460 unsigned long vaddr, npages, entry, slen;
461
462 slen = s->length;
463 /* Sanity check */
464 if (slen == 0) {
465 dma_next = 0;
466 continue;
467 }
468 /* Allocate iommu entries for that segment */
469 vaddr = (unsigned long) sg_virt(s);
470 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
471 align = 0;
472 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
473 (vaddr & ~PAGE_MASK) == 0)
474 align = PAGE_SHIFT - tbl->it_page_shift;
475 entry = iommu_range_alloc(dev, tbl, npages, &handle,
476 mask >> tbl->it_page_shift, align);
477
478 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
479
480 /* Handle failure */
481 if (unlikely(entry == DMA_ERROR_CODE)) {
482 if (printk_ratelimit())
483 dev_info(dev, "iommu_alloc failed, tbl %p "
484 "vaddr %lx npages %lu\n", tbl, vaddr,
485 npages);
486 goto failure;
487 }
488
489 /* Convert entry to a dma_addr_t */
490 entry += tbl->it_offset;
491 dma_addr = entry << tbl->it_page_shift;
492 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
493
494 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
495 npages, entry, dma_addr);
496
497 /* Insert into HW table */
498 build_fail = ppc_md.tce_build(tbl, entry, npages,
499 vaddr & IOMMU_PAGE_MASK(tbl),
500 direction, attrs);
501 if(unlikely(build_fail))
502 goto failure;
503
504 /* If we are in an open segment, try merging */
505 if (segstart != s) {
506 DBG(" - trying merge...\n");
507 /* We cannot merge if:
508 * - allocated dma_addr isn't contiguous to previous allocation
509 */
510 if (novmerge || (dma_addr != dma_next) ||
511 (outs->dma_length + s->length > max_seg_size)) {
512 /* Can't merge: create a new segment */
513 segstart = s;
514 outcount++;
515 outs = sg_next(outs);
516 DBG(" can't merge, new segment.\n");
517 } else {
518 outs->dma_length += s->length;
519 DBG(" merged, new len: %ux\n", outs->dma_length);
520 }
521 }
522
523 if (segstart == s) {
524 /* This is a new segment, fill entries */
525 DBG(" - filling new segment.\n");
526 outs->dma_address = dma_addr;
527 outs->dma_length = slen;
528 }
529
530 /* Calculate next page pointer for contiguous check */
531 dma_next = dma_addr + slen;
532
533 DBG(" - dma next is: %lx\n", dma_next);
534 }
535
536 /* Flush/invalidate TLB caches if necessary */
537 if (ppc_md.tce_flush)
538 ppc_md.tce_flush(tbl);
539
540 DBG("mapped %d elements:\n", outcount);
541
542 /* For the sake of iommu_unmap_sg, we clear out the length in the
543 * next entry of the sglist if we didn't fill the list completely
544 */
545 if (outcount < incount) {
546 outs = sg_next(outs);
547 outs->dma_address = DMA_ERROR_CODE;
548 outs->dma_length = 0;
549 }
550
551 /* Make sure updates are seen by hardware */
552 mb();
553
554 return outcount;
555
556 failure:
557 for_each_sg(sglist, s, nelems, i) {
558 if (s->dma_length != 0) {
559 unsigned long vaddr, npages;
560
561 vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
562 npages = iommu_num_pages(s->dma_address, s->dma_length,
563 IOMMU_PAGE_SIZE(tbl));
564 __iommu_free(tbl, vaddr, npages);
565 s->dma_address = DMA_ERROR_CODE;
566 s->dma_length = 0;
567 }
568 if (s == outs)
569 break;
570 }
571 return 0;
572}
573
574
575void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
576 int nelems, enum dma_data_direction direction,
577 struct dma_attrs *attrs)
578{
579 struct scatterlist *sg;
580
581 BUG_ON(direction == DMA_NONE);
582
583 if (!tbl)
584 return;
585
586 sg = sglist;
587 while (nelems--) {
588 unsigned int npages;
589 dma_addr_t dma_handle = sg->dma_address;
590
591 if (sg->dma_length == 0)
592 break;
593 npages = iommu_num_pages(dma_handle, sg->dma_length,
594 IOMMU_PAGE_SIZE(tbl));
595 __iommu_free(tbl, dma_handle, npages);
596 sg = sg_next(sg);
597 }
598
599 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
600 * do not do an mb() here, the affected platforms do not need it
601 * when freeing.
602 */
603 if (ppc_md.tce_flush)
604 ppc_md.tce_flush(tbl);
605}
606
607static void iommu_table_clear(struct iommu_table *tbl)
608{
609 /*
610 * In case of firmware assisted dump system goes through clean
611 * reboot process at the time of system crash. Hence it's safe to
612 * clear the TCE entries if firmware assisted dump is active.
613 */
614 if (!is_kdump_kernel() || is_fadump_active()) {
615 /* Clear the table in case firmware left allocations in it */
616 ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
617 return;
618 }
619
620#ifdef CONFIG_CRASH_DUMP
621 if (ppc_md.tce_get) {
622 unsigned long index, tceval, tcecount = 0;
623
624 /* Reserve the existing mappings left by the first kernel. */
625 for (index = 0; index < tbl->it_size; index++) {
626 tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
627 /*
628 * Freed TCE entry contains 0x7fffffffffffffff on JS20
629 */
630 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
631 __set_bit(index, tbl->it_map);
632 tcecount++;
633 }
634 }
635
636 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
637 printk(KERN_WARNING "TCE table is full; freeing ");
638 printk(KERN_WARNING "%d entries for the kdump boot\n",
639 KDUMP_MIN_TCE_ENTRIES);
640 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
641 index < tbl->it_size; index++)
642 __clear_bit(index, tbl->it_map);
643 }
644 }
645#endif
646}
647
648/*
649 * Build a iommu_table structure. This contains a bit map which
650 * is used to manage allocation of the tce space.
651 */
652struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
653{
654 unsigned long sz;
655 static int welcomed = 0;
656 struct page *page;
657 unsigned int i;
658 struct iommu_pool *p;
659
660 /* number of bytes needed for the bitmap */
661 sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
662
663 page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
664 if (!page)
665 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
666 tbl->it_map = page_address(page);
667 memset(tbl->it_map, 0, sz);
668
669 /*
670 * Reserve page 0 so it will not be used for any mappings.
671 * This avoids buggy drivers that consider page 0 to be invalid
672 * to crash the machine or even lose data.
673 */
674 if (tbl->it_offset == 0)
675 set_bit(0, tbl->it_map);
676
677 /* We only split the IOMMU table if we have 1GB or more of space */
678 if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
679 tbl->nr_pools = IOMMU_NR_POOLS;
680 else
681 tbl->nr_pools = 1;
682
683 /* We reserve the top 1/4 of the table for large allocations */
684 tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
685
686 for (i = 0; i < tbl->nr_pools; i++) {
687 p = &tbl->pools[i];
688 spin_lock_init(&(p->lock));
689 p->start = tbl->poolsize * i;
690 p->hint = p->start;
691 p->end = p->start + tbl->poolsize;
692 }
693
694 p = &tbl->large_pool;
695 spin_lock_init(&(p->lock));
696 p->start = tbl->poolsize * i;
697 p->hint = p->start;
698 p->end = tbl->it_size;
699
700 iommu_table_clear(tbl);
701
702 if (!welcomed) {
703 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
704 novmerge ? "disabled" : "enabled");
705 welcomed = 1;
706 }
707
708 return tbl;
709}
710
711void iommu_free_table(struct iommu_table *tbl, const char *node_name)
712{
713 unsigned long bitmap_sz;
714 unsigned int order;
715
716 if (!tbl || !tbl->it_map) {
717 printk(KERN_ERR "%s: expected TCE map for %s\n", __func__,
718 node_name);
719 return;
720 }
721
722 /*
723 * In case we have reserved the first bit, we should not emit
724 * the warning below.
725 */
726 if (tbl->it_offset == 0)
727 clear_bit(0, tbl->it_map);
728
729#ifdef CONFIG_IOMMU_API
730 if (tbl->it_group) {
731 iommu_group_put(tbl->it_group);
732 BUG_ON(tbl->it_group);
733 }
734#endif
735
736 /* verify that table contains no entries */
737 if (!bitmap_empty(tbl->it_map, tbl->it_size))
738 pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name);
739
740 /* calculate bitmap size in bytes */
741 bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
742
743 /* free bitmap */
744 order = get_order(bitmap_sz);
745 free_pages((unsigned long) tbl->it_map, order);
746
747 /* free table */
748 kfree(tbl);
749}
750
751/* Creates TCEs for a user provided buffer. The user buffer must be
752 * contiguous real kernel storage (not vmalloc). The address passed here
753 * comprises a page address and offset into that page. The dma_addr_t
754 * returned will point to the same byte within the page as was passed in.
755 */
756dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
757 struct page *page, unsigned long offset, size_t size,
758 unsigned long mask, enum dma_data_direction direction,
759 struct dma_attrs *attrs)
760{
761 dma_addr_t dma_handle = DMA_ERROR_CODE;
762 void *vaddr;
763 unsigned long uaddr;
764 unsigned int npages, align;
765
766 BUG_ON(direction == DMA_NONE);
767
768 vaddr = page_address(page) + offset;
769 uaddr = (unsigned long)vaddr;
770 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
771
772 if (tbl) {
773 align = 0;
774 if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
775 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
776 align = PAGE_SHIFT - tbl->it_page_shift;
777
778 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
779 mask >> tbl->it_page_shift, align,
780 attrs);
781 if (dma_handle == DMA_ERROR_CODE) {
782 if (printk_ratelimit()) {
783 dev_info(dev, "iommu_alloc failed, tbl %p "
784 "vaddr %p npages %d\n", tbl, vaddr,
785 npages);
786 }
787 } else
788 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
789 }
790
791 return dma_handle;
792}
793
794void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
795 size_t size, enum dma_data_direction direction,
796 struct dma_attrs *attrs)
797{
798 unsigned int npages;
799
800 BUG_ON(direction == DMA_NONE);
801
802 if (tbl) {
803 npages = iommu_num_pages(dma_handle, size,
804 IOMMU_PAGE_SIZE(tbl));
805 iommu_free(tbl, dma_handle, npages);
806 }
807}
808
809/* Allocates a contiguous real buffer and creates mappings over it.
810 * Returns the virtual address of the buffer and sets dma_handle
811 * to the dma address (mapping) of the first page.
812 */
813void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
814 size_t size, dma_addr_t *dma_handle,
815 unsigned long mask, gfp_t flag, int node)
816{
817 void *ret = NULL;
818 dma_addr_t mapping;
819 unsigned int order;
820 unsigned int nio_pages, io_order;
821 struct page *page;
822
823 size = PAGE_ALIGN(size);
824 order = get_order(size);
825
826 /*
827 * Client asked for way too much space. This is checked later
828 * anyway. It is easier to debug here for the drivers than in
829 * the tce tables.
830 */
831 if (order >= IOMAP_MAX_ORDER) {
832 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
833 size);
834 return NULL;
835 }
836
837 if (!tbl)
838 return NULL;
839
840 /* Alloc enough pages (and possibly more) */
841 page = alloc_pages_node(node, flag, order);
842 if (!page)
843 return NULL;
844 ret = page_address(page);
845 memset(ret, 0, size);
846
847 /* Set up tces to cover the allocated range */
848 nio_pages = size >> tbl->it_page_shift;
849 io_order = get_iommu_order(size, tbl);
850 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
851 mask >> tbl->it_page_shift, io_order, NULL);
852 if (mapping == DMA_ERROR_CODE) {
853 free_pages((unsigned long)ret, order);
854 return NULL;
855 }
856 *dma_handle = mapping;
857 return ret;
858}
859
860void iommu_free_coherent(struct iommu_table *tbl, size_t size,
861 void *vaddr, dma_addr_t dma_handle)
862{
863 if (tbl) {
864 unsigned int nio_pages;
865
866 size = PAGE_ALIGN(size);
867 nio_pages = size >> tbl->it_page_shift;
868 iommu_free(tbl, dma_handle, nio_pages);
869 size = PAGE_ALIGN(size);
870 free_pages((unsigned long)vaddr, get_order(size));
871 }
872}
873
874#ifdef CONFIG_IOMMU_API
875/*
876 * SPAPR TCE API
877 */
878static void group_release(void *iommu_data)
879{
880 struct iommu_table *tbl = iommu_data;
881 tbl->it_group = NULL;
882}
883
884void iommu_register_group(struct iommu_table *tbl,
885 int pci_domain_number, unsigned long pe_num)
886{
887 struct iommu_group *grp;
888 char *name;
889
890 grp = iommu_group_alloc();
891 if (IS_ERR(grp)) {
892 pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
893 PTR_ERR(grp));
894 return;
895 }
896 tbl->it_group = grp;
897 iommu_group_set_iommudata(grp, tbl, group_release);
898 name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
899 pci_domain_number, pe_num);
900 if (!name)
901 return;
902 iommu_group_set_name(grp, name);
903 kfree(name);
904}
905
906enum dma_data_direction iommu_tce_direction(unsigned long tce)
907{
908 if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
909 return DMA_BIDIRECTIONAL;
910 else if (tce & TCE_PCI_READ)
911 return DMA_TO_DEVICE;
912 else if (tce & TCE_PCI_WRITE)
913 return DMA_FROM_DEVICE;
914 else
915 return DMA_NONE;
916}
917EXPORT_SYMBOL_GPL(iommu_tce_direction);
918
919void iommu_flush_tce(struct iommu_table *tbl)
920{
921 /* Flush/invalidate TLB caches if necessary */
922 if (ppc_md.tce_flush)
923 ppc_md.tce_flush(tbl);
924
925 /* Make sure updates are seen by hardware */
926 mb();
927}
928EXPORT_SYMBOL_GPL(iommu_flush_tce);
929
930int iommu_tce_clear_param_check(struct iommu_table *tbl,
931 unsigned long ioba, unsigned long tce_value,
932 unsigned long npages)
933{
934 /* ppc_md.tce_free() does not support any value but 0 */
935 if (tce_value)
936 return -EINVAL;
937
938 if (ioba & ~IOMMU_PAGE_MASK(tbl))
939 return -EINVAL;
940
941 ioba >>= tbl->it_page_shift;
942 if (ioba < tbl->it_offset)
943 return -EINVAL;
944
945 if ((ioba + npages) > (tbl->it_offset + tbl->it_size))
946 return -EINVAL;
947
948 return 0;
949}
950EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
951
952int iommu_tce_put_param_check(struct iommu_table *tbl,
953 unsigned long ioba, unsigned long tce)
954{
955 if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))
956 return -EINVAL;
957
958 if (tce & ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))
959 return -EINVAL;
960
961 if (ioba & ~IOMMU_PAGE_MASK(tbl))
962 return -EINVAL;
963
964 ioba >>= tbl->it_page_shift;
965 if (ioba < tbl->it_offset)
966 return -EINVAL;
967
968 if ((ioba + 1) > (tbl->it_offset + tbl->it_size))
969 return -EINVAL;
970
971 return 0;
972}
973EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);
974
975unsigned long iommu_clear_tce(struct iommu_table *tbl, unsigned long entry)
976{
977 unsigned long oldtce;
978 struct iommu_pool *pool = get_pool(tbl, entry);
979
980 spin_lock(&(pool->lock));
981
982 oldtce = ppc_md.tce_get(tbl, entry);
983 if (oldtce & (TCE_PCI_WRITE | TCE_PCI_READ))
984 ppc_md.tce_free(tbl, entry, 1);
985 else
986 oldtce = 0;
987
988 spin_unlock(&(pool->lock));
989
990 return oldtce;
991}
992EXPORT_SYMBOL_GPL(iommu_clear_tce);
993
994int iommu_clear_tces_and_put_pages(struct iommu_table *tbl,
995 unsigned long entry, unsigned long pages)
996{
997 unsigned long oldtce;
998 struct page *page;
999
1000 for ( ; pages; --pages, ++entry) {
1001 oldtce = iommu_clear_tce(tbl, entry);
1002 if (!oldtce)
1003 continue;
1004
1005 page = pfn_to_page(oldtce >> PAGE_SHIFT);
1006 WARN_ON(!page);
1007 if (page) {
1008 if (oldtce & TCE_PCI_WRITE)
1009 SetPageDirty(page);
1010 put_page(page);
1011 }
1012 }
1013
1014 return 0;
1015}
1016EXPORT_SYMBOL_GPL(iommu_clear_tces_and_put_pages);
1017
1018/*
1019 * hwaddr is a kernel virtual address here (0xc... bazillion),
1020 * tce_build converts it to a physical address.
1021 */
1022int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
1023 unsigned long hwaddr, enum dma_data_direction direction)
1024{
1025 int ret = -EBUSY;
1026 unsigned long oldtce;
1027 struct iommu_pool *pool = get_pool(tbl, entry);
1028
1029 spin_lock(&(pool->lock));
1030
1031 oldtce = ppc_md.tce_get(tbl, entry);
1032 /* Add new entry if it is not busy */
1033 if (!(oldtce & (TCE_PCI_WRITE | TCE_PCI_READ)))
1034 ret = ppc_md.tce_build(tbl, entry, 1, hwaddr, direction, NULL);
1035
1036 spin_unlock(&(pool->lock));
1037
1038 /* if (unlikely(ret))
1039 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
1040 __func__, hwaddr, entry << IOMMU_PAGE_SHIFT(tbl),
1041 hwaddr, ret); */
1042
1043 return ret;
1044}
1045EXPORT_SYMBOL_GPL(iommu_tce_build);
1046
1047int iommu_put_tce_user_mode(struct iommu_table *tbl, unsigned long entry,
1048 unsigned long tce)
1049{
1050 int ret;
1051 struct page *page = NULL;
1052 unsigned long hwaddr, offset = tce & IOMMU_PAGE_MASK(tbl) & ~PAGE_MASK;
1053 enum dma_data_direction direction = iommu_tce_direction(tce);
1054
1055 ret = get_user_pages_fast(tce & PAGE_MASK, 1,
1056 direction != DMA_TO_DEVICE, &page);
1057 if (unlikely(ret != 1)) {
1058 /* pr_err("iommu_tce: get_user_pages_fast failed tce=%lx ioba=%lx ret=%d\n",
1059 tce, entry << IOMMU_PAGE_SHIFT(tbl), ret); */
1060 return -EFAULT;
1061 }
1062 hwaddr = (unsigned long) page_address(page) + offset;
1063
1064 ret = iommu_tce_build(tbl, entry, hwaddr, direction);
1065 if (ret)
1066 put_page(page);
1067
1068 if (ret < 0)
1069 pr_err("iommu_tce: %s failed ioba=%lx, tce=%lx, ret=%d\n",
1070 __func__, entry << tbl->it_page_shift, tce, ret);
1071
1072 return ret;
1073}
1074EXPORT_SYMBOL_GPL(iommu_put_tce_user_mode);
1075
1076int iommu_take_ownership(struct iommu_table *tbl)
1077{
1078 unsigned long sz = (tbl->it_size + 7) >> 3;
1079
1080 if (tbl->it_offset == 0)
1081 clear_bit(0, tbl->it_map);
1082
1083 if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
1084 pr_err("iommu_tce: it_map is not empty");
1085 return -EBUSY;
1086 }
1087
1088 memset(tbl->it_map, 0xff, sz);
1089 iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
1090
1091 /*
1092 * Disable iommu bypass, otherwise the user can DMA to all of
1093 * our physical memory via the bypass window instead of just
1094 * the pages that has been explicitly mapped into the iommu
1095 */
1096 if (tbl->set_bypass)
1097 tbl->set_bypass(tbl, false);
1098
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(iommu_take_ownership);
1102
1103void iommu_release_ownership(struct iommu_table *tbl)
1104{
1105 unsigned long sz = (tbl->it_size + 7) >> 3;
1106
1107 iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
1108 memset(tbl->it_map, 0, sz);
1109
1110 /* Restore bit#0 set by iommu_init_table() */
1111 if (tbl->it_offset == 0)
1112 set_bit(0, tbl->it_map);
1113
1114 /* The kernel owns the device now, we can restore the iommu bypass */
1115 if (tbl->set_bypass)
1116 tbl->set_bypass(tbl, true);
1117}
1118EXPORT_SYMBOL_GPL(iommu_release_ownership);
1119
1120int iommu_add_device(struct device *dev)
1121{
1122 struct iommu_table *tbl;
1123 int ret = 0;
1124
1125 if (WARN_ON(dev->iommu_group)) {
1126 pr_warn("iommu_tce: device %s is already in iommu group %d, skipping\n",
1127 dev_name(dev),
1128 iommu_group_id(dev->iommu_group));
1129 return -EBUSY;
1130 }
1131
1132 tbl = get_iommu_table_base(dev);
1133 if (!tbl || !tbl->it_group) {
1134 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1135 dev_name(dev));
1136 return 0;
1137 }
1138
1139 pr_debug("iommu_tce: adding %s to iommu group %d\n",
1140 dev_name(dev), iommu_group_id(tbl->it_group));
1141
1142 if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
1143 pr_err("iommu_tce: unsupported iommu page size.");
1144 pr_err("%s has not been added\n", dev_name(dev));
1145 return -EINVAL;
1146 }
1147
1148 ret = iommu_group_add_device(tbl->it_group, dev);
1149 if (ret < 0)
1150 pr_err("iommu_tce: %s has not been added, ret=%d\n",
1151 dev_name(dev), ret);
1152
1153 return ret;
1154}
1155EXPORT_SYMBOL_GPL(iommu_add_device);
1156
1157void iommu_del_device(struct device *dev)
1158{
1159 /*
1160 * Some devices might not have IOMMU table and group
1161 * and we needn't detach them from the associated
1162 * IOMMU groups
1163 */
1164 if (!dev->iommu_group) {
1165 pr_debug("iommu_tce: skipping device %s with no tbl\n",
1166 dev_name(dev));
1167 return;
1168 }
1169
1170 iommu_group_remove_device(dev);
1171}
1172EXPORT_SYMBOL_GPL(iommu_del_device);
1173
1174#endif /* CONFIG_IOMMU_API */