1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 *  FPU support code, moved here from head.S so that it can be used
  4 *  by chips which use other head-whatever.S files.
  5 *
  6 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  7 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  8 *    Copyright (C) 1996 Paul Mackerras.
  9 *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
 
 
 
 
 
 
 10 */
 11
 12#include <linux/export.h>
 13#include <asm/reg.h>
 14#include <asm/page.h>
 15#include <asm/mmu.h>
 
 16#include <asm/cputable.h>
 17#include <asm/cache.h>
 18#include <asm/thread_info.h>
 19#include <asm/ppc_asm.h>
 20#include <asm/asm-offsets.h>
 21#include <asm/ptrace.h>
 22#include <asm/asm-compat.h>
 23#include <asm/feature-fixups.h>
 24
 25#ifdef CONFIG_VSX
 26#define __REST_1FPVSR(n,c,base)						\
 27BEGIN_FTR_SECTION							\
 28	b	2f;							\
 29END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 30	REST_FPR(n,base);						\
 31	b	3f;							\
 322:	REST_VSR(n,c,base);						\
 333:
 34
 35#define __REST_32FPVSRS(n,c,base)					\
 36BEGIN_FTR_SECTION							\
 37	b	2f;							\
 38END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 39	REST_32FPRS(n,base);						\
 40	b	3f;							\
 412:	REST_32VSRS(n,c,base);						\
 423:
 43
 44#define __SAVE_32FPVSRS(n,c,base)					\
 45BEGIN_FTR_SECTION							\
 46	b	2f;							\
 47END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 48	SAVE_32FPRS(n,base);						\
 49	b	3f;							\
 502:	SAVE_32VSRS(n,c,base);						\
 513:
 52#else
 53#define __REST_1FPVSR(n,b,base)		REST_FPR(n, base)
 54#define __REST_32FPVSRS(n,b,base)	REST_32FPRS(n, base)
 55#define __SAVE_32FPVSRS(n,b,base)	SAVE_32FPRS(n, base)
 56#endif
 57#define REST_1FPVSR(n,c,base)   __REST_1FPVSR(n,__REG_##c,__REG_##base)
 58#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
 59#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
 60
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 61/*
 62 * Load state from memory into FP registers including FPSCR.
 63 * Assumes the caller has enabled FP in the MSR.
 64 */
 65_GLOBAL(load_fp_state)
 66	lfd	fr0,FPSTATE_FPSCR(r3)
 67	MTFSF_L(fr0)
 68	REST_32FPVSRS(0, R4, R3)
 69	blr
 70EXPORT_SYMBOL(load_fp_state)
 71_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */
 72
 73/*
 74 * Store FP state into memory, including FPSCR
 75 * Assumes the caller has enabled FP in the MSR.
 76 */
 77_GLOBAL(store_fp_state)
 78	SAVE_32FPVSRS(0, R4, R3)
 79	mffs	fr0
 80	stfd	fr0,FPSTATE_FPSCR(r3)
 81	REST_1FPVSR(0, R4, R3)
 82	blr
 83EXPORT_SYMBOL(store_fp_state)
 84
 85/*
 86 * This task wants to use the FPU now.
 87 * On UP, disable FP for the task which had the FPU previously,
 88 * and save its floating-point registers in its thread_struct.
 89 * Load up this task's FP registers from its thread_struct,
 90 * enable the FPU for the current task and return to the task.
 91 * Note that on 32-bit this can only use registers that will be
 92 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
 93 */
 94_GLOBAL(load_up_fpu)
 95	mfmsr	r5
 96#ifdef CONFIG_PPC_BOOK3S_64
 97	/* interrupt doesn't set MSR[RI] and HPT can fault on current access */
 98	ori	r5,r5,MSR_FP|MSR_RI
 99#else
100	ori	r5,r5,MSR_FP
101#endif
102#ifdef CONFIG_VSX
103BEGIN_FTR_SECTION
104	oris	r5,r5,MSR_VSX@h
105END_FTR_SECTION_IFSET(CPU_FTR_VSX)
106#endif
 
107	MTMSRD(r5)			/* enable use of fpu now */
108	isync
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
109	/* enable use of FP after return */
110#ifdef CONFIG_PPC32
111	addi	r5,r2,THREAD
112	lwz	r4,THREAD_FPEXC_MODE(r5)
113	ori	r9,r9,MSR_FP		/* enable FP for current */
114	or	r9,r9,r4
115#else
116	ld	r4,PACACURRENT(r13)
117	addi	r5,r4,THREAD		/* Get THREAD */
118	lwz	r4,THREAD_FPEXC_MODE(r5)
119	ori	r12,r12,MSR_FP
120	or	r12,r12,r4
121	std	r12,_MSR(r1)
122#ifdef CONFIG_PPC_BOOK3S_64
123	li	r4,0
124	stb	r4,PACASRR_VALID(r13)
125#endif
126#endif
127	li	r4,1
128	stb	r4,THREAD_LOAD_FP(r5)
129	addi	r10,r5,THREAD_FPSTATE
130	lfd	fr0,FPSTATE_FPSCR(r10)
131	MTFSF_L(fr0)
132	REST_32FPVSRS(0, R4, R10)
 
 
 
 
 
133	/* restore registers and return */
134	/* we haven't used ctr or xer or lr */
135	blr
136_ASM_NOKPROBE_SYMBOL(load_up_fpu)
137
138/*
139 * save_fpu(tsk)
140 * Save the floating-point registers in its thread_struct.
 
141 * Enables the FPU for use in the kernel on return.
142 */
143_GLOBAL(save_fpu)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
144	addi	r3,r3,THREAD	        /* want THREAD of task */
145	PPC_LL	r6,THREAD_FPSAVEAREA(r3)
146	PPC_LL	r5,PT_REGS(r3)
147	PPC_LCMPI	0,r6,0
148	bne	2f
149	addi	r6,r3,THREAD_FPSTATE
1502:	SAVE_32FPVSRS(0, R4, R6)
 
151	mffs	fr0
152	stfd	fr0,FPSTATE_FPSCR(r6)
153	REST_1FPVSR(0, R4, R6)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
154	blr

 
  1/*
  2 *  FPU support code, moved here from head.S so that it can be used
  3 *  by chips which use other head-whatever.S files.
  4 *
  5 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  6 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  7 *    Copyright (C) 1996 Paul Mackerras.
  8 *    Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  9 *
 10 *  This program is free software; you can redistribute it and/or
 11 *  modify it under the terms of the GNU General Public License
 12 *  as published by the Free Software Foundation; either version
 13 *  2 of the License, or (at your option) any later version.
 14 *
 15 */
 16
 
 17#include <asm/reg.h>
 18#include <asm/page.h>
 19#include <asm/mmu.h>
 20#include <asm/pgtable.h>
 21#include <asm/cputable.h>
 22#include <asm/cache.h>
 23#include <asm/thread_info.h>
 24#include <asm/ppc_asm.h>
 25#include <asm/asm-offsets.h>
 26#include <asm/ptrace.h>
 
 
 27
 28#ifdef CONFIG_VSX
 
 
 
 
 
 
 
 
 
 29#define __REST_32FPVSRS(n,c,base)					\
 30BEGIN_FTR_SECTION							\
 31	b	2f;							\
 32END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 33	REST_32FPRS(n,base);						\
 34	b	3f;							\
 352:	REST_32VSRS(n,c,base);						\
 363:
 37
 38#define __SAVE_32FPVSRS(n,c,base)					\
 39BEGIN_FTR_SECTION							\
 40	b	2f;							\
 41END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 42	SAVE_32FPRS(n,base);						\
 43	b	3f;							\
 442:	SAVE_32VSRS(n,c,base);						\
 453:
 46#else
 
 47#define __REST_32FPVSRS(n,b,base)	REST_32FPRS(n, base)
 48#define __SAVE_32FPVSRS(n,b,base)	SAVE_32FPRS(n, base)
 49#endif
 
 50#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
 51#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
 52
 53#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 54/* void do_load_up_transact_fpu(struct thread_struct *thread)
 55 *
 56 * This is similar to load_up_fpu but for the transactional version of the FP
 57 * register set.  It doesn't mess with the task MSR or valid flags.
 58 * Furthermore, we don't do lazy FP with TM currently.
 59 */
 60_GLOBAL(do_load_up_transact_fpu)
 61	mfmsr	r6
 62	ori	r5,r6,MSR_FP
 63#ifdef CONFIG_VSX
 64BEGIN_FTR_SECTION
 65	oris	r5,r5,MSR_VSX@h
 66END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 67#endif
 68	SYNC
 69	MTMSRD(r5)
 70
 71	addi	r7,r3,THREAD_TRANSACT_FPSTATE
 72	lfd	fr0,FPSTATE_FPSCR(r7)
 73	MTFSF_L(fr0)
 74	REST_32FPVSRS(0, R4, R7)
 75
 76	/* FP/VSX off again */
 77	MTMSRD(r6)
 78	SYNC
 79
 80	blr
 81#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 82
 83/*
 84 * Enable use of the FPU, and VSX if possible, for the caller.
 85 */
 86_GLOBAL(fp_enable)
 87	mfmsr	r3
 88	ori	r3,r3,MSR_FP
 89#ifdef CONFIG_VSX
 90BEGIN_FTR_SECTION
 91	oris	r3,r3,MSR_VSX@h
 92END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 93#endif
 94	SYNC
 95	MTMSRD(r3)
 96	isync			/* (not necessary for arch 2.02 and later) */
 97	blr
 98
 99/*
100 * Load state from memory into FP registers including FPSCR.
101 * Assumes the caller has enabled FP in the MSR.
102 */
103_GLOBAL(load_fp_state)
104	lfd	fr0,FPSTATE_FPSCR(r3)
105	MTFSF_L(fr0)
106	REST_32FPVSRS(0, R4, R3)
107	blr
 
 
108
109/*
110 * Store FP state into memory, including FPSCR
111 * Assumes the caller has enabled FP in the MSR.
112 */
113_GLOBAL(store_fp_state)
114	SAVE_32FPVSRS(0, R4, R3)
115	mffs	fr0
116	stfd	fr0,FPSTATE_FPSCR(r3)
 
117	blr
 
118
119/*
120 * This task wants to use the FPU now.
121 * On UP, disable FP for the task which had the FPU previously,
122 * and save its floating-point registers in its thread_struct.
123 * Load up this task's FP registers from its thread_struct,
124 * enable the FPU for the current task and return to the task.
125 * Note that on 32-bit this can only use registers that will be
126 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
127 */
128_GLOBAL(load_up_fpu)
129	mfmsr	r5
 
 
 
 
130	ori	r5,r5,MSR_FP
 
131#ifdef CONFIG_VSX
132BEGIN_FTR_SECTION
133	oris	r5,r5,MSR_VSX@h
134END_FTR_SECTION_IFSET(CPU_FTR_VSX)
135#endif
136	SYNC
137	MTMSRD(r5)			/* enable use of fpu now */
138	isync
139/*
140 * For SMP, we don't do lazy FPU switching because it just gets too
141 * horrendously complex, especially when a task switches from one CPU
142 * to another.  Instead we call giveup_fpu in switch_to.
143 */
144#ifndef CONFIG_SMP
145	LOAD_REG_ADDRBASE(r3, last_task_used_math)
146	toreal(r3)
147	PPC_LL	r4,ADDROFF(last_task_used_math)(r3)
148	PPC_LCMPI	0,r4,0
149	beq	1f
150	toreal(r4)
151	addi	r4,r4,THREAD		/* want last_task_used_math->thread */
152	addi	r10,r4,THREAD_FPSTATE
153	SAVE_32FPVSRS(0, R5, R10)
154	mffs	fr0
155	stfd	fr0,FPSTATE_FPSCR(r10)
156	PPC_LL	r5,PT_REGS(r4)
157	toreal(r5)
158	PPC_LL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
159	li	r10,MSR_FP|MSR_FE0|MSR_FE1
160	andc	r4,r4,r10		/* disable FP for previous task */
161	PPC_STL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1621:
163#endif /* CONFIG_SMP */
164	/* enable use of FP after return */
165#ifdef CONFIG_PPC32
166	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
167	lwz	r4,THREAD_FPEXC_MODE(r5)
168	ori	r9,r9,MSR_FP		/* enable FP for current */
169	or	r9,r9,r4
170#else
171	ld	r4,PACACURRENT(r13)
172	addi	r5,r4,THREAD		/* Get THREAD */
173	lwz	r4,THREAD_FPEXC_MODE(r5)
174	ori	r12,r12,MSR_FP
175	or	r12,r12,r4
176	std	r12,_MSR(r1)
 
 
 
 
177#endif
 
 
178	addi	r10,r5,THREAD_FPSTATE
179	lfd	fr0,FPSTATE_FPSCR(r10)
180	MTFSF_L(fr0)
181	REST_32FPVSRS(0, R4, R10)
182#ifndef CONFIG_SMP
183	subi	r4,r5,THREAD
184	fromreal(r4)
185	PPC_STL	r4,ADDROFF(last_task_used_math)(r3)
186#endif /* CONFIG_SMP */
187	/* restore registers and return */
188	/* we haven't used ctr or xer or lr */
189	blr
 
190
191/*
192 * giveup_fpu(tsk)
193 * Disable FP for the task given as the argument,
194 * and save the floating-point registers in its thread_struct.
195 * Enables the FPU for use in the kernel on return.
196 */
197_GLOBAL(giveup_fpu)
198	mfmsr	r5
199	ori	r5,r5,MSR_FP
200#ifdef CONFIG_VSX
201BEGIN_FTR_SECTION
202	oris	r5,r5,MSR_VSX@h
203END_FTR_SECTION_IFSET(CPU_FTR_VSX)
204#endif
205	SYNC_601
206	ISYNC_601
207	MTMSRD(r5)			/* enable use of fpu now */
208	SYNC_601
209	isync
210	PPC_LCMPI	0,r3,0
211	beqlr-				/* if no previous owner, done */
212	addi	r3,r3,THREAD	        /* want THREAD of task */
213	PPC_LL	r6,THREAD_FPSAVEAREA(r3)
214	PPC_LL	r5,PT_REGS(r3)
215	PPC_LCMPI	0,r6,0
216	bne	2f
217	addi	r6,r3,THREAD_FPSTATE
2182:	PPC_LCMPI	0,r5,0
219	SAVE_32FPVSRS(0, R4, R6)
220	mffs	fr0
221	stfd	fr0,FPSTATE_FPSCR(r6)
222	beq	1f
223	PPC_LL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
224	li	r3,MSR_FP|MSR_FE0|MSR_FE1
225#ifdef CONFIG_VSX
226BEGIN_FTR_SECTION
227	oris	r3,r3,MSR_VSX@h
228END_FTR_SECTION_IFSET(CPU_FTR_VSX)
229#endif
230	andc	r4,r4,r3		/* disable FP for previous task */
231	PPC_STL	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
2321:
233#ifndef CONFIG_SMP
234	li	r5,0
235	LOAD_REG_ADDRBASE(r4,last_task_used_math)
236	PPC_STL	r5,ADDROFF(last_task_used_math)(r4)
237#endif /* CONFIG_SMP */
238	blr
239
240/*
241 * These are used in the alignment trap handler when emulating
242 * single-precision loads and stores.
243 */
244
245_GLOBAL(cvt_fd)
246	lfs	0,0(r3)
247	stfd	0,0(r4)
248	blr
249
250_GLOBAL(cvt_df)
251	lfd	0,0(r3)
252	stfs	0,0(r4)
253	blr