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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8378E RDB Device Tree Source
4 *
5 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/ {
11 compatible = "fsl,mpc8378rdb";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 serial0 = &serial0;
19 serial1 = &serial1;
20 pci0 = &pci0;
21 pci1 = &pci1;
22 pci2 = &pci2;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,8378@0 {
30 device_type = "cpu";
31 reg = <0x0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <0x00000000 0x10000000>; // 256MB at 0
45 };
46
47 localbus@e0005000 {
48 #address-cells = <2>;
49 #size-cells = <1>;
50 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>;
54
55 // CS0 and CS1 are swapped when
56 // booting from nand, but the
57 // addresses are the same.
58 ranges = <0x0 0x0 0xfe000000 0x00800000
59 0x1 0x0 0xe0600000 0x00008000
60 0x2 0x0 0xf0000000 0x00020000
61 0x3 0x0 0xfa000000 0x00008000>;
62
63 flash@0,0 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x800000>;
68 bank-width = <2>;
69 device-width = <1>;
70 };
71
72 nand@1,0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,mpc8378-fcm-nand",
76 "fsl,elbc-fcm-nand";
77 reg = <0x1 0x0 0x8000>;
78
79 u-boot@0 {
80 reg = <0x0 0x100000>;
81 read-only;
82 };
83
84 kernel@100000 {
85 reg = <0x100000 0x300000>;
86 };
87 fs@400000 {
88 reg = <0x400000 0x1c00000>;
89 };
90 };
91 };
92
93 immr@e0000000 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 compatible = "simple-bus";
98 ranges = <0x0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
101
102 wdt@200 {
103 device_type = "watchdog";
104 compatible = "mpc83xx_wdt";
105 reg = <0x200 0x100>;
106 };
107
108 gpio1: gpio-controller@c00 {
109 #gpio-cells = <2>;
110 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
111 reg = <0xc00 0x100>;
112 interrupts = <74 0x8>;
113 interrupt-parent = <&ipic>;
114 gpio-controller;
115 };
116
117 gpio2: gpio-controller@d00 {
118 #gpio-cells = <2>;
119 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
120 reg = <0xd00 0x100>;
121 interrupts = <75 0x8>;
122 interrupt-parent = <&ipic>;
123 gpio-controller;
124 };
125
126 sleep-nexus {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
130 sleep = <&pmc 0x0c000000>;
131 ranges;
132
133 i2c@3000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 cell-index = <0>;
137 compatible = "fsl-i2c";
138 reg = <0x3000 0x100>;
139 interrupts = <14 0x8>;
140 interrupt-parent = <&ipic>;
141 dfsrr;
142
143 dtt@48 {
144 compatible = "national,lm75";
145 reg = <0x48>;
146 };
147
148 at24@50 {
149 compatible = "atmel,24c256";
150 reg = <0x50>;
151 };
152
153 rtc@68 {
154 compatible = "dallas,ds1339";
155 reg = <0x68>;
156 };
157
158 mcu_pio: mcu@a {
159 #gpio-cells = <2>;
160 compatible = "fsl,mc9s08qg8-mpc8378erdb",
161 "fsl,mcu-mpc8349emitx";
162 reg = <0x0a>;
163 gpio-controller;
164 };
165 };
166
167 sdhci@2e000 {
168 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
169 reg = <0x2e000 0x1000>;
170 interrupts = <42 0x8>;
171 interrupt-parent = <&ipic>;
172 sdhci,wp-inverted;
173 /* Filled in by U-Boot */
174 clock-frequency = <111111111>;
175 };
176 };
177
178 i2c@3100 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 cell-index = <1>;
182 compatible = "fsl-i2c";
183 reg = <0x3100 0x100>;
184 interrupts = <15 0x8>;
185 interrupt-parent = <&ipic>;
186 dfsrr;
187 };
188
189 spi@7000 {
190 cell-index = <0>;
191 compatible = "fsl,spi";
192 reg = <0x7000 0x1000>;
193 interrupts = <16 0x8>;
194 interrupt-parent = <&ipic>;
195 mode = "cpu";
196 };
197
198 dma@82a8 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
202 reg = <0x82a8 4>;
203 ranges = <0 0x8100 0x1a8>;
204 interrupt-parent = <&ipic>;
205 interrupts = <71 8>;
206 cell-index = <0>;
207 dma-channel@0 {
208 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
209 reg = <0 0x80>;
210 cell-index = <0>;
211 interrupt-parent = <&ipic>;
212 interrupts = <71 8>;
213 };
214 dma-channel@80 {
215 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
216 reg = <0x80 0x80>;
217 cell-index = <1>;
218 interrupt-parent = <&ipic>;
219 interrupts = <71 8>;
220 };
221 dma-channel@100 {
222 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
223 reg = <0x100 0x80>;
224 cell-index = <2>;
225 interrupt-parent = <&ipic>;
226 interrupts = <71 8>;
227 };
228 dma-channel@180 {
229 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
230 reg = <0x180 0x28>;
231 cell-index = <3>;
232 interrupt-parent = <&ipic>;
233 interrupts = <71 8>;
234 };
235 };
236
237 usb@23000 {
238 compatible = "fsl-usb2-dr";
239 reg = <0x23000 0x1000>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 interrupt-parent = <&ipic>;
243 interrupts = <38 0x8>;
244 phy_type = "ulpi";
245 sleep = <&pmc 0x00c00000>;
246 };
247
248 enet0: ethernet@24000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <0>;
252 device_type = "network";
253 model = "eTSEC";
254 compatible = "gianfar";
255 reg = <0x24000 0x1000>;
256 ranges = <0x0 0x24000 0x1000>;
257 local-mac-address = [ 00 00 00 00 00 00 ];
258 interrupts = <32 0x8 33 0x8 34 0x8>;
259 phy-connection-type = "mii";
260 interrupt-parent = <&ipic>;
261 tbi-handle = <&tbi0>;
262 phy-handle = <&phy2>;
263 sleep = <&pmc 0xc0000000>;
264 fsl,magic-packet;
265
266 mdio@520 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "fsl,gianfar-mdio";
270 reg = <0x520 0x20>;
271
272 phy2: ethernet-phy@2 {
273 interrupt-parent = <&ipic>;
274 interrupts = <17 0x8>;
275 reg = <0x2>;
276 };
277
278 tbi0: tbi-phy@11 {
279 reg = <0x11>;
280 device_type = "tbi-phy";
281 };
282 };
283 };
284
285 enet1: ethernet@25000 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 cell-index = <1>;
289 device_type = "network";
290 model = "eTSEC";
291 compatible = "gianfar";
292 reg = <0x25000 0x1000>;
293 ranges = <0x0 0x25000 0x1000>;
294 local-mac-address = [ 00 00 00 00 00 00 ];
295 interrupts = <35 0x8 36 0x8 37 0x8>;
296 phy-connection-type = "mii";
297 interrupt-parent = <&ipic>;
298 fixed-link = <1 1 1000 0 0>;
299 tbi-handle = <&tbi1>;
300 sleep = <&pmc 0x30000000>;
301 fsl,magic-packet;
302
303 mdio@520 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "fsl,gianfar-tbi";
307 reg = <0x520 0x20>;
308
309 tbi1: tbi-phy@11 {
310 reg = <0x11>;
311 device_type = "tbi-phy";
312 };
313 };
314 };
315
316 serial0: serial@4500 {
317 cell-index = <0>;
318 device_type = "serial";
319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4500 0x100>;
321 clock-frequency = <0>;
322 interrupts = <9 0x8>;
323 interrupt-parent = <&ipic>;
324 };
325
326 serial1: serial@4600 {
327 cell-index = <1>;
328 device_type = "serial";
329 compatible = "fsl,ns16550", "ns16550";
330 reg = <0x4600 0x100>;
331 clock-frequency = <0>;
332 interrupts = <10 0x8>;
333 interrupt-parent = <&ipic>;
334 };
335
336 crypto@30000 {
337 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
338 "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000>;
340 interrupts = <11 0x8>;
341 interrupt-parent = <&ipic>;
342 fsl,num-channels = <4>;
343 fsl,channel-fifo-len = <24>;
344 fsl,exec-units-mask = <0x9fe>;
345 fsl,descriptor-types-mask = <0x3ab0ebf>;
346 sleep = <&pmc 0x03000000>;
347 };
348
349 /* IPIC
350 * interrupts cell = <intr #, sense>
351 * sense values match linux IORESOURCE_IRQ_* defines:
352 * sense == 8: Level, low assertion
353 * sense == 2: Edge, high-to-low change
354 */
355 ipic: interrupt-controller@700 {
356 compatible = "fsl,ipic";
357 interrupt-controller;
358 #address-cells = <0>;
359 #interrupt-cells = <2>;
360 reg = <0x700 0x100>;
361 };
362
363 pmc: power@b00 {
364 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
365 reg = <0xb00 0x100 0xa00 0x100>;
366 interrupts = <80 0x8>;
367 interrupt-parent = <&ipic>;
368 };
369 };
370
371 pci0: pci@e0008500 {
372 interrupt-map-mask = <0xf800 0 0 7>;
373 interrupt-map = <
374 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
375
376 /* IDSEL AD14 IRQ6 inta */
377 0x7000 0x0 0x0 0x1 &ipic 22 0x8
378
379 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
380 0x7800 0x0 0x0 0x1 &ipic 21 0x8
381 0x7800 0x0 0x0 0x2 &ipic 22 0x8
382 0x7800 0x0 0x0 0x4 &ipic 23 0x8
383
384 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
385 0xE000 0x0 0x0 0x1 &ipic 23 0x8
386 0xE000 0x0 0x0 0x2 &ipic 21 0x8
387 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
388 interrupt-parent = <&ipic>;
389 interrupts = <66 0x8>;
390 bus-range = <0 0>;
391 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
392 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
393 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
394 sleep = <&pmc 0x00010000>;
395 clock-frequency = <66666666>;
396 #interrupt-cells = <1>;
397 #size-cells = <2>;
398 #address-cells = <3>;
399 reg = <0xe0008500 0x100 /* internal registers */
400 0xe0008300 0x8>; /* config space access registers */
401 compatible = "fsl,mpc8349-pci";
402 device_type = "pci";
403 };
404
405 pci1: pcie@e0009000 {
406 #address-cells = <3>;
407 #size-cells = <2>;
408 #interrupt-cells = <1>;
409 device_type = "pci";
410 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
411 reg = <0xe0009000 0x00001000>;
412 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
413 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
414 bus-range = <0 255>;
415 interrupt-map-mask = <0xf800 0 0 7>;
416 interrupt-map = <0 0 0 1 &ipic 1 8
417 0 0 0 2 &ipic 1 8
418 0 0 0 3 &ipic 1 8
419 0 0 0 4 &ipic 1 8>;
420 sleep = <&pmc 0x00300000>;
421 clock-frequency = <0>;
422
423 pcie@0 {
424 #address-cells = <3>;
425 #size-cells = <2>;
426 device_type = "pci";
427 reg = <0 0 0 0 0>;
428 ranges = <0x02000000 0 0xa8000000
429 0x02000000 0 0xa8000000
430 0 0x10000000
431 0x01000000 0 0x00000000
432 0x01000000 0 0x00000000
433 0 0x00800000>;
434 };
435 };
436
437 pci2: pcie@e000a000 {
438 #address-cells = <3>;
439 #size-cells = <2>;
440 #interrupt-cells = <1>;
441 device_type = "pci";
442 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
443 reg = <0xe000a000 0x00001000>;
444 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
445 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
446 bus-range = <0 255>;
447 interrupt-map-mask = <0xf800 0 0 7>;
448 interrupt-map = <0 0 0 1 &ipic 2 8
449 0 0 0 2 &ipic 2 8
450 0 0 0 3 &ipic 2 8
451 0 0 0 4 &ipic 2 8>;
452 sleep = <&pmc 0x000c0000>;
453 clock-frequency = <0>;
454
455 pcie@0 {
456 #address-cells = <3>;
457 #size-cells = <2>;
458 device_type = "pci";
459 reg = <0 0 0 0 0>;
460 ranges = <0x02000000 0 0xc8000000
461 0x02000000 0 0xc8000000
462 0 0x10000000
463 0x01000000 0 0x00000000
464 0x01000000 0 0x00000000
465 0 0x00800000>;
466 };
467 };
468
469 leds {
470 compatible = "gpio-leds";
471
472 pwr {
473 gpios = <&mcu_pio 0 0>;
474 default-state = "on";
475 };
476
477 hdd {
478 gpios = <&mcu_pio 1 0>;
479 linux,default-trigger = "disk-activity";
480 };
481 };
482};
1/*
2 * MPC8378E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "fsl,mpc8378rdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8378@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
49 };
50
51 localbus@e0005000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
58
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00008000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
66
67 flash@0,0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
72 bank-width = <2>;
73 device-width = <1>;
74 };
75
76 nand@1,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,mpc8378-fcm-nand",
80 "fsl,elbc-fcm-nand";
81 reg = <0x1 0x0 0x8000>;
82
83 u-boot@0 {
84 reg = <0x0 0x100000>;
85 read-only;
86 };
87
88 kernel@100000 {
89 reg = <0x100000 0x300000>;
90 };
91 fs@400000 {
92 reg = <0x400000 0x1c00000>;
93 };
94 };
95 };
96
97 immr@e0000000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 device_type = "soc";
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
104 bus-frequency = <0>;
105
106 wdt@200 {
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
109 reg = <0x200 0x100>;
110 };
111
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
120
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
129
130 sleep-nexus {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 sleep = <&pmc 0x0c000000>;
135 ranges;
136
137 i2c@3000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 cell-index = <0>;
141 compatible = "fsl-i2c";
142 reg = <0x3000 0x100>;
143 interrupts = <14 0x8>;
144 interrupt-parent = <&ipic>;
145 dfsrr;
146
147 dtt@48 {
148 compatible = "national,lm75";
149 reg = <0x48>;
150 };
151
152 at24@50 {
153 compatible = "at24,24c256";
154 reg = <0x50>;
155 };
156
157 rtc@68 {
158 compatible = "dallas,ds1339";
159 reg = <0x68>;
160 };
161
162 mcu_pio: mcu@a {
163 #gpio-cells = <2>;
164 compatible = "fsl,mc9s08qg8-mpc8378erdb",
165 "fsl,mcu-mpc8349emitx";
166 reg = <0x0a>;
167 gpio-controller;
168 };
169 };
170
171 sdhci@2e000 {
172 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
173 reg = <0x2e000 0x1000>;
174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>;
176 sdhci,wp-inverted;
177 /* Filled in by U-Boot */
178 clock-frequency = <111111111>;
179 };
180 };
181
182 i2c@3100 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 cell-index = <1>;
186 compatible = "fsl-i2c";
187 reg = <0x3100 0x100>;
188 interrupts = <15 0x8>;
189 interrupt-parent = <&ipic>;
190 dfsrr;
191 };
192
193 spi@7000 {
194 cell-index = <0>;
195 compatible = "fsl,spi";
196 reg = <0x7000 0x1000>;
197 interrupts = <16 0x8>;
198 interrupt-parent = <&ipic>;
199 mode = "cpu";
200 };
201
202 dma@82a8 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
206 reg = <0x82a8 4>;
207 ranges = <0 0x8100 0x1a8>;
208 interrupt-parent = <&ipic>;
209 interrupts = <71 8>;
210 cell-index = <0>;
211 dma-channel@0 {
212 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
213 reg = <0 0x80>;
214 cell-index = <0>;
215 interrupt-parent = <&ipic>;
216 interrupts = <71 8>;
217 };
218 dma-channel@80 {
219 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
220 reg = <0x80 0x80>;
221 cell-index = <1>;
222 interrupt-parent = <&ipic>;
223 interrupts = <71 8>;
224 };
225 dma-channel@100 {
226 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
227 reg = <0x100 0x80>;
228 cell-index = <2>;
229 interrupt-parent = <&ipic>;
230 interrupts = <71 8>;
231 };
232 dma-channel@180 {
233 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
234 reg = <0x180 0x28>;
235 cell-index = <3>;
236 interrupt-parent = <&ipic>;
237 interrupts = <71 8>;
238 };
239 };
240
241 usb@23000 {
242 compatible = "fsl-usb2-dr";
243 reg = <0x23000 0x1000>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 interrupt-parent = <&ipic>;
247 interrupts = <38 0x8>;
248 phy_type = "ulpi";
249 sleep = <&pmc 0x00c00000>;
250 };
251
252 enet0: ethernet@24000 {
253 #address-cells = <1>;
254 #size-cells = <1>;
255 cell-index = <0>;
256 device_type = "network";
257 model = "eTSEC";
258 compatible = "gianfar";
259 reg = <0x24000 0x1000>;
260 ranges = <0x0 0x24000 0x1000>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupts = <32 0x8 33 0x8 34 0x8>;
263 phy-connection-type = "mii";
264 interrupt-parent = <&ipic>;
265 tbi-handle = <&tbi0>;
266 phy-handle = <&phy2>;
267 sleep = <&pmc 0xc0000000>;
268 fsl,magic-packet;
269
270 mdio@520 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "fsl,gianfar-mdio";
274 reg = <0x520 0x20>;
275
276 phy2: ethernet-phy@2 {
277 interrupt-parent = <&ipic>;
278 interrupts = <17 0x8>;
279 reg = <0x2>;
280 };
281
282 tbi0: tbi-phy@11 {
283 reg = <0x11>;
284 device_type = "tbi-phy";
285 };
286 };
287 };
288
289 enet1: ethernet@25000 {
290 #address-cells = <1>;
291 #size-cells = <1>;
292 cell-index = <1>;
293 device_type = "network";
294 model = "eTSEC";
295 compatible = "gianfar";
296 reg = <0x25000 0x1000>;
297 ranges = <0x0 0x25000 0x1000>;
298 local-mac-address = [ 00 00 00 00 00 00 ];
299 interrupts = <35 0x8 36 0x8 37 0x8>;
300 phy-connection-type = "mii";
301 interrupt-parent = <&ipic>;
302 fixed-link = <1 1 1000 0 0>;
303 tbi-handle = <&tbi1>;
304 sleep = <&pmc 0x30000000>;
305 fsl,magic-packet;
306
307 mdio@520 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "fsl,gianfar-tbi";
311 reg = <0x520 0x20>;
312
313 tbi1: tbi-phy@11 {
314 reg = <0x11>;
315 device_type = "tbi-phy";
316 };
317 };
318 };
319
320 serial0: serial@4500 {
321 cell-index = <0>;
322 device_type = "serial";
323 compatible = "fsl,ns16550", "ns16550";
324 reg = <0x4500 0x100>;
325 clock-frequency = <0>;
326 interrupts = <9 0x8>;
327 interrupt-parent = <&ipic>;
328 };
329
330 serial1: serial@4600 {
331 cell-index = <1>;
332 device_type = "serial";
333 compatible = "fsl,ns16550", "ns16550";
334 reg = <0x4600 0x100>;
335 clock-frequency = <0>;
336 interrupts = <10 0x8>;
337 interrupt-parent = <&ipic>;
338 };
339
340 crypto@30000 {
341 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
342 "fsl,sec2.1", "fsl,sec2.0";
343 reg = <0x30000 0x10000>;
344 interrupts = <11 0x8>;
345 interrupt-parent = <&ipic>;
346 fsl,num-channels = <4>;
347 fsl,channel-fifo-len = <24>;
348 fsl,exec-units-mask = <0x9fe>;
349 fsl,descriptor-types-mask = <0x3ab0ebf>;
350 sleep = <&pmc 0x03000000>;
351 };
352
353 /* IPIC
354 * interrupts cell = <intr #, sense>
355 * sense values match linux IORESOURCE_IRQ_* defines:
356 * sense == 8: Level, low assertion
357 * sense == 2: Edge, high-to-low change
358 */
359 ipic: interrupt-controller@700 {
360 compatible = "fsl,ipic";
361 interrupt-controller;
362 #address-cells = <0>;
363 #interrupt-cells = <2>;
364 reg = <0x700 0x100>;
365 };
366
367 pmc: power@b00 {
368 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
369 reg = <0xb00 0x100 0xa00 0x100>;
370 interrupts = <80 0x8>;
371 interrupt-parent = <&ipic>;
372 };
373 };
374
375 pci0: pci@e0008500 {
376 interrupt-map-mask = <0xf800 0 0 7>;
377 interrupt-map = <
378 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
379
380 /* IDSEL AD14 IRQ6 inta */
381 0x7000 0x0 0x0 0x1 &ipic 22 0x8
382
383 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
384 0x7800 0x0 0x0 0x1 &ipic 21 0x8
385 0x7800 0x0 0x0 0x2 &ipic 22 0x8
386 0x7800 0x0 0x0 0x4 &ipic 23 0x8
387
388 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
389 0xE000 0x0 0x0 0x1 &ipic 23 0x8
390 0xE000 0x0 0x0 0x2 &ipic 21 0x8
391 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
392 interrupt-parent = <&ipic>;
393 interrupts = <66 0x8>;
394 bus-range = <0 0>;
395 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
396 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
397 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
398 sleep = <&pmc 0x00010000>;
399 clock-frequency = <66666666>;
400 #interrupt-cells = <1>;
401 #size-cells = <2>;
402 #address-cells = <3>;
403 reg = <0xe0008500 0x100 /* internal registers */
404 0xe0008300 0x8>; /* config space access registers */
405 compatible = "fsl,mpc8349-pci";
406 device_type = "pci";
407 };
408
409 pci1: pcie@e0009000 {
410 #address-cells = <3>;
411 #size-cells = <2>;
412 #interrupt-cells = <1>;
413 device_type = "pci";
414 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
415 reg = <0xe0009000 0x00001000>;
416 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
417 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
418 bus-range = <0 255>;
419 interrupt-map-mask = <0xf800 0 0 7>;
420 interrupt-map = <0 0 0 1 &ipic 1 8
421 0 0 0 2 &ipic 1 8
422 0 0 0 3 &ipic 1 8
423 0 0 0 4 &ipic 1 8>;
424 sleep = <&pmc 0x00300000>;
425 clock-frequency = <0>;
426
427 pcie@0 {
428 #address-cells = <3>;
429 #size-cells = <2>;
430 device_type = "pci";
431 reg = <0 0 0 0 0>;
432 ranges = <0x02000000 0 0xa8000000
433 0x02000000 0 0xa8000000
434 0 0x10000000
435 0x01000000 0 0x00000000
436 0x01000000 0 0x00000000
437 0 0x00800000>;
438 };
439 };
440
441 pci2: pcie@e000a000 {
442 #address-cells = <3>;
443 #size-cells = <2>;
444 #interrupt-cells = <1>;
445 device_type = "pci";
446 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
447 reg = <0xe000a000 0x00001000>;
448 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
449 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
450 bus-range = <0 255>;
451 interrupt-map-mask = <0xf800 0 0 7>;
452 interrupt-map = <0 0 0 1 &ipic 2 8
453 0 0 0 2 &ipic 2 8
454 0 0 0 3 &ipic 2 8
455 0 0 0 4 &ipic 2 8>;
456 sleep = <&pmc 0x000c0000>;
457 clock-frequency = <0>;
458
459 pcie@0 {
460 #address-cells = <3>;
461 #size-cells = <2>;
462 device_type = "pci";
463 reg = <0 0 0 0 0>;
464 ranges = <0x02000000 0 0xc8000000
465 0x02000000 0 0xc8000000
466 0 0x10000000
467 0x01000000 0 0x00000000
468 0x01000000 0 0x00000000
469 0 0x00800000>;
470 };
471 };
472
473 leds {
474 compatible = "gpio-leds";
475
476 pwr {
477 gpios = <&mcu_pio 0 0>;
478 default-state = "on";
479 };
480
481 hdd {
482 gpios = <&mcu_pio 1 0>;
483 linux,default-trigger = "ide-disk";
484 };
485 };
486};