1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 2003, 07 Ralf Baechle
 7 */
 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10
11#include <asm/cpu.h>
12
13/*
14 * IP27 only comes with R1x000 family processors, all using the same config
15 */
16#define cpu_has_tlb			1
17#define cpu_has_tlbinv			0
18#define cpu_has_segments		0
19#define cpu_has_eva			0
20#define cpu_has_htw			0
21#define cpu_has_rixiex			0
22#define cpu_has_maar			0
23#define cpu_has_rw_llb			0
24#define cpu_has_3kex			0
25#define cpu_has_4kex			1
26#define cpu_has_3k_cache		0
27#define cpu_has_4k_cache		1
28#define cpu_has_nofpuex			0
29#define cpu_has_32fpr			1
30#define cpu_has_counter			1
31#define cpu_has_watch			1
32#define cpu_has_64bits			1
33#define cpu_has_divec			0
34#define cpu_has_vce			0
35#define cpu_has_cache_cdex_p		0
36#define cpu_has_cache_cdex_s		0
37#define cpu_has_prefetch		1
38#define cpu_has_mcheck			0
39#define cpu_has_ejtag			0
40#define cpu_has_llsc			1
41#define cpu_has_mips16			0
42#define cpu_has_mips16e2		0
43#define cpu_has_mdmx			0
44#define cpu_has_mips3d			0
45#define cpu_has_smartmips		0
46#define cpu_has_rixi			0
47#define cpu_has_xpa			0
48#define cpu_has_vtag_icache		0
49#define cpu_has_dc_aliases		0
50#define cpu_has_ic_fills_f_dc		0
51
 
 
 
 
 
 
52#define cpu_icache_snoops_remote_store	1
 
 
 
 
 
 
 
 
 
 
 
 
53
54#define cpu_has_mips32r1		0
55#define cpu_has_mips32r2		0
56#define cpu_has_mips64r1		0
57#define cpu_has_mips64r2		0
58#define cpu_has_mips32r6		0
59#define cpu_has_mips64r6		0
60
61#define cpu_has_dsp			0
62#define cpu_has_dsp2			0
63#define cpu_has_mipsmt			0
64#define cpu_has_userlocal		0
65#define cpu_has_inclusive_pcaches	1
66#define cpu_has_perf_cntr_intr_bit	0
67#define cpu_has_vz			0
68#define cpu_has_fre			0
69#define cpu_has_cdmm			0
70
71#define cpu_dcache_line_size()		32
72#define cpu_icache_line_size()		64
73#define cpu_scache_line_size()		128
 
74
75#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */

 1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 2003, 07 Ralf Baechle
 7 */
 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10
11#include <asm/cpu.h>
12
13/*
14 * IP27 only comes with R10000 family processors all using the same config
15 */
16#define cpu_has_watch		1
17#define cpu_has_mips16		0
18#define cpu_has_divec		0
19#define cpu_has_vce		0
20#define cpu_has_cache_cdex_p	0
21#define cpu_has_cache_cdex_s	0
22#define cpu_has_prefetch	1
23#define cpu_has_mcheck		0
24#define cpu_has_ejtag		0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
25
26#define cpu_has_llsc		1
27#define cpu_has_vtag_icache	0
28#define cpu_has_dc_aliases	0
29#define cpu_has_ic_fills_f_dc	0
30#define cpu_has_dsp		0
31#define cpu_has_dsp2		0
32#define cpu_icache_snoops_remote_store	1
33#define cpu_has_mipsmt		0
34#define cpu_has_userlocal	0
35
36#define cpu_has_nofpuex		0
37#define cpu_has_64bits		1
38
39#define cpu_has_4kex		1
40#define cpu_has_3k_cache	0
41#define cpu_has_6k_cache	0
42#define cpu_has_4k_cache	1
43#define cpu_has_8k_cache	0
44#define cpu_has_tx39_cache	0
45
 
 
 
 
 
 
 
 
 
 
 
46#define cpu_has_inclusive_pcaches	1
47
48#define cpu_dcache_line_size()	32
49#define cpu_icache_line_size()	64
50#define cpu_scache_line_size()	128
51
52#define cpu_has_mips32r1	0
53#define cpu_has_mips32r2	0
54#define cpu_has_mips64r1	0
55#define cpu_has_mips64r2	0
56
57#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */