1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. (www.synopsys.com)
  4 *
  5 * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed.
  6 * This file contains the TLB access registers and commands
  7 */
  8
  9#ifndef _ASM_ARC_MMU_ARCV2_H
 10#define _ASM_ARC_MMU_ARCV2_H
 11
 12/*
 13 * TLB Management regs
 14 */
 15#define ARC_REG_MMU_BCR		0x06f
 16
 17#ifdef CONFIG_ARC_MMU_V3
 18#define ARC_REG_TLBPD0		0x405
 19#define ARC_REG_TLBPD1		0x406
 20#define ARC_REG_TLBPD1HI	0	/* Dummy: allows common code */
 21#define ARC_REG_TLBINDEX	0x407
 22#define ARC_REG_TLBCOMMAND	0x408
 23#define ARC_REG_PID		0x409
 24#define ARC_REG_SCRATCH_DATA0	0x418
 25#else
 26#define ARC_REG_TLBPD0		0x460
 27#define ARC_REG_TLBPD1		0x461
 28#define ARC_REG_TLBPD1HI	0x463
 29#define ARC_REG_TLBINDEX	0x464
 30#define ARC_REG_TLBCOMMAND	0x465
 31#define ARC_REG_PID		0x468
 32#define ARC_REG_SCRATCH_DATA0	0x46c
 33#endif
 34
 35/* Bits in MMU PID reg */
 36#define __TLB_ENABLE		(1 << 31)
 37#define __PROG_ENABLE		(1 << 30)
 38#define MMU_ENABLE		(__TLB_ENABLE | __PROG_ENABLE)
 39
 40/* Bits in TLB Index reg */
 41#define TLB_LKUP_ERR		0x80000000
 42
 43#ifdef CONFIG_ARC_MMU_V3
 44#define TLB_DUP_ERR		(TLB_LKUP_ERR | 0x00000001)
 45#else
 46#define TLB_DUP_ERR		(TLB_LKUP_ERR | 0x40000000)
 47#endif
 48
 49/*
 50 * TLB Commands
 51 */
 52#define TLBWrite    		0x1
 53#define TLBRead     		0x2
 54#define TLBGetIndex 		0x3
 55#define TLBProbe    		0x4
 56#define TLBWriteNI		0x5  /* write JTLB without inv uTLBs */
 57#define TLBIVUTLB		0x6  /* explicitly inv uTLBs */
 58
 59#ifdef CONFIG_ARC_MMU_V4
 60#define TLBInsertEntry		0x7
 61#define TLBDeleteEntry		0x8
 62#endif
 63
 64/* Masks for actual TLB "PD"s */
 65#define PTE_BITS_IN_PD0		(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)
 66#define PTE_BITS_RWX		(_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
 67
 68#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK_PHYS | _PAGE_CACHEABLE)
 69
 70#ifndef __ASSEMBLY__
 71
 72struct mm_struct;
 73extern int pae40_exist_but_not_enab(void);
 74
 75static inline int is_pae40_enabled(void)
 76{
 77	return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
 78}
 79
 80static inline void mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
 81{
 82	write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
 83}
 84
 85static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd)
 86{
 87	/* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
 88#ifdef CONFIG_ISA_ARCV2
 89	write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
 90#endif
 91}
 92
 93#else
 94
 95.macro ARC_MMU_REENABLE reg
 96	lr \reg, [ARC_REG_PID]
 97	or \reg, \reg, MMU_ENABLE
 98	sr \reg, [ARC_REG_PID]
 99.endm
100
101#endif /* !__ASSEMBLY__ */
102
103#endif