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1/*
2 * Copyright (c) 2009 Nuvoton technology.
3 * Wan ZongShun <mcuos.com@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <linux/workqueue.h>
14#include <linux/interrupt.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24
25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h>
27
28#include <linux/platform_data/spi-nuc900.h>
29
30/* usi registers offset */
31#define USI_CNT 0x00
32#define USI_DIV 0x04
33#define USI_SSR 0x08
34#define USI_RX0 0x10
35#define USI_TX0 0x10
36
37/* usi register bit */
38#define ENINT (0x01 << 17)
39#define ENFLG (0x01 << 16)
40#define SLEEP (0x0f << 12)
41#define TXNUM (0x03 << 8)
42#define TXBITLEN (0x1f << 3)
43#define TXNEG (0x01 << 2)
44#define RXNEG (0x01 << 1)
45#define LSB (0x01 << 10)
46#define SELECTLEV (0x01 << 2)
47#define SELECTPOL (0x01 << 31)
48#define SELECTSLAVE 0x01
49#define GOBUSY 0x01
50
51struct nuc900_spi {
52 struct spi_bitbang bitbang;
53 struct completion done;
54 void __iomem *regs;
55 int irq;
56 int len;
57 int count;
58 const unsigned char *tx;
59 unsigned char *rx;
60 struct clk *clk;
61 struct spi_master *master;
62 struct nuc900_spi_info *pdata;
63 spinlock_t lock;
64};
65
66static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
67{
68 return spi_master_get_devdata(sdev->master);
69}
70
71static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr)
72{
73 struct nuc900_spi *hw = to_hw(spi);
74 unsigned int val;
75 unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0;
76 unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0;
77 unsigned long flags;
78
79 spin_lock_irqsave(&hw->lock, flags);
80
81 val = __raw_readl(hw->regs + USI_SSR);
82
83 if (!cs)
84 val &= ~SELECTLEV;
85 else
86 val |= SELECTLEV;
87
88 if (!ssr)
89 val &= ~SELECTSLAVE;
90 else
91 val |= SELECTSLAVE;
92
93 __raw_writel(val, hw->regs + USI_SSR);
94
95 val = __raw_readl(hw->regs + USI_CNT);
96
97 if (!cpol)
98 val &= ~SELECTPOL;
99 else
100 val |= SELECTPOL;
101
102 __raw_writel(val, hw->regs + USI_CNT);
103
104 spin_unlock_irqrestore(&hw->lock, flags);
105}
106
107static void nuc900_spi_chipsel(struct spi_device *spi, int value)
108{
109 switch (value) {
110 case BITBANG_CS_INACTIVE:
111 nuc900_slave_select(spi, 0);
112 break;
113
114 case BITBANG_CS_ACTIVE:
115 nuc900_slave_select(spi, 1);
116 break;
117 }
118}
119
120static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum)
121{
122 unsigned int val;
123 unsigned long flags;
124
125 spin_lock_irqsave(&hw->lock, flags);
126
127 val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM;
128
129 if (txnum)
130 val |= txnum << 0x08;
131
132 __raw_writel(val, hw->regs + USI_CNT);
133
134 spin_unlock_irqrestore(&hw->lock, flags);
135
136}
137
138static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
139 unsigned int txbitlen)
140{
141 unsigned int val;
142 unsigned long flags;
143
144 spin_lock_irqsave(&hw->lock, flags);
145
146 val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN;
147
148 val |= (txbitlen << 0x03);
149
150 __raw_writel(val, hw->regs + USI_CNT);
151
152 spin_unlock_irqrestore(&hw->lock, flags);
153}
154
155static void nuc900_spi_gobusy(struct nuc900_spi *hw)
156{
157 unsigned int val;
158 unsigned long flags;
159
160 spin_lock_irqsave(&hw->lock, flags);
161
162 val = __raw_readl(hw->regs + USI_CNT);
163
164 val |= GOBUSY;
165
166 __raw_writel(val, hw->regs + USI_CNT);
167
168 spin_unlock_irqrestore(&hw->lock, flags);
169}
170
171static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
172{
173 return hw->tx ? hw->tx[count] : 0;
174}
175
176static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
177{
178 struct nuc900_spi *hw = to_hw(spi);
179
180 hw->tx = t->tx_buf;
181 hw->rx = t->rx_buf;
182 hw->len = t->len;
183 hw->count = 0;
184
185 __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0);
186
187 nuc900_spi_gobusy(hw);
188
189 wait_for_completion(&hw->done);
190
191 return hw->count;
192}
193
194static irqreturn_t nuc900_spi_irq(int irq, void *dev)
195{
196 struct nuc900_spi *hw = dev;
197 unsigned int status;
198 unsigned int count = hw->count;
199
200 status = __raw_readl(hw->regs + USI_CNT);
201 __raw_writel(status, hw->regs + USI_CNT);
202
203 if (status & ENFLG) {
204 hw->count++;
205
206 if (hw->rx)
207 hw->rx[count] = __raw_readl(hw->regs + USI_RX0);
208 count++;
209
210 if (count < hw->len) {
211 __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0);
212 nuc900_spi_gobusy(hw);
213 } else {
214 complete(&hw->done);
215 }
216
217 return IRQ_HANDLED;
218 }
219
220 complete(&hw->done);
221 return IRQ_HANDLED;
222}
223
224static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge)
225{
226 unsigned int val;
227 unsigned long flags;
228
229 spin_lock_irqsave(&hw->lock, flags);
230
231 val = __raw_readl(hw->regs + USI_CNT);
232
233 if (edge)
234 val |= TXNEG;
235 else
236 val &= ~TXNEG;
237 __raw_writel(val, hw->regs + USI_CNT);
238
239 spin_unlock_irqrestore(&hw->lock, flags);
240}
241
242static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge)
243{
244 unsigned int val;
245 unsigned long flags;
246
247 spin_lock_irqsave(&hw->lock, flags);
248
249 val = __raw_readl(hw->regs + USI_CNT);
250
251 if (edge)
252 val |= RXNEG;
253 else
254 val &= ~RXNEG;
255 __raw_writel(val, hw->regs + USI_CNT);
256
257 spin_unlock_irqrestore(&hw->lock, flags);
258}
259
260static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb)
261{
262 unsigned int val;
263 unsigned long flags;
264
265 spin_lock_irqsave(&hw->lock, flags);
266
267 val = __raw_readl(hw->regs + USI_CNT);
268
269 if (lsb)
270 val |= LSB;
271 else
272 val &= ~LSB;
273 __raw_writel(val, hw->regs + USI_CNT);
274
275 spin_unlock_irqrestore(&hw->lock, flags);
276}
277
278static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
279{
280 unsigned int val;
281 unsigned long flags;
282
283 spin_lock_irqsave(&hw->lock, flags);
284
285 val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP;
286
287 if (sleep)
288 val |= (sleep << 12);
289
290 __raw_writel(val, hw->regs + USI_CNT);
291
292 spin_unlock_irqrestore(&hw->lock, flags);
293}
294
295static void nuc900_enable_int(struct nuc900_spi *hw)
296{
297 unsigned int val;
298 unsigned long flags;
299
300 spin_lock_irqsave(&hw->lock, flags);
301
302 val = __raw_readl(hw->regs + USI_CNT);
303
304 val |= ENINT;
305
306 __raw_writel(val, hw->regs + USI_CNT);
307
308 spin_unlock_irqrestore(&hw->lock, flags);
309}
310
311static void nuc900_set_divider(struct nuc900_spi *hw)
312{
313 __raw_writel(hw->pdata->divider, hw->regs + USI_DIV);
314}
315
316static void nuc900_init_spi(struct nuc900_spi *hw)
317{
318 clk_enable(hw->clk);
319 spin_lock_init(&hw->lock);
320
321 nuc900_tx_edge(hw, hw->pdata->txneg);
322 nuc900_rx_edge(hw, hw->pdata->rxneg);
323 nuc900_send_first(hw, hw->pdata->lsb);
324 nuc900_set_sleep(hw, hw->pdata->sleep);
325 nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen);
326 nuc900_spi_setup_txnum(hw, hw->pdata->txnum);
327 nuc900_set_divider(hw);
328 nuc900_enable_int(hw);
329}
330
331static int nuc900_spi_probe(struct platform_device *pdev)
332{
333 struct nuc900_spi *hw;
334 struct spi_master *master;
335 struct resource *res;
336 int err = 0;
337
338 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
339 if (master == NULL) {
340 dev_err(&pdev->dev, "No memory for spi_master\n");
341 return -ENOMEM;
342 }
343
344 hw = spi_master_get_devdata(master);
345 hw->master = master;
346 hw->pdata = dev_get_platdata(&pdev->dev);
347
348 if (hw->pdata == NULL) {
349 dev_err(&pdev->dev, "No platform data supplied\n");
350 err = -ENOENT;
351 goto err_pdata;
352 }
353
354 platform_set_drvdata(pdev, hw);
355 init_completion(&hw->done);
356
357 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
358 if (hw->pdata->lsb)
359 master->mode_bits |= SPI_LSB_FIRST;
360 master->num_chipselect = hw->pdata->num_cs;
361 master->bus_num = hw->pdata->bus_num;
362 hw->bitbang.master = hw->master;
363 hw->bitbang.chipselect = nuc900_spi_chipsel;
364 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
365
366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367 hw->regs = devm_ioremap_resource(&pdev->dev, res);
368 if (IS_ERR(hw->regs)) {
369 err = PTR_ERR(hw->regs);
370 goto err_pdata;
371 }
372
373 hw->irq = platform_get_irq(pdev, 0);
374 if (hw->irq < 0) {
375 dev_err(&pdev->dev, "No IRQ specified\n");
376 err = -ENOENT;
377 goto err_pdata;
378 }
379
380 err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0,
381 pdev->name, hw);
382 if (err) {
383 dev_err(&pdev->dev, "Cannot claim IRQ\n");
384 goto err_pdata;
385 }
386
387 hw->clk = devm_clk_get(&pdev->dev, "spi");
388 if (IS_ERR(hw->clk)) {
389 dev_err(&pdev->dev, "No clock for device\n");
390 err = PTR_ERR(hw->clk);
391 goto err_pdata;
392 }
393
394 mfp_set_groupg(&pdev->dev, NULL);
395 nuc900_init_spi(hw);
396
397 err = spi_bitbang_start(&hw->bitbang);
398 if (err) {
399 dev_err(&pdev->dev, "Failed to register SPI master\n");
400 goto err_register;
401 }
402
403 return 0;
404
405err_register:
406 clk_disable(hw->clk);
407err_pdata:
408 spi_master_put(hw->master);
409 return err;
410}
411
412static int nuc900_spi_remove(struct platform_device *dev)
413{
414 struct nuc900_spi *hw = platform_get_drvdata(dev);
415
416 spi_bitbang_stop(&hw->bitbang);
417 clk_disable(hw->clk);
418 spi_master_put(hw->master);
419 return 0;
420}
421
422static struct platform_driver nuc900_spi_driver = {
423 .probe = nuc900_spi_probe,
424 .remove = nuc900_spi_remove,
425 .driver = {
426 .name = "nuc900-spi",
427 .owner = THIS_MODULE,
428 },
429};
430module_platform_driver(nuc900_spi_driver);
431
432MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
433MODULE_DESCRIPTION("nuc900 spi driver!");
434MODULE_LICENSE("GPL");
435MODULE_ALIAS("platform:nuc900-spi");