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1/*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/highmem.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/spi/spi.h>
27
28#include "spi-dw.h"
29
30#ifdef CONFIG_DEBUG_FS
31#include <linux/debugfs.h>
32#endif
33
34#define START_STATE ((void *)0)
35#define RUNNING_STATE ((void *)1)
36#define DONE_STATE ((void *)2)
37#define ERROR_STATE ((void *)-1)
38
39#define QUEUE_RUNNING 0
40#define QUEUE_STOPPED 1
41
42#define MRST_SPI_DEASSERT 0
43#define MRST_SPI_ASSERT 1
44
45/* Slave spi_dev related */
46struct chip_data {
47 u16 cr0;
48 u8 cs; /* chip select pin */
49 u8 n_bytes; /* current is a 1/2/4 byte op */
50 u8 tmode; /* TR/TO/RO/EEPROM */
51 u8 type; /* SPI/SSP/MicroWire */
52
53 u8 poll_mode; /* 1 means use poll mode */
54
55 u32 dma_width;
56 u32 rx_threshold;
57 u32 tx_threshold;
58 u8 enable_dma;
59 u8 bits_per_word;
60 u16 clk_div; /* baud rate divider */
61 u32 speed_hz; /* baud rate */
62 void (*cs_control)(u32 command);
63};
64
65#ifdef CONFIG_DEBUG_FS
66#define SPI_REGS_BUFSIZE 1024
67static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69{
70 struct dw_spi *dws;
71 char *buf;
72 u32 len = 0;
73 ssize_t ret;
74
75 dws = file->private_data;
76
77 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
78 if (!buf)
79 return 0;
80
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "MRST SPI0 registers:\n");
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "=================================\n");
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "=================================\n");
117
118 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
119 kfree(buf);
120 return ret;
121}
122
123static const struct file_operations mrst_spi_regs_ops = {
124 .owner = THIS_MODULE,
125 .open = simple_open,
126 .read = spi_show_regs,
127 .llseek = default_llseek,
128};
129
130static int mrst_spi_debugfs_init(struct dw_spi *dws)
131{
132 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
133 if (!dws->debugfs)
134 return -ENOMEM;
135
136 debugfs_create_file("registers", S_IFREG | S_IRUGO,
137 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
138 return 0;
139}
140
141static void mrst_spi_debugfs_remove(struct dw_spi *dws)
142{
143 if (dws->debugfs)
144 debugfs_remove_recursive(dws->debugfs);
145}
146
147#else
148static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
149{
150 return 0;
151}
152
153static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
154{
155}
156#endif /* CONFIG_DEBUG_FS */
157
158/* Return the max entries we can fill into tx fifo */
159static inline u32 tx_max(struct dw_spi *dws)
160{
161 u32 tx_left, tx_room, rxtx_gap;
162
163 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
164 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
165
166 /*
167 * Another concern is about the tx/rx mismatch, we
168 * though to use (dws->fifo_len - rxflr - txflr) as
169 * one maximum value for tx, but it doesn't cover the
170 * data which is out of tx/rx fifo and inside the
171 * shift registers. So a control from sw point of
172 * view is taken.
173 */
174 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
175 / dws->n_bytes;
176
177 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
178}
179
180/* Return the max entries we should read out of rx fifo */
181static inline u32 rx_max(struct dw_spi *dws)
182{
183 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
184
185 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
186}
187
188static void dw_writer(struct dw_spi *dws)
189{
190 u32 max = tx_max(dws);
191 u16 txw = 0;
192
193 while (max--) {
194 /* Set the tx word if the transfer's original "tx" is not null */
195 if (dws->tx_end - dws->len) {
196 if (dws->n_bytes == 1)
197 txw = *(u8 *)(dws->tx);
198 else
199 txw = *(u16 *)(dws->tx);
200 }
201 dw_writew(dws, DW_SPI_DR, txw);
202 dws->tx += dws->n_bytes;
203 }
204}
205
206static void dw_reader(struct dw_spi *dws)
207{
208 u32 max = rx_max(dws);
209 u16 rxw;
210
211 while (max--) {
212 rxw = dw_readw(dws, DW_SPI_DR);
213 /* Care rx only if the transfer's original "rx" is not null */
214 if (dws->rx_end - dws->len) {
215 if (dws->n_bytes == 1)
216 *(u8 *)(dws->rx) = rxw;
217 else
218 *(u16 *)(dws->rx) = rxw;
219 }
220 dws->rx += dws->n_bytes;
221 }
222}
223
224static void *next_transfer(struct dw_spi *dws)
225{
226 struct spi_message *msg = dws->cur_msg;
227 struct spi_transfer *trans = dws->cur_transfer;
228
229 /* Move to next transfer */
230 if (trans->transfer_list.next != &msg->transfers) {
231 dws->cur_transfer =
232 list_entry(trans->transfer_list.next,
233 struct spi_transfer,
234 transfer_list);
235 return RUNNING_STATE;
236 } else
237 return DONE_STATE;
238}
239
240/*
241 * Note: first step is the protocol driver prepares
242 * a dma-capable memory, and this func just need translate
243 * the virt addr to physical
244 */
245static int map_dma_buffers(struct dw_spi *dws)
246{
247 if (!dws->cur_msg->is_dma_mapped
248 || !dws->dma_inited
249 || !dws->cur_chip->enable_dma
250 || !dws->dma_ops)
251 return 0;
252
253 if (dws->cur_transfer->tx_dma)
254 dws->tx_dma = dws->cur_transfer->tx_dma;
255
256 if (dws->cur_transfer->rx_dma)
257 dws->rx_dma = dws->cur_transfer->rx_dma;
258
259 return 1;
260}
261
262/* Caller already set message->status; dma and pio irqs are blocked */
263static void giveback(struct dw_spi *dws)
264{
265 struct spi_transfer *last_transfer;
266 unsigned long flags;
267 struct spi_message *msg;
268
269 spin_lock_irqsave(&dws->lock, flags);
270 msg = dws->cur_msg;
271 dws->cur_msg = NULL;
272 dws->cur_transfer = NULL;
273 dws->prev_chip = dws->cur_chip;
274 dws->cur_chip = NULL;
275 dws->dma_mapped = 0;
276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags);
278
279 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
280 transfer_list);
281
282 if (!last_transfer->cs_change && dws->cs_control)
283 dws->cs_control(MRST_SPI_DEASSERT);
284
285 msg->state = NULL;
286 if (msg->complete)
287 msg->complete(msg->context);
288}
289
290static void int_error_stop(struct dw_spi *dws, const char *msg)
291{
292 /* Stop the hw */
293 spi_enable_chip(dws, 0);
294
295 dev_err(&dws->master->dev, "%s\n", msg);
296 dws->cur_msg->state = ERROR_STATE;
297 tasklet_schedule(&dws->pump_transfers);
298}
299
300void dw_spi_xfer_done(struct dw_spi *dws)
301{
302 /* Update total byte transferred return count actual bytes read */
303 dws->cur_msg->actual_length += dws->len;
304
305 /* Move to next transfer */
306 dws->cur_msg->state = next_transfer(dws);
307
308 /* Handle end of message */
309 if (dws->cur_msg->state == DONE_STATE) {
310 dws->cur_msg->status = 0;
311 giveback(dws);
312 } else
313 tasklet_schedule(&dws->pump_transfers);
314}
315EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
316
317static irqreturn_t interrupt_transfer(struct dw_spi *dws)
318{
319 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
320
321 /* Error handling */
322 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
323 dw_readw(dws, DW_SPI_TXOICR);
324 dw_readw(dws, DW_SPI_RXOICR);
325 dw_readw(dws, DW_SPI_RXUICR);
326 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
327 return IRQ_HANDLED;
328 }
329
330 dw_reader(dws);
331 if (dws->rx_end == dws->rx) {
332 spi_mask_intr(dws, SPI_INT_TXEI);
333 dw_spi_xfer_done(dws);
334 return IRQ_HANDLED;
335 }
336 if (irq_status & SPI_INT_TXEI) {
337 spi_mask_intr(dws, SPI_INT_TXEI);
338 dw_writer(dws);
339 /* Enable TX irq always, it will be disabled when RX finished */
340 spi_umask_intr(dws, SPI_INT_TXEI);
341 }
342
343 return IRQ_HANDLED;
344}
345
346static irqreturn_t dw_spi_irq(int irq, void *dev_id)
347{
348 struct dw_spi *dws = dev_id;
349 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
350
351 if (!irq_status)
352 return IRQ_NONE;
353
354 if (!dws->cur_msg) {
355 spi_mask_intr(dws, SPI_INT_TXEI);
356 return IRQ_HANDLED;
357 }
358
359 return dws->transfer_handler(dws);
360}
361
362/* Must be called inside pump_transfers() */
363static void poll_transfer(struct dw_spi *dws)
364{
365 do {
366 dw_writer(dws);
367 dw_reader(dws);
368 cpu_relax();
369 } while (dws->rx_end > dws->rx);
370
371 dw_spi_xfer_done(dws);
372}
373
374static void pump_transfers(unsigned long data)
375{
376 struct dw_spi *dws = (struct dw_spi *)data;
377 struct spi_message *message = NULL;
378 struct spi_transfer *transfer = NULL;
379 struct spi_transfer *previous = NULL;
380 struct spi_device *spi = NULL;
381 struct chip_data *chip = NULL;
382 u8 bits = 0;
383 u8 imask = 0;
384 u8 cs_change = 0;
385 u16 txint_level = 0;
386 u16 clk_div = 0;
387 u32 speed = 0;
388 u32 cr0 = 0;
389
390 /* Get current state information */
391 message = dws->cur_msg;
392 transfer = dws->cur_transfer;
393 chip = dws->cur_chip;
394 spi = message->spi;
395
396 if (unlikely(!chip->clk_div))
397 chip->clk_div = dws->max_freq / chip->speed_hz;
398
399 if (message->state == ERROR_STATE) {
400 message->status = -EIO;
401 goto early_exit;
402 }
403
404 /* Handle end of message */
405 if (message->state == DONE_STATE) {
406 message->status = 0;
407 goto early_exit;
408 }
409
410 /* Delay if requested at end of transfer*/
411 if (message->state == RUNNING_STATE) {
412 previous = list_entry(transfer->transfer_list.prev,
413 struct spi_transfer,
414 transfer_list);
415 if (previous->delay_usecs)
416 udelay(previous->delay_usecs);
417 }
418
419 dws->n_bytes = chip->n_bytes;
420 dws->dma_width = chip->dma_width;
421 dws->cs_control = chip->cs_control;
422
423 dws->rx_dma = transfer->rx_dma;
424 dws->tx_dma = transfer->tx_dma;
425 dws->tx = (void *)transfer->tx_buf;
426 dws->tx_end = dws->tx + transfer->len;
427 dws->rx = transfer->rx_buf;
428 dws->rx_end = dws->rx + transfer->len;
429 dws->len = dws->cur_transfer->len;
430 if (chip != dws->prev_chip)
431 cs_change = 1;
432
433 cr0 = chip->cr0;
434
435 /* Handle per transfer options for bpw and speed */
436 if (transfer->speed_hz) {
437 speed = chip->speed_hz;
438
439 if (transfer->speed_hz != speed) {
440 speed = transfer->speed_hz;
441
442 /* clk_div doesn't support odd number */
443 clk_div = dws->max_freq / speed;
444 clk_div = (clk_div + 1) & 0xfffe;
445
446 chip->speed_hz = speed;
447 chip->clk_div = clk_div;
448 }
449 }
450 if (transfer->bits_per_word) {
451 bits = transfer->bits_per_word;
452 dws->n_bytes = dws->dma_width = bits >> 3;
453 cr0 = (bits - 1)
454 | (chip->type << SPI_FRF_OFFSET)
455 | (spi->mode << SPI_MODE_OFFSET)
456 | (chip->tmode << SPI_TMOD_OFFSET);
457 }
458 message->state = RUNNING_STATE;
459
460 /*
461 * Adjust transfer mode if necessary. Requires platform dependent
462 * chipselect mechanism.
463 */
464 if (dws->cs_control) {
465 if (dws->rx && dws->tx)
466 chip->tmode = SPI_TMOD_TR;
467 else if (dws->rx)
468 chip->tmode = SPI_TMOD_RO;
469 else
470 chip->tmode = SPI_TMOD_TO;
471
472 cr0 &= ~SPI_TMOD_MASK;
473 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
474 }
475
476 /* Check if current transfer is a DMA transaction */
477 dws->dma_mapped = map_dma_buffers(dws);
478
479 /*
480 * Interrupt mode
481 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
482 */
483 if (!dws->dma_mapped && !chip->poll_mode) {
484 int templen = dws->len / dws->n_bytes;
485 txint_level = dws->fifo_len / 2;
486 txint_level = (templen > txint_level) ? txint_level : templen;
487
488 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
489 dws->transfer_handler = interrupt_transfer;
490 }
491
492 /*
493 * Reprogram registers only if
494 * 1. chip select changes
495 * 2. clk_div is changed
496 * 3. control value changes
497 */
498 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
499 spi_enable_chip(dws, 0);
500
501 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
502 dw_writew(dws, DW_SPI_CTRL0, cr0);
503
504 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
505 spi_chip_sel(dws, spi->chip_select);
506
507 /* Set the interrupt mask, for poll mode just disable all int */
508 spi_mask_intr(dws, 0xff);
509 if (imask)
510 spi_umask_intr(dws, imask);
511 if (txint_level)
512 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
513
514 spi_enable_chip(dws, 1);
515 if (cs_change)
516 dws->prev_chip = chip;
517 }
518
519 if (dws->dma_mapped)
520 dws->dma_ops->dma_transfer(dws, cs_change);
521
522 if (chip->poll_mode)
523 poll_transfer(dws);
524
525 return;
526
527early_exit:
528 giveback(dws);
529 return;
530}
531
532static void pump_messages(struct work_struct *work)
533{
534 struct dw_spi *dws =
535 container_of(work, struct dw_spi, pump_messages);
536 unsigned long flags;
537
538 /* Lock queue and check for queue work */
539 spin_lock_irqsave(&dws->lock, flags);
540 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
541 dws->busy = 0;
542 spin_unlock_irqrestore(&dws->lock, flags);
543 return;
544 }
545
546 /* Make sure we are not already running a message */
547 if (dws->cur_msg) {
548 spin_unlock_irqrestore(&dws->lock, flags);
549 return;
550 }
551
552 /* Extract head of queue */
553 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
554 list_del_init(&dws->cur_msg->queue);
555
556 /* Initial message state*/
557 dws->cur_msg->state = START_STATE;
558 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
559 struct spi_transfer,
560 transfer_list);
561 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
562
563 /* Mark as busy and launch transfers */
564 tasklet_schedule(&dws->pump_transfers);
565
566 dws->busy = 1;
567 spin_unlock_irqrestore(&dws->lock, flags);
568}
569
570/* spi_device use this to queue in their spi_msg */
571static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
572{
573 struct dw_spi *dws = spi_master_get_devdata(spi->master);
574 unsigned long flags;
575
576 spin_lock_irqsave(&dws->lock, flags);
577
578 if (dws->run == QUEUE_STOPPED) {
579 spin_unlock_irqrestore(&dws->lock, flags);
580 return -ESHUTDOWN;
581 }
582
583 msg->actual_length = 0;
584 msg->status = -EINPROGRESS;
585 msg->state = START_STATE;
586
587 list_add_tail(&msg->queue, &dws->queue);
588
589 if (dws->run == QUEUE_RUNNING && !dws->busy) {
590
591 if (dws->cur_transfer || dws->cur_msg)
592 queue_work(dws->workqueue,
593 &dws->pump_messages);
594 else {
595 /* If no other data transaction in air, just go */
596 spin_unlock_irqrestore(&dws->lock, flags);
597 pump_messages(&dws->pump_messages);
598 return 0;
599 }
600 }
601
602 spin_unlock_irqrestore(&dws->lock, flags);
603 return 0;
604}
605
606/* This may be called twice for each spi dev */
607static int dw_spi_setup(struct spi_device *spi)
608{
609 struct dw_spi_chip *chip_info = NULL;
610 struct chip_data *chip;
611
612 /* Only alloc on first setup */
613 chip = spi_get_ctldata(spi);
614 if (!chip) {
615 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
616 GFP_KERNEL);
617 if (!chip)
618 return -ENOMEM;
619 spi_set_ctldata(spi, chip);
620 }
621
622 /*
623 * Protocol drivers may change the chip settings, so...
624 * if chip_info exists, use it
625 */
626 chip_info = spi->controller_data;
627
628 /* chip_info doesn't always exist */
629 if (chip_info) {
630 if (chip_info->cs_control)
631 chip->cs_control = chip_info->cs_control;
632
633 chip->poll_mode = chip_info->poll_mode;
634 chip->type = chip_info->type;
635
636 chip->rx_threshold = 0;
637 chip->tx_threshold = 0;
638
639 chip->enable_dma = chip_info->enable_dma;
640 }
641
642 if (spi->bits_per_word == 8) {
643 chip->n_bytes = 1;
644 chip->dma_width = 1;
645 } else if (spi->bits_per_word == 16) {
646 chip->n_bytes = 2;
647 chip->dma_width = 2;
648 }
649 chip->bits_per_word = spi->bits_per_word;
650
651 if (!spi->max_speed_hz) {
652 dev_err(&spi->dev, "No max speed HZ parameter\n");
653 return -EINVAL;
654 }
655 chip->speed_hz = spi->max_speed_hz;
656
657 chip->tmode = 0; /* Tx & Rx */
658 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
659 chip->cr0 = (chip->bits_per_word - 1)
660 | (chip->type << SPI_FRF_OFFSET)
661 | (spi->mode << SPI_MODE_OFFSET)
662 | (chip->tmode << SPI_TMOD_OFFSET);
663
664 return 0;
665}
666
667static int init_queue(struct dw_spi *dws)
668{
669 INIT_LIST_HEAD(&dws->queue);
670 spin_lock_init(&dws->lock);
671
672 dws->run = QUEUE_STOPPED;
673 dws->busy = 0;
674
675 tasklet_init(&dws->pump_transfers,
676 pump_transfers, (unsigned long)dws);
677
678 INIT_WORK(&dws->pump_messages, pump_messages);
679 dws->workqueue = create_singlethread_workqueue(
680 dev_name(dws->master->dev.parent));
681 if (dws->workqueue == NULL)
682 return -EBUSY;
683
684 return 0;
685}
686
687static int start_queue(struct dw_spi *dws)
688{
689 unsigned long flags;
690
691 spin_lock_irqsave(&dws->lock, flags);
692
693 if (dws->run == QUEUE_RUNNING || dws->busy) {
694 spin_unlock_irqrestore(&dws->lock, flags);
695 return -EBUSY;
696 }
697
698 dws->run = QUEUE_RUNNING;
699 dws->cur_msg = NULL;
700 dws->cur_transfer = NULL;
701 dws->cur_chip = NULL;
702 dws->prev_chip = NULL;
703 spin_unlock_irqrestore(&dws->lock, flags);
704
705 queue_work(dws->workqueue, &dws->pump_messages);
706
707 return 0;
708}
709
710static int stop_queue(struct dw_spi *dws)
711{
712 unsigned long flags;
713 unsigned limit = 50;
714 int status = 0;
715
716 spin_lock_irqsave(&dws->lock, flags);
717 dws->run = QUEUE_STOPPED;
718 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
719 spin_unlock_irqrestore(&dws->lock, flags);
720 msleep(10);
721 spin_lock_irqsave(&dws->lock, flags);
722 }
723
724 if (!list_empty(&dws->queue) || dws->busy)
725 status = -EBUSY;
726 spin_unlock_irqrestore(&dws->lock, flags);
727
728 return status;
729}
730
731static int destroy_queue(struct dw_spi *dws)
732{
733 int status;
734
735 status = stop_queue(dws);
736 if (status != 0)
737 return status;
738 destroy_workqueue(dws->workqueue);
739 return 0;
740}
741
742/* Restart the controller, disable all interrupts, clean rx fifo */
743static void spi_hw_init(struct dw_spi *dws)
744{
745 spi_enable_chip(dws, 0);
746 spi_mask_intr(dws, 0xff);
747 spi_enable_chip(dws, 1);
748
749 /*
750 * Try to detect the FIFO depth if not set by interface driver,
751 * the depth could be from 2 to 256 from HW spec
752 */
753 if (!dws->fifo_len) {
754 u32 fifo;
755 for (fifo = 2; fifo <= 257; fifo++) {
756 dw_writew(dws, DW_SPI_TXFLTR, fifo);
757 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
758 break;
759 }
760
761 dws->fifo_len = (fifo == 257) ? 0 : fifo;
762 dw_writew(dws, DW_SPI_TXFLTR, 0);
763 }
764}
765
766int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
767{
768 struct spi_master *master;
769 int ret;
770
771 BUG_ON(dws == NULL);
772
773 master = spi_alloc_master(dev, 0);
774 if (!master)
775 return -ENOMEM;
776
777 dws->master = master;
778 dws->type = SSI_MOTO_SPI;
779 dws->prev_chip = NULL;
780 dws->dma_inited = 0;
781 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
782 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
783 dws->bus_num);
784
785 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
786 dws->name, dws);
787 if (ret < 0) {
788 dev_err(&master->dev, "can not get IRQ\n");
789 goto err_free_master;
790 }
791
792 master->mode_bits = SPI_CPOL | SPI_CPHA;
793 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
794 master->bus_num = dws->bus_num;
795 master->num_chipselect = dws->num_cs;
796 master->setup = dw_spi_setup;
797 master->transfer = dw_spi_transfer;
798 master->max_speed_hz = dws->max_freq;
799
800 /* Basic HW init */
801 spi_hw_init(dws);
802
803 if (dws->dma_ops && dws->dma_ops->dma_init) {
804 ret = dws->dma_ops->dma_init(dws);
805 if (ret) {
806 dev_warn(&master->dev, "DMA init failed\n");
807 dws->dma_inited = 0;
808 }
809 }
810
811 /* Initial and start queue */
812 ret = init_queue(dws);
813 if (ret) {
814 dev_err(&master->dev, "problem initializing queue\n");
815 goto err_diable_hw;
816 }
817 ret = start_queue(dws);
818 if (ret) {
819 dev_err(&master->dev, "problem starting queue\n");
820 goto err_diable_hw;
821 }
822
823 spi_master_set_devdata(master, dws);
824 ret = devm_spi_register_master(dev, master);
825 if (ret) {
826 dev_err(&master->dev, "problem registering spi master\n");
827 goto err_queue_alloc;
828 }
829
830 mrst_spi_debugfs_init(dws);
831 return 0;
832
833err_queue_alloc:
834 destroy_queue(dws);
835 if (dws->dma_ops && dws->dma_ops->dma_exit)
836 dws->dma_ops->dma_exit(dws);
837err_diable_hw:
838 spi_enable_chip(dws, 0);
839err_free_master:
840 spi_master_put(master);
841 return ret;
842}
843EXPORT_SYMBOL_GPL(dw_spi_add_host);
844
845void dw_spi_remove_host(struct dw_spi *dws)
846{
847 int status = 0;
848
849 if (!dws)
850 return;
851 mrst_spi_debugfs_remove(dws);
852
853 /* Remove the queue */
854 status = destroy_queue(dws);
855 if (status != 0)
856 dev_err(&dws->master->dev,
857 "dw_spi_remove: workqueue will not complete, message memory not freed\n");
858
859 if (dws->dma_ops && dws->dma_ops->dma_exit)
860 dws->dma_ops->dma_exit(dws);
861 spi_enable_chip(dws, 0);
862 /* Disable clk */
863 spi_set_clk(dws, 0);
864}
865EXPORT_SYMBOL_GPL(dw_spi_remove_host);
866
867int dw_spi_suspend_host(struct dw_spi *dws)
868{
869 int ret = 0;
870
871 ret = stop_queue(dws);
872 if (ret)
873 return ret;
874 spi_enable_chip(dws, 0);
875 spi_set_clk(dws, 0);
876 return ret;
877}
878EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
879
880int dw_spi_resume_host(struct dw_spi *dws)
881{
882 int ret;
883
884 spi_hw_init(dws);
885 ret = start_queue(dws);
886 if (ret)
887 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
888 return ret;
889}
890EXPORT_SYMBOL_GPL(dw_spi_resume_host);
891
892MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
893MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
894MODULE_LICENSE("GPL v2");