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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
4 *
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This driver has been based on the spi-gpio.c:
8 * Copyright (C) 2006,2008 David Brownell
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/spi-mem.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/bitops.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23
24#define DRV_NAME "ath79-spi"
25
26#define ATH79_SPI_RRW_DELAY_FACTOR 12000
27#define MHZ (1000 * 1000)
28
29#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
30#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
31#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
32#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
33
34#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
35
36#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
37#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
38#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
39
40struct ath79_spi {
41 struct spi_bitbang bitbang;
42 u32 ioc_base;
43 u32 reg_ctrl;
44 void __iomem *base;
45 struct clk *clk;
46 unsigned int rrw_delay;
47};
48
49static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
50{
51 return ioread32(sp->base + reg);
52}
53
54static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
55{
56 iowrite32(val, sp->base + reg);
57}
58
59static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
60{
61 return spi_controller_get_devdata(spi->controller);
62}
63
64static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
65{
66 if (nsecs > sp->rrw_delay)
67 ndelay(nsecs - sp->rrw_delay);
68}
69
70static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
71{
72 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
73 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74 u32 cs_bit = AR71XX_SPI_IOC_CS(spi_get_chipselect(spi, 0));
75
76 if (cs_high)
77 sp->ioc_base |= cs_bit;
78 else
79 sp->ioc_base &= ~cs_bit;
80
81 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
82}
83
84static void ath79_spi_enable(struct ath79_spi *sp)
85{
86 /* enable GPIO mode */
87 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
88
89 /* save CTRL register */
90 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
91 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
92
93 /* clear clk and mosi in the base state */
94 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
95
96 /* TODO: setup speed? */
97 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
98}
99
100static void ath79_spi_disable(struct ath79_spi *sp)
101{
102 /* restore CTRL register */
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
104 /* disable GPIO mode */
105 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
106}
107
108static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
109 u32 word, u8 bits, unsigned flags)
110{
111 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
112 u32 ioc = sp->ioc_base;
113
114 /* clock starts at inactive polarity */
115 for (word <<= (32 - bits); likely(bits); bits--) {
116 u32 out;
117
118 if (word & (1 << 31))
119 out = ioc | AR71XX_SPI_IOC_DO;
120 else
121 out = ioc & ~AR71XX_SPI_IOC_DO;
122
123 /* setup MSB (to target) on trailing edge */
124 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
125 ath79_spi_delay(sp, nsecs);
126 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
127 ath79_spi_delay(sp, nsecs);
128 if (bits == 1)
129 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
130
131 word <<= 1;
132 }
133
134 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
135}
136
137static int ath79_exec_mem_op(struct spi_mem *mem,
138 const struct spi_mem_op *op)
139{
140 struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
141
142 /* Ensures that reading is performed on device connected to hardware cs0 */
143 if (spi_get_chipselect(mem->spi, 0) || spi_get_csgpiod(mem->spi, 0))
144 return -ENOTSUPP;
145
146 /* Only use for fast-read op. */
147 if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
148 op->addr.nbytes != 3 || op->dummy.nbytes != 1)
149 return -EOPNOTSUPP;
150
151 /* disable GPIO mode */
152 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
153
154 memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
155
156 /* enable GPIO mode */
157 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
158
159 /* restore IOC register */
160 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
161
162 return 0;
163}
164
165static const struct spi_controller_mem_ops ath79_mem_ops = {
166 .exec_op = ath79_exec_mem_op,
167};
168
169static int ath79_spi_probe(struct platform_device *pdev)
170{
171 struct spi_controller *host;
172 struct ath79_spi *sp;
173 unsigned long rate;
174 int ret;
175
176 host = spi_alloc_host(&pdev->dev, sizeof(*sp));
177 if (host == NULL) {
178 dev_err(&pdev->dev, "failed to allocate spi host\n");
179 return -ENOMEM;
180 }
181
182 sp = spi_controller_get_devdata(host);
183 host->dev.of_node = pdev->dev.of_node;
184 platform_set_drvdata(pdev, sp);
185
186 host->use_gpio_descriptors = true;
187 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
188 host->flags = SPI_CONTROLLER_GPIO_SS;
189 host->num_chipselect = 3;
190 host->mem_ops = &ath79_mem_ops;
191
192 sp->bitbang.master = host;
193 sp->bitbang.chipselect = ath79_spi_chipselect;
194 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
195 sp->bitbang.flags = SPI_CS_HIGH;
196
197 sp->base = devm_platform_ioremap_resource(pdev, 0);
198 if (IS_ERR(sp->base)) {
199 ret = PTR_ERR(sp->base);
200 goto err_put_host;
201 }
202
203 sp->clk = devm_clk_get_enabled(&pdev->dev, "ahb");
204 if (IS_ERR(sp->clk)) {
205 ret = PTR_ERR(sp->clk);
206 goto err_put_host;
207 }
208
209 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
210 if (!rate) {
211 ret = -EINVAL;
212 goto err_put_host;
213 }
214
215 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
216 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
217 sp->rrw_delay);
218
219 ath79_spi_enable(sp);
220 ret = spi_bitbang_start(&sp->bitbang);
221 if (ret)
222 goto err_disable;
223
224 return 0;
225
226err_disable:
227 ath79_spi_disable(sp);
228err_put_host:
229 spi_controller_put(host);
230
231 return ret;
232}
233
234static void ath79_spi_remove(struct platform_device *pdev)
235{
236 struct ath79_spi *sp = platform_get_drvdata(pdev);
237
238 spi_bitbang_stop(&sp->bitbang);
239 ath79_spi_disable(sp);
240 spi_controller_put(sp->bitbang.master);
241}
242
243static void ath79_spi_shutdown(struct platform_device *pdev)
244{
245 ath79_spi_remove(pdev);
246}
247
248static const struct of_device_id ath79_spi_of_match[] = {
249 { .compatible = "qca,ar7100-spi", },
250 { },
251};
252MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
253
254static struct platform_driver ath79_spi_driver = {
255 .probe = ath79_spi_probe,
256 .remove_new = ath79_spi_remove,
257 .shutdown = ath79_spi_shutdown,
258 .driver = {
259 .name = DRV_NAME,
260 .of_match_table = ath79_spi_of_match,
261 },
262};
263module_platform_driver(ath79_spi_driver);
264
265MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
266MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
267MODULE_LICENSE("GPL v2");
268MODULE_ALIAS("platform:" DRV_NAME);
1/*
2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/workqueue.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24#include <linux/bitops.h>
25#include <linux/gpio.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28
29#include <asm/mach-ath79/ar71xx_regs.h>
30#include <asm/mach-ath79/ath79_spi_platform.h>
31
32#define DRV_NAME "ath79-spi"
33
34#define ATH79_SPI_RRW_DELAY_FACTOR 12000
35#define MHZ (1000 * 1000)
36
37struct ath79_spi {
38 struct spi_bitbang bitbang;
39 u32 ioc_base;
40 u32 reg_ctrl;
41 void __iomem *base;
42 struct clk *clk;
43 unsigned rrw_delay;
44};
45
46static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
47{
48 return ioread32(sp->base + reg);
49}
50
51static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
52{
53 iowrite32(val, sp->base + reg);
54}
55
56static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
57{
58 return spi_master_get_devdata(spi->master);
59}
60
61static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
62{
63 if (nsecs > sp->rrw_delay)
64 ndelay(nsecs - sp->rrw_delay);
65}
66
67static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
68{
69 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
70 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
71
72 if (is_active) {
73 /* set initial clock polarity */
74 if (spi->mode & SPI_CPOL)
75 sp->ioc_base |= AR71XX_SPI_IOC_CLK;
76 else
77 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
78
79 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
80 }
81
82 if (spi->chip_select) {
83 struct ath79_spi_controller_data *cdata = spi->controller_data;
84
85 /* SPI is normally active-low */
86 gpio_set_value(cdata->gpio, cs_high);
87 } else {
88 if (cs_high)
89 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
90 else
91 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
92
93 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
94 }
95
96}
97
98static void ath79_spi_enable(struct ath79_spi *sp)
99{
100 /* enable GPIO mode */
101 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
102
103 /* save CTRL register */
104 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
105 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
106
107 /* TODO: setup speed? */
108 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
109}
110
111static void ath79_spi_disable(struct ath79_spi *sp)
112{
113 /* restore CTRL register */
114 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
115 /* disable GPIO mode */
116 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
117}
118
119static int ath79_spi_setup_cs(struct spi_device *spi)
120{
121 struct ath79_spi_controller_data *cdata;
122 int status;
123
124 cdata = spi->controller_data;
125 if (spi->chip_select && !cdata)
126 return -EINVAL;
127
128 status = 0;
129 if (spi->chip_select) {
130 unsigned long flags;
131
132 flags = GPIOF_DIR_OUT;
133 if (spi->mode & SPI_CS_HIGH)
134 flags |= GPIOF_INIT_LOW;
135 else
136 flags |= GPIOF_INIT_HIGH;
137
138 status = gpio_request_one(cdata->gpio, flags,
139 dev_name(&spi->dev));
140 }
141
142 return status;
143}
144
145static void ath79_spi_cleanup_cs(struct spi_device *spi)
146{
147 if (spi->chip_select) {
148 struct ath79_spi_controller_data *cdata = spi->controller_data;
149 gpio_free(cdata->gpio);
150 }
151}
152
153static int ath79_spi_setup(struct spi_device *spi)
154{
155 int status = 0;
156
157 if (!spi->controller_state) {
158 status = ath79_spi_setup_cs(spi);
159 if (status)
160 return status;
161 }
162
163 status = spi_bitbang_setup(spi);
164 if (status && !spi->controller_state)
165 ath79_spi_cleanup_cs(spi);
166
167 return status;
168}
169
170static void ath79_spi_cleanup(struct spi_device *spi)
171{
172 ath79_spi_cleanup_cs(spi);
173 spi_bitbang_cleanup(spi);
174}
175
176static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
177 u32 word, u8 bits)
178{
179 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
180 u32 ioc = sp->ioc_base;
181
182 /* clock starts at inactive polarity */
183 for (word <<= (32 - bits); likely(bits); bits--) {
184 u32 out;
185
186 if (word & (1 << 31))
187 out = ioc | AR71XX_SPI_IOC_DO;
188 else
189 out = ioc & ~AR71XX_SPI_IOC_DO;
190
191 /* setup MSB (to slave) on trailing edge */
192 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
193 ath79_spi_delay(sp, nsecs);
194 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
195 ath79_spi_delay(sp, nsecs);
196 if (bits == 1)
197 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
198
199 word <<= 1;
200 }
201
202 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
203}
204
205static int ath79_spi_probe(struct platform_device *pdev)
206{
207 struct spi_master *master;
208 struct ath79_spi *sp;
209 struct ath79_spi_platform_data *pdata;
210 struct resource *r;
211 unsigned long rate;
212 int ret;
213
214 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
215 if (master == NULL) {
216 dev_err(&pdev->dev, "failed to allocate spi master\n");
217 return -ENOMEM;
218 }
219
220 sp = spi_master_get_devdata(master);
221 platform_set_drvdata(pdev, sp);
222
223 pdata = dev_get_platdata(&pdev->dev);
224
225 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
226 master->setup = ath79_spi_setup;
227 master->cleanup = ath79_spi_cleanup;
228 if (pdata) {
229 master->bus_num = pdata->bus_num;
230 master->num_chipselect = pdata->num_chipselect;
231 }
232
233 sp->bitbang.master = master;
234 sp->bitbang.chipselect = ath79_spi_chipselect;
235 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
236 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
237 sp->bitbang.flags = SPI_CS_HIGH;
238
239 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (r == NULL) {
241 ret = -ENOENT;
242 goto err_put_master;
243 }
244
245 sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
246 if (!sp->base) {
247 ret = -ENXIO;
248 goto err_put_master;
249 }
250
251 sp->clk = devm_clk_get(&pdev->dev, "ahb");
252 if (IS_ERR(sp->clk)) {
253 ret = PTR_ERR(sp->clk);
254 goto err_put_master;
255 }
256
257 ret = clk_enable(sp->clk);
258 if (ret)
259 goto err_put_master;
260
261 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
262 if (!rate) {
263 ret = -EINVAL;
264 goto err_clk_disable;
265 }
266
267 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
268 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
269 sp->rrw_delay);
270
271 ath79_spi_enable(sp);
272 ret = spi_bitbang_start(&sp->bitbang);
273 if (ret)
274 goto err_disable;
275
276 return 0;
277
278err_disable:
279 ath79_spi_disable(sp);
280err_clk_disable:
281 clk_disable(sp->clk);
282err_put_master:
283 spi_master_put(sp->bitbang.master);
284
285 return ret;
286}
287
288static int ath79_spi_remove(struct platform_device *pdev)
289{
290 struct ath79_spi *sp = platform_get_drvdata(pdev);
291
292 spi_bitbang_stop(&sp->bitbang);
293 ath79_spi_disable(sp);
294 clk_disable(sp->clk);
295 spi_master_put(sp->bitbang.master);
296
297 return 0;
298}
299
300static void ath79_spi_shutdown(struct platform_device *pdev)
301{
302 ath79_spi_remove(pdev);
303}
304
305static struct platform_driver ath79_spi_driver = {
306 .probe = ath79_spi_probe,
307 .remove = ath79_spi_remove,
308 .shutdown = ath79_spi_shutdown,
309 .driver = {
310 .name = DRV_NAME,
311 .owner = THIS_MODULE,
312 },
313};
314module_platform_driver(ath79_spi_driver);
315
316MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
317MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
318MODULE_LICENSE("GPL v2");
319MODULE_ALIAS("platform:" DRV_NAME);