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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include <linux/sched.h>
36#include <linux/firmware.h>
37#include <linux/etherdevice.h>
38#include <linux/vmalloc.h>
39#include <linux/usb.h>
40#include <net/mac80211.h>
41#include <linux/completion.h>
42#include "debug.h"
43
44#define MASKBYTE0 0xff
45#define MASKBYTE1 0xff00
46#define MASKBYTE2 0xff0000
47#define MASKBYTE3 0xff000000
48#define MASKHWORD 0xffff0000
49#define MASKLWORD 0x0000ffff
50#define MASKDWORD 0xffffffff
51#define MASK12BITS 0xfff
52#define MASKH4BITS 0xf0000000
53#define MASKOFDM_D 0xffc00000
54#define MASKCCK 0x3f3f3f3f
55
56#define MASK4BITS 0x0f
57#define MASK20BITS 0xfffff
58#define RFREG_OFFSET_MASK 0xfffff
59
60#define MASKBYTE0 0xff
61#define MASKBYTE1 0xff00
62#define MASKBYTE2 0xff0000
63#define MASKBYTE3 0xff000000
64#define MASKHWORD 0xffff0000
65#define MASKLWORD 0x0000ffff
66#define MASKDWORD 0xffffffff
67#define MASK12BITS 0xfff
68#define MASKH4BITS 0xf0000000
69#define MASKOFDM_D 0xffc00000
70#define MASKCCK 0x3f3f3f3f
71
72#define MASK4BITS 0x0f
73#define MASK20BITS 0xfffff
74#define RFREG_OFFSET_MASK 0xfffff
75
76#define RF_CHANGE_BY_INIT 0
77#define RF_CHANGE_BY_IPS BIT(28)
78#define RF_CHANGE_BY_PS BIT(29)
79#define RF_CHANGE_BY_HW BIT(30)
80#define RF_CHANGE_BY_SW BIT(31)
81
82#define IQK_ADDA_REG_NUM 16
83#define IQK_MAC_REG_NUM 4
84#define IQK_THRESHOLD 8
85
86#define MAX_KEY_LEN 61
87#define KEY_BUF_SIZE 5
88
89/* QoS related. */
90/*aci: 0x00 Best Effort*/
91/*aci: 0x01 Background*/
92/*aci: 0x10 Video*/
93/*aci: 0x11 Voice*/
94/*Max: define total number.*/
95#define AC0_BE 0
96#define AC1_BK 1
97#define AC2_VI 2
98#define AC3_VO 3
99#define AC_MAX 4
100#define QOS_QUEUE_NUM 4
101#define RTL_MAC80211_NUM_QUEUE 5
102#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
103#define RTL_USB_MAX_RX_COUNT 100
104#define QBSS_LOAD_SIZE 5
105#define MAX_WMMELE_LENGTH 64
106
107#define TOTAL_CAM_ENTRY 32
108
109/*slot time for 11g. */
110#define RTL_SLOT_TIME_9 9
111#define RTL_SLOT_TIME_20 20
112
113/*related to tcp/ip. */
114#define SNAP_SIZE 6
115#define PROTOC_TYPE_SIZE 2
116
117/*related with 802.11 frame*/
118#define MAC80211_3ADDR_LEN 24
119#define MAC80211_4ADDR_LEN 30
120
121#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
122#define CHANNEL_MAX_NUMBER_2G 14
123#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
124 *"phy_GetChnlGroup8812A" and
125 * "Hal_ReadTxPowerInfo8812A"
126 */
127#define CHANNEL_MAX_NUMBER_5G_80M 7
128#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
129#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
130 *"phy_GetChnlGroup8812A" and
131 * "Hal_ReadTxPowerInfo8812A"
132 */
133#define CHANNEL_MAX_NUMBER_5G_80M 7
134#define MAX_PG_GROUP 13
135#define CHANNEL_GROUP_MAX_2G 3
136#define CHANNEL_GROUP_IDX_5GL 3
137#define CHANNEL_GROUP_IDX_5GM 6
138#define CHANNEL_GROUP_IDX_5GH 9
139#define CHANNEL_GROUP_MAX_5G 9
140#define CHANNEL_MAX_NUMBER_2G 14
141#define AVG_THERMAL_NUM 8
142#define AVG_THERMAL_NUM_88E 4
143#define AVG_THERMAL_NUM_8723BE 4
144#define MAX_TID_COUNT 9
145
146/* for early mode */
147#define FCS_LEN 4
148#define EM_HDR_LEN 8
149
150#define MAX_TX_COUNT 4
151#define MAX_RF_PATH 4
152#define MAX_CHNL_GROUP_24G 6
153#define MAX_CHNL_GROUP_5G 14
154
155#define TX_PWR_BY_RATE_NUM_BAND 2
156#define TX_PWR_BY_RATE_NUM_RF 4
157#define TX_PWR_BY_RATE_NUM_SECTION 12
158#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
159#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
160
161#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
162
163#define DEL_SW_IDX_SZ 30
164#define BAND_NUM 3
165
166enum rf_tx_num {
167 RF_1TX = 0,
168 RF_2TX,
169 RF_MAX_TX_NUM,
170 RF_TX_NUM_NONIMPLEMENT,
171};
172
173struct txpower_info_2g {
174 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
175 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
176 /*If only one tx, only BW20 and OFDM are used.*/
177 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
178 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
179 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
180 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
181 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
182 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
183};
184
185struct txpower_info_5g {
186 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
187 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
188 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
189 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
190 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
191 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
192 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
193};
194
195enum rate_section {
196 CCK = 0,
197 OFDM,
198 HT_MCS0_MCS7,
199 HT_MCS8_MCS15,
200 VHT_1SSMCS0_1SSMCS9,
201 VHT_2SSMCS0_2SSMCS9,
202};
203
204enum intf_type {
205 INTF_PCI = 0,
206 INTF_USB = 1,
207};
208
209enum radio_path {
210 RF90_PATH_A = 0,
211 RF90_PATH_B = 1,
212 RF90_PATH_C = 2,
213 RF90_PATH_D = 3,
214};
215
216enum rt_eeprom_type {
217 EEPROM_93C46,
218 EEPROM_93C56,
219 EEPROM_BOOT_EFUSE,
220};
221
222enum ttl_status {
223 RTL_STATUS_INTERFACE_START = 0,
224};
225
226enum hardware_type {
227 HARDWARE_TYPE_RTL8192E,
228 HARDWARE_TYPE_RTL8192U,
229 HARDWARE_TYPE_RTL8192SE,
230 HARDWARE_TYPE_RTL8192SU,
231 HARDWARE_TYPE_RTL8192CE,
232 HARDWARE_TYPE_RTL8192CU,
233 HARDWARE_TYPE_RTL8192DE,
234 HARDWARE_TYPE_RTL8192DU,
235 HARDWARE_TYPE_RTL8723AE,
236 HARDWARE_TYPE_RTL8723U,
237 HARDWARE_TYPE_RTL8723BE,
238 HARDWARE_TYPE_RTL8188EE,
239 HARDWARE_TYPE_RTL8821AE,
240 HARDWARE_TYPE_RTL8812AE,
241
242 /* keep it last */
243 HARDWARE_TYPE_NUM
244};
245
246#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
247 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
248#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
249 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
250#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
251 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
252#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
253 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
254#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
255 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
256#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
257 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
258#define IS_HARDWARE_TYPE_8723E(rtlhal) \
259 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
260#define IS_HARDWARE_TYPE_8723U(rtlhal) \
261 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
262#define IS_HARDWARE_TYPE_8192S(rtlhal) \
263(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
264#define IS_HARDWARE_TYPE_8192C(rtlhal) \
265(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
266#define IS_HARDWARE_TYPE_8192D(rtlhal) \
267(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
268#define IS_HARDWARE_TYPE_8723(rtlhal) \
269(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
270
271#define RX_HAL_IS_CCK_RATE(_pdesc)\
272 (_pdesc->rxmcs == DESC92_RATE1M || \
273 _pdesc->rxmcs == DESC92_RATE2M || \
274 _pdesc->rxmcs == DESC92_RATE5_5M || \
275 _pdesc->rxmcs == DESC92_RATE11M)
276
277#define RTL8723E_RX_HAL_IS_CCK_RATE(rxmcs) \
278 ((rxmcs) == DESC92_RATE1M || \
279 (rxmcs) == DESC92_RATE2M || \
280 (rxmcs) == DESC92_RATE5_5M || \
281 (rxmcs) == DESC92_RATE11M)
282
283enum scan_operation_backup_opt {
284 SCAN_OPT_BACKUP = 0,
285 SCAN_OPT_BACKUP_BAND0 = 0,
286 SCAN_OPT_BACKUP_BAND1,
287 SCAN_OPT_RESTORE,
288 SCAN_OPT_MAX
289};
290
291/*RF state.*/
292enum rf_pwrstate {
293 ERFON,
294 ERFSLEEP,
295 ERFOFF
296};
297
298struct bb_reg_def {
299 u32 rfintfs;
300 u32 rfintfi;
301 u32 rfintfo;
302 u32 rfintfe;
303 u32 rf3wire_offset;
304 u32 rflssi_select;
305 u32 rftxgain_stage;
306 u32 rfhssi_para1;
307 u32 rfhssi_para2;
308 u32 rfsw_ctrl;
309 u32 rfagc_control1;
310 u32 rfagc_control2;
311 u32 rfrxiq_imbal;
312 u32 rfrx_afe;
313 u32 rftxiq_imbal;
314 u32 rftx_afe;
315 u32 rf_rb; /* rflssi_readback */
316 u32 rf_rbpi; /* rflssi_readbackpi */
317};
318
319enum io_type {
320 IO_CMD_PAUSE_DM_BY_SCAN = 0,
321 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
322 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
323 IO_CMD_RESUME_DM_BY_SCAN = 2,
324};
325
326enum hw_variables {
327 HW_VAR_ETHER_ADDR,
328 HW_VAR_MULTICAST_REG,
329 HW_VAR_BASIC_RATE,
330 HW_VAR_BSSID,
331 HW_VAR_MEDIA_STATUS,
332 HW_VAR_SECURITY_CONF,
333 HW_VAR_BEACON_INTERVAL,
334 HW_VAR_ATIM_WINDOW,
335 HW_VAR_LISTEN_INTERVAL,
336 HW_VAR_CS_COUNTER,
337 HW_VAR_DEFAULTKEY0,
338 HW_VAR_DEFAULTKEY1,
339 HW_VAR_DEFAULTKEY2,
340 HW_VAR_DEFAULTKEY3,
341 HW_VAR_SIFS,
342 HW_VAR_DIFS,
343 HW_VAR_EIFS,
344 HW_VAR_SLOT_TIME,
345 HW_VAR_ACK_PREAMBLE,
346 HW_VAR_CW_CONFIG,
347 HW_VAR_CW_VALUES,
348 HW_VAR_RATE_FALLBACK_CONTROL,
349 HW_VAR_CONTENTION_WINDOW,
350 HW_VAR_RETRY_COUNT,
351 HW_VAR_TR_SWITCH,
352 HW_VAR_COMMAND,
353 HW_VAR_WPA_CONFIG,
354 HW_VAR_AMPDU_MIN_SPACE,
355 HW_VAR_SHORTGI_DENSITY,
356 HW_VAR_AMPDU_FACTOR,
357 HW_VAR_MCS_RATE_AVAILABLE,
358 HW_VAR_AC_PARAM,
359 HW_VAR_ACM_CTRL,
360 HW_VAR_DIS_Req_Qsize,
361 HW_VAR_CCX_CHNL_LOAD,
362 HW_VAR_CCX_NOISE_HISTOGRAM,
363 HW_VAR_CCX_CLM_NHM,
364 HW_VAR_TxOPLimit,
365 HW_VAR_TURBO_MODE,
366 HW_VAR_RF_STATE,
367 HW_VAR_RF_OFF_BY_HW,
368 HW_VAR_BUS_SPEED,
369 HW_VAR_SET_DEV_POWER,
370
371 HW_VAR_RCR,
372 HW_VAR_RATR_0,
373 HW_VAR_RRSR,
374 HW_VAR_CPU_RST,
375 HW_VAR_CHECK_BSSID,
376 HW_VAR_LBK_MODE,
377 HW_VAR_AES_11N_FIX,
378 HW_VAR_USB_RX_AGGR,
379 HW_VAR_USER_CONTROL_TURBO_MODE,
380 HW_VAR_RETRY_LIMIT,
381 HW_VAR_INIT_TX_RATE,
382 HW_VAR_TX_RATE_REG,
383 HW_VAR_EFUSE_USAGE,
384 HW_VAR_EFUSE_BYTES,
385 HW_VAR_AUTOLOAD_STATUS,
386 HW_VAR_RF_2R_DISABLE,
387 HW_VAR_SET_RPWM,
388 HW_VAR_H2C_FW_PWRMODE,
389 HW_VAR_H2C_FW_JOINBSSRPT,
390 HW_VAR_H2C_FW_MEDIASTATUSRPT,
391 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
392 HW_VAR_FW_PSMODE_STATUS,
393 HW_VAR_RESUME_CLK_ON,
394 HW_VAR_FW_LPS_ACTION,
395 HW_VAR_1X1_RECV_COMBINE,
396 HW_VAR_STOP_SEND_BEACON,
397 HW_VAR_TSF_TIMER,
398 HW_VAR_IO_CMD,
399
400 HW_VAR_RF_RECOVERY,
401 HW_VAR_H2C_FW_UPDATE_GTK,
402 HW_VAR_WF_MASK,
403 HW_VAR_WF_CRC,
404 HW_VAR_WF_IS_MAC_ADDR,
405 HW_VAR_H2C_FW_OFFLOAD,
406 HW_VAR_RESET_WFCRC,
407
408 HW_VAR_HANDLE_FW_C2H,
409 HW_VAR_DL_FW_RSVD_PAGE,
410 HW_VAR_AID,
411 HW_VAR_HW_SEQ_ENABLE,
412 HW_VAR_CORRECT_TSF,
413 HW_VAR_BCN_VALID,
414 HW_VAR_FWLPS_RF_ON,
415 HW_VAR_DUAL_TSF_RST,
416 HW_VAR_SWITCH_EPHY_WoWLAN,
417 HW_VAR_INT_MIGRATION,
418 HW_VAR_INT_AC,
419 HW_VAR_RF_TIMING,
420
421 HAL_DEF_WOWLAN,
422 HW_VAR_MRC,
423 HW_VAR_KEEP_ALIVE,
424 HW_VAR_NAV_UPPER,
425
426 HW_VAR_MGT_FILTER,
427 HW_VAR_CTRL_FILTER,
428 HW_VAR_DATA_FILTER,
429};
430
431enum _RT_MEDIA_STATUS {
432 RT_MEDIA_DISCONNECT = 0,
433 RT_MEDIA_CONNECT = 1
434};
435
436enum rt_oem_id {
437 RT_CID_DEFAULT = 0,
438 RT_CID_8187_ALPHA0 = 1,
439 RT_CID_8187_SERCOMM_PS = 2,
440 RT_CID_8187_HW_LED = 3,
441 RT_CID_8187_NETGEAR = 4,
442 RT_CID_WHQL = 5,
443 RT_CID_819X_CAMEO = 6,
444 RT_CID_819X_RUNTOP = 7,
445 RT_CID_819X_SENAO = 8,
446 RT_CID_TOSHIBA = 9,
447 RT_CID_819X_NETCORE = 10,
448 RT_CID_NETTRONIX = 11,
449 RT_CID_DLINK = 12,
450 RT_CID_PRONET = 13,
451 RT_CID_COREGA = 14,
452 RT_CID_819X_ALPHA = 15,
453 RT_CID_819X_SITECOM = 16,
454 RT_CID_CCX = 17,
455 RT_CID_819X_LENOVO = 18,
456 RT_CID_819X_QMI = 19,
457 RT_CID_819X_EDIMAX_BELKIN = 20,
458 RT_CID_819X_SERCOMM_BELKIN = 21,
459 RT_CID_819X_CAMEO1 = 22,
460 RT_CID_819X_MSI = 23,
461 RT_CID_819X_ACER = 24,
462 RT_CID_819X_HP = 27,
463 RT_CID_819X_CLEVO = 28,
464 RT_CID_819X_ARCADYAN_BELKIN = 29,
465 RT_CID_819X_SAMSUNG = 30,
466 RT_CID_819X_WNC_COREGA = 31,
467 RT_CID_819X_FOXCOON = 32,
468 RT_CID_819X_DELL = 33,
469 RT_CID_819X_PRONETS = 34,
470 RT_CID_819X_EDIMAX_ASUS = 35,
471 RT_CID_NETGEAR = 36,
472 RT_CID_PLANEX = 37,
473 RT_CID_CC_C = 38,
474};
475
476enum hw_descs {
477 HW_DESC_OWN,
478 HW_DESC_RXOWN,
479 HW_DESC_TX_NEXTDESC_ADDR,
480 HW_DESC_TXBUFF_ADDR,
481 HW_DESC_RXBUFF_ADDR,
482 HW_DESC_RXPKT_LEN,
483 HW_DESC_RXERO,
484 HW_DESC_RX_PREPARE,
485};
486
487enum prime_sc {
488 PRIME_CHNL_OFFSET_DONT_CARE = 0,
489 PRIME_CHNL_OFFSET_LOWER = 1,
490 PRIME_CHNL_OFFSET_UPPER = 2,
491};
492
493enum rf_type {
494 RF_1T1R = 0,
495 RF_1T2R = 1,
496 RF_2T2R = 2,
497 RF_2T2R_GREEN = 3,
498};
499
500enum ht_channel_width {
501 HT_CHANNEL_WIDTH_20 = 0,
502 HT_CHANNEL_WIDTH_20_40 = 1,
503 HT_CHANNEL_WIDTH_80 = 2,
504};
505
506/* Ref: 802.11i sepc D10.0 7.3.2.25.1
507Cipher Suites Encryption Algorithms */
508enum rt_enc_alg {
509 NO_ENCRYPTION = 0,
510 WEP40_ENCRYPTION = 1,
511 TKIP_ENCRYPTION = 2,
512 RSERVED_ENCRYPTION = 3,
513 AESCCMP_ENCRYPTION = 4,
514 WEP104_ENCRYPTION = 5,
515 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
516};
517
518enum rtl_hal_state {
519 _HAL_STATE_STOP = 0,
520 _HAL_STATE_START = 1,
521};
522
523enum rtl_desc92_rate {
524 DESC92_RATE1M = 0x00,
525 DESC92_RATE2M = 0x01,
526 DESC92_RATE5_5M = 0x02,
527 DESC92_RATE11M = 0x03,
528
529 DESC92_RATE6M = 0x04,
530 DESC92_RATE9M = 0x05,
531 DESC92_RATE12M = 0x06,
532 DESC92_RATE18M = 0x07,
533 DESC92_RATE24M = 0x08,
534 DESC92_RATE36M = 0x09,
535 DESC92_RATE48M = 0x0a,
536 DESC92_RATE54M = 0x0b,
537
538 DESC92_RATEMCS0 = 0x0c,
539 DESC92_RATEMCS1 = 0x0d,
540 DESC92_RATEMCS2 = 0x0e,
541 DESC92_RATEMCS3 = 0x0f,
542 DESC92_RATEMCS4 = 0x10,
543 DESC92_RATEMCS5 = 0x11,
544 DESC92_RATEMCS6 = 0x12,
545 DESC92_RATEMCS7 = 0x13,
546 DESC92_RATEMCS8 = 0x14,
547 DESC92_RATEMCS9 = 0x15,
548 DESC92_RATEMCS10 = 0x16,
549 DESC92_RATEMCS11 = 0x17,
550 DESC92_RATEMCS12 = 0x18,
551 DESC92_RATEMCS13 = 0x19,
552 DESC92_RATEMCS14 = 0x1a,
553 DESC92_RATEMCS15 = 0x1b,
554 DESC92_RATEMCS15_SG = 0x1c,
555 DESC92_RATEMCS32 = 0x20,
556};
557
558enum rtl_var_map {
559 /*reg map */
560 SYS_ISO_CTRL = 0,
561 SYS_FUNC_EN,
562 SYS_CLK,
563 MAC_RCR_AM,
564 MAC_RCR_AB,
565 MAC_RCR_ACRC32,
566 MAC_RCR_ACF,
567 MAC_RCR_AAP,
568 MAC_HIMR,
569 MAC_HIMRE,
570 MAC_HSISR,
571
572 /*efuse map */
573 EFUSE_TEST,
574 EFUSE_CTRL,
575 EFUSE_CLK,
576 EFUSE_CLK_CTRL,
577 EFUSE_PWC_EV12V,
578 EFUSE_FEN_ELDR,
579 EFUSE_LOADER_CLK_EN,
580 EFUSE_ANA8M,
581 EFUSE_HWSET_MAX_SIZE,
582 EFUSE_MAX_SECTION_MAP,
583 EFUSE_REAL_CONTENT_SIZE,
584 EFUSE_OOB_PROTECT_BYTES_LEN,
585 EFUSE_ACCESS,
586
587 /*CAM map */
588 RWCAM,
589 WCAMI,
590 RCAMO,
591 CAMDBG,
592 SECR,
593 SEC_CAM_NONE,
594 SEC_CAM_WEP40,
595 SEC_CAM_TKIP,
596 SEC_CAM_AES,
597 SEC_CAM_WEP104,
598
599 /*IMR map */
600 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
601 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
602 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
603 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
604 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
605 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
606 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
607 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
608 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
609 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
610 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
611 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
612 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
613 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
614 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
615 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
616 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
617 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
618 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
619 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
620 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
621 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
622 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
623 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
624 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
625 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
626 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
627 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
628 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
629 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
630 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
631 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
632 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
633 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
634 * RTL_IMR_TBDER) */
635 RTL_IMR_C2HCMD, /*fw interrupt*/
636
637 /*CCK Rates, TxHT = 0 */
638 RTL_RC_CCK_RATE1M,
639 RTL_RC_CCK_RATE2M,
640 RTL_RC_CCK_RATE5_5M,
641 RTL_RC_CCK_RATE11M,
642
643 /*OFDM Rates, TxHT = 0 */
644 RTL_RC_OFDM_RATE6M,
645 RTL_RC_OFDM_RATE9M,
646 RTL_RC_OFDM_RATE12M,
647 RTL_RC_OFDM_RATE18M,
648 RTL_RC_OFDM_RATE24M,
649 RTL_RC_OFDM_RATE36M,
650 RTL_RC_OFDM_RATE48M,
651 RTL_RC_OFDM_RATE54M,
652
653 RTL_RC_HT_RATEMCS7,
654 RTL_RC_HT_RATEMCS15,
655
656 /*keep it last */
657 RTL_VAR_MAP_MAX,
658};
659
660/*Firmware PS mode for control LPS.*/
661enum _fw_ps_mode {
662 FW_PS_ACTIVE_MODE = 0,
663 FW_PS_MIN_MODE = 1,
664 FW_PS_MAX_MODE = 2,
665 FW_PS_DTIM_MODE = 3,
666 FW_PS_VOIP_MODE = 4,
667 FW_PS_UAPSD_WMM_MODE = 5,
668 FW_PS_UAPSD_MODE = 6,
669 FW_PS_IBSS_MODE = 7,
670 FW_PS_WWLAN_MODE = 8,
671 FW_PS_PM_Radio_Off = 9,
672 FW_PS_PM_Card_Disable = 10,
673};
674
675enum rt_psmode {
676 EACTIVE, /*Active/Continuous access. */
677 EMAXPS, /*Max power save mode. */
678 EFASTPS, /*Fast power save mode. */
679 EAUTOPS, /*Auto power save mode. */
680};
681
682/*LED related.*/
683enum led_ctl_mode {
684 LED_CTL_POWER_ON = 1,
685 LED_CTL_LINK = 2,
686 LED_CTL_NO_LINK = 3,
687 LED_CTL_TX = 4,
688 LED_CTL_RX = 5,
689 LED_CTL_SITE_SURVEY = 6,
690 LED_CTL_POWER_OFF = 7,
691 LED_CTL_START_TO_LINK = 8,
692 LED_CTL_START_WPS = 9,
693 LED_CTL_STOP_WPS = 10,
694};
695
696enum rtl_led_pin {
697 LED_PIN_GPIO0,
698 LED_PIN_LED0,
699 LED_PIN_LED1,
700 LED_PIN_LED2
701};
702
703/*QoS related.*/
704/*acm implementation method.*/
705enum acm_method {
706 eAcmWay0_SwAndHw = 0,
707 eAcmWay1_HW = 1,
708 EACMWAY2_SW = 2,
709};
710
711enum macphy_mode {
712 SINGLEMAC_SINGLEPHY = 0,
713 DUALMAC_DUALPHY,
714 DUALMAC_SINGLEPHY,
715};
716
717enum band_type {
718 BAND_ON_2_4G = 0,
719 BAND_ON_5G,
720 BAND_ON_BOTH,
721 BANDMAX
722};
723
724/*aci/aifsn Field.
725Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
726union aci_aifsn {
727 u8 char_data;
728
729 struct {
730 u8 aifsn:4;
731 u8 acm:1;
732 u8 aci:2;
733 u8 reserved:1;
734 } f; /* Field */
735};
736
737/*mlme related.*/
738enum wireless_mode {
739 WIRELESS_MODE_UNKNOWN = 0x00,
740 WIRELESS_MODE_A = 0x01,
741 WIRELESS_MODE_B = 0x02,
742 WIRELESS_MODE_G = 0x04,
743 WIRELESS_MODE_AUTO = 0x08,
744 WIRELESS_MODE_N_24G = 0x10,
745 WIRELESS_MODE_N_5G = 0x20,
746 WIRELESS_MODE_AC_5G = 0x40,
747 WIRELESS_MODE_AC_24G = 0x80
748};
749
750#define IS_WIRELESS_MODE_A(wirelessmode) \
751 (wirelessmode == WIRELESS_MODE_A)
752#define IS_WIRELESS_MODE_B(wirelessmode) \
753 (wirelessmode == WIRELESS_MODE_B)
754#define IS_WIRELESS_MODE_G(wirelessmode) \
755 (wirelessmode == WIRELESS_MODE_G)
756#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
757 (wirelessmode == WIRELESS_MODE_N_24G)
758#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
759 (wirelessmode == WIRELESS_MODE_N_5G)
760
761enum ratr_table_mode {
762 RATR_INX_WIRELESS_NGB = 0,
763 RATR_INX_WIRELESS_NG = 1,
764 RATR_INX_WIRELESS_NB = 2,
765 RATR_INX_WIRELESS_N = 3,
766 RATR_INX_WIRELESS_GB = 4,
767 RATR_INX_WIRELESS_G = 5,
768 RATR_INX_WIRELESS_B = 6,
769 RATR_INX_WIRELESS_MC = 7,
770 RATR_INX_WIRELESS_A = 8,
771 RATR_INX_WIRELESS_AC_5N = 8,
772 RATR_INX_WIRELESS_AC_24N = 9,
773};
774
775enum rtl_link_state {
776 MAC80211_NOLINK = 0,
777 MAC80211_LINKING = 1,
778 MAC80211_LINKED = 2,
779 MAC80211_LINKED_SCANNING = 3,
780};
781
782enum act_category {
783 ACT_CAT_QOS = 1,
784 ACT_CAT_DLS = 2,
785 ACT_CAT_BA = 3,
786 ACT_CAT_HT = 7,
787 ACT_CAT_WMM = 17,
788};
789
790enum ba_action {
791 ACT_ADDBAREQ = 0,
792 ACT_ADDBARSP = 1,
793 ACT_DELBA = 2,
794};
795
796enum rt_polarity_ctl {
797 RT_POLARITY_LOW_ACT = 0,
798 RT_POLARITY_HIGH_ACT = 1,
799};
800
801struct octet_string {
802 u8 *octet;
803 u16 length;
804};
805
806struct rtl_hdr_3addr {
807 __le16 frame_ctl;
808 __le16 duration_id;
809 u8 addr1[ETH_ALEN];
810 u8 addr2[ETH_ALEN];
811 u8 addr3[ETH_ALEN];
812 __le16 seq_ctl;
813 u8 payload[0];
814} __packed;
815
816struct rtl_info_element {
817 u8 id;
818 u8 len;
819 u8 data[0];
820} __packed;
821
822struct rtl_probe_rsp {
823 struct rtl_hdr_3addr header;
824 u32 time_stamp[2];
825 __le16 beacon_interval;
826 __le16 capability;
827 /*SSID, supported rates, FH params, DS params,
828 CF params, IBSS params, TIM (if beacon), RSN */
829 struct rtl_info_element info_element[0];
830} __packed;
831
832/*LED related.*/
833/*ledpin Identify how to implement this SW led.*/
834struct rtl_led {
835 void *hw;
836 enum rtl_led_pin ledpin;
837 bool ledon;
838};
839
840struct rtl_led_ctl {
841 bool led_opendrain;
842 struct rtl_led sw_led0;
843 struct rtl_led sw_led1;
844};
845
846struct rtl_qos_parameters {
847 __le16 cw_min;
848 __le16 cw_max;
849 u8 aifs;
850 u8 flag;
851 __le16 tx_op;
852} __packed;
853
854struct rt_smooth_data {
855 u32 elements[100]; /*array to store values */
856 u32 index; /*index to current array to store */
857 u32 total_num; /*num of valid elements */
858 u32 total_val; /*sum of valid elements */
859};
860
861struct false_alarm_statistics {
862 u32 cnt_parity_fail;
863 u32 cnt_rate_illegal;
864 u32 cnt_crc8_fail;
865 u32 cnt_mcs_fail;
866 u32 cnt_fast_fsync_fail;
867 u32 cnt_sb_search_fail;
868 u32 cnt_ofdm_fail;
869 u32 cnt_cck_fail;
870 u32 cnt_all;
871 u32 cnt_ofdm_cca;
872 u32 cnt_cck_cca;
873 u32 cnt_cca_all;
874 u32 cnt_bw_usc;
875 u32 cnt_bw_lsc;
876};
877
878struct init_gain {
879 u8 xaagccore1;
880 u8 xbagccore1;
881 u8 xcagccore1;
882 u8 xdagccore1;
883 u8 cca;
884
885};
886
887struct wireless_stats {
888 unsigned long txbytesunicast;
889 unsigned long txbytesmulticast;
890 unsigned long txbytesbroadcast;
891 unsigned long rxbytesunicast;
892
893 long rx_snr_db[4];
894 /*Correct smoothed ss in Dbm, only used
895 in driver to report real power now. */
896 long recv_signal_power;
897 long signal_quality;
898 long last_sigstrength_inpercent;
899
900 u32 rssi_calculate_cnt;
901
902 /*Transformed, in dbm. Beautified signal
903 strength for UI, not correct. */
904 long signal_strength;
905
906 u8 rx_rssi_percentage[4];
907 u8 rx_evm_dbm[4];
908 u8 rx_evm_percentage[2];
909
910 u16 rx_cfo_short[4];
911 u16 rx_cfo_tail[4];
912
913 struct rt_smooth_data ui_rssi;
914 struct rt_smooth_data ui_link_quality;
915};
916
917struct rate_adaptive {
918 u8 rate_adaptive_disabled;
919 u8 ratr_state;
920 u16 reserve;
921
922 u32 high_rssi_thresh_for_ra;
923 u32 high2low_rssi_thresh_for_ra;
924 u8 low2high_rssi_thresh_for_ra40m;
925 u32 low_rssi_thresh_for_ra40m;
926 u8 low2high_rssi_thresh_for_ra20m;
927 u32 low_rssi_thresh_for_ra20m;
928 u32 upper_rssi_threshold_ratr;
929 u32 middleupper_rssi_threshold_ratr;
930 u32 middle_rssi_threshold_ratr;
931 u32 middlelow_rssi_threshold_ratr;
932 u32 low_rssi_threshold_ratr;
933 u32 ultralow_rssi_threshold_ratr;
934 u32 low_rssi_threshold_ratr_40m;
935 u32 low_rssi_threshold_ratr_20m;
936 u8 ping_rssi_enable;
937 u32 ping_rssi_ratr;
938 u32 ping_rssi_thresh_for_ra;
939 u32 last_ratr;
940 u8 pre_ratr_state;
941 u8 ldpc_thres;
942 bool use_ldpc;
943 bool lower_rts_rate;
944 bool is_special_data;
945};
946
947struct regd_pair_mapping {
948 u16 reg_dmnenum;
949 u16 reg_5ghz_ctl;
950 u16 reg_2ghz_ctl;
951};
952
953struct dynamic_primary_cca {
954 u8 pricca_flag;
955 u8 intf_flag;
956 u8 intf_type;
957 u8 dup_rts_flag;
958 u8 monitor_flag;
959 u8 ch_offset;
960 u8 mf_state;
961};
962
963struct rtl_regulatory {
964 char alpha2[2];
965 u16 country_code;
966 u16 max_power_level;
967 u32 tp_scale;
968 u16 current_rd;
969 u16 current_rd_ext;
970 int16_t power_limit;
971 struct regd_pair_mapping *regpair;
972};
973
974struct rtl_rfkill {
975 bool rfkill_state; /*0 is off, 1 is on */
976};
977
978/*for P2P PS**/
979#define P2P_MAX_NOA_NUM 2
980
981enum p2p_role {
982 P2P_ROLE_DISABLE = 0,
983 P2P_ROLE_DEVICE = 1,
984 P2P_ROLE_CLIENT = 2,
985 P2P_ROLE_GO = 3
986};
987
988enum p2p_ps_state {
989 P2P_PS_DISABLE = 0,
990 P2P_PS_ENABLE = 1,
991 P2P_PS_SCAN = 2,
992 P2P_PS_SCAN_DONE = 3,
993 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
994};
995
996enum p2p_ps_mode {
997 P2P_PS_NONE = 0,
998 P2P_PS_CTWINDOW = 1,
999 P2P_PS_NOA = 2,
1000 P2P_PS_MIX = 3, /* CTWindow and NoA */
1001};
1002
1003struct rtl_p2p_ps_info {
1004 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1005 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1006 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1007 /* Client traffic window. A period of time in TU after TBTT. */
1008 u8 ctwindow;
1009 u8 opp_ps; /* opportunistic power save. */
1010 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1011 /* Count for owner, Type of client. */
1012 u8 noa_count_type[P2P_MAX_NOA_NUM];
1013 /* Max duration for owner, preferred or min acceptable duration
1014 * for client.
1015 */
1016 u32 noa_duration[P2P_MAX_NOA_NUM];
1017 /* Length of interval for owner, preferred or max acceptable intervali
1018 * of client.
1019 */
1020 u32 noa_interval[P2P_MAX_NOA_NUM];
1021 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1022 u32 noa_start_time[P2P_MAX_NOA_NUM];
1023};
1024
1025struct p2p_ps_offload_t {
1026 u8 offload_en:1;
1027 u8 role:1; /* 1: Owner, 0: Client */
1028 u8 ctwindow_en:1;
1029 u8 noa0_en:1;
1030 u8 noa1_en:1;
1031 u8 allstasleep:1;
1032 u8 discovery:1;
1033 u8 reserved:1;
1034};
1035
1036#define IQK_MATRIX_REG_NUM 8
1037#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1038
1039struct iqk_matrix_regs {
1040 bool iqk_done;
1041 long value[1][IQK_MATRIX_REG_NUM];
1042};
1043
1044struct phy_parameters {
1045 u16 length;
1046 u32 *pdata;
1047};
1048
1049enum hw_param_tab_index {
1050 PHY_REG_2T,
1051 PHY_REG_1T,
1052 PHY_REG_PG,
1053 RADIOA_2T,
1054 RADIOB_2T,
1055 RADIOA_1T,
1056 RADIOB_1T,
1057 MAC_REG,
1058 AGCTAB_2T,
1059 AGCTAB_1T,
1060 MAX_TAB
1061};
1062
1063struct rtl_phy {
1064 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1065 struct init_gain initgain_backup;
1066 enum io_type current_io_type;
1067
1068 u8 rf_mode;
1069 u8 rf_type;
1070 u8 current_chan_bw;
1071 u8 set_bwmode_inprogress;
1072 u8 sw_chnl_inprogress;
1073 u8 sw_chnl_stage;
1074 u8 sw_chnl_step;
1075 u8 current_channel;
1076 u8 h2c_box_num;
1077 u8 set_io_inprogress;
1078 u8 lck_inprogress;
1079
1080 /* record for power tracking */
1081 s32 reg_e94;
1082 s32 reg_e9c;
1083 s32 reg_ea4;
1084 s32 reg_eac;
1085 s32 reg_eb4;
1086 s32 reg_ebc;
1087 s32 reg_ec4;
1088 s32 reg_ecc;
1089 u8 rfpienable;
1090 u8 reserve_0;
1091 u16 reserve_1;
1092 u32 reg_c04, reg_c08, reg_874;
1093 u32 adda_backup[16];
1094 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1095 u32 iqk_bb_backup[10];
1096 bool iqk_initialized;
1097
1098 bool rfpath_rx_enable[MAX_RF_PATH];
1099 u8 reg_837;
1100 /* Dual mac */
1101 bool need_iqk;
1102 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1103
1104 bool rfpi_enable;
1105 bool iqk_in_progress;
1106
1107 u8 pwrgroup_cnt;
1108 u8 cck_high_power;
1109 /* MAX_PG_GROUP groups of pwr diff by rates */
1110 u32 mcs_offset[MAX_PG_GROUP][16];
1111 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1112 [TX_PWR_BY_RATE_NUM_RF]
1113 [TX_PWR_BY_RATE_NUM_RF]
1114 [TX_PWR_BY_RATE_NUM_SECTION];
1115 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1116 [TX_PWR_BY_RATE_NUM_RF]
1117 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1118 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1119 [TX_PWR_BY_RATE_NUM_RF]
1120 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1121 u8 default_initialgain[4];
1122
1123 /* the current Tx power level */
1124 u8 cur_cck_txpwridx;
1125 u8 cur_ofdm24g_txpwridx;
1126 u8 cur_bw20_txpwridx;
1127 u8 cur_bw40_txpwridx;
1128
1129 u32 rfreg_chnlval[2];
1130 bool apk_done;
1131 u32 reg_rf3c[2]; /* pathA / pathB */
1132
1133 u32 backup_rf_0x1a;/*92ee*/
1134 /* bfsync */
1135 u8 framesync;
1136 u32 framesync_c34;
1137
1138 u8 num_total_rfpath;
1139 struct phy_parameters hwparam_tables[MAX_TAB];
1140 u16 rf_pathmap;
1141
1142 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1143 enum rt_polarity_ctl polarity_ctl;
1144};
1145
1146#define MAX_TID_COUNT 9
1147#define RTL_AGG_STOP 0
1148#define RTL_AGG_PROGRESS 1
1149#define RTL_AGG_START 2
1150#define RTL_AGG_OPERATIONAL 3
1151#define RTL_AGG_OFF 0
1152#define RTL_AGG_ON 1
1153#define RTL_RX_AGG_START 1
1154#define RTL_RX_AGG_STOP 0
1155#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1156#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1157
1158struct rtl_ht_agg {
1159 u16 txq_id;
1160 u16 wait_for_ba;
1161 u16 start_idx;
1162 u64 bitmap;
1163 u32 rate_n_flags;
1164 u8 agg_state;
1165 u8 rx_agg_state;
1166};
1167
1168struct rssi_sta {
1169 long undec_sm_pwdb;
1170 long undec_sm_cck;
1171};
1172
1173struct rtl_tid_data {
1174 u16 seq_number;
1175 struct rtl_ht_agg agg;
1176};
1177
1178struct rtl_sta_info {
1179 struct list_head list;
1180 u8 ratr_index;
1181 u8 wireless_mode;
1182 u8 mimo_ps;
1183 u8 mac_addr[ETH_ALEN];
1184 struct rtl_tid_data tids[MAX_TID_COUNT];
1185
1186 /* just used for ap adhoc or mesh*/
1187 struct rssi_sta rssi_stat;
1188} __packed;
1189
1190struct rtl_priv;
1191struct rtl_io {
1192 struct device *dev;
1193 struct mutex bb_mutex;
1194
1195 /*PCI MEM map */
1196 unsigned long pci_mem_end; /*shared mem end */
1197 unsigned long pci_mem_start; /*shared mem start */
1198
1199 /*PCI IO map */
1200 unsigned long pci_base_addr; /*device I/O address */
1201
1202 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1203 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1204 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1205 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1206 u16 len);
1207
1208 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1209 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1210 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1211
1212};
1213
1214struct rtl_mac {
1215 u8 mac_addr[ETH_ALEN];
1216 u8 mac80211_registered;
1217 u8 beacon_enabled;
1218
1219 u32 tx_ss_num;
1220 u32 rx_ss_num;
1221
1222 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1223 struct ieee80211_hw *hw;
1224 struct ieee80211_vif *vif;
1225 enum nl80211_iftype opmode;
1226
1227 /*Probe Beacon management */
1228 struct rtl_tid_data tids[MAX_TID_COUNT];
1229 enum rtl_link_state link_state;
1230
1231 int n_channels;
1232 int n_bitrates;
1233
1234 bool offchan_delay;
1235 u8 p2p; /*using p2p role*/
1236 bool p2p_in_use;
1237
1238 /*filters */
1239 u32 rx_conf;
1240 u16 rx_mgt_filter;
1241 u16 rx_ctrl_filter;
1242 u16 rx_data_filter;
1243
1244 bool act_scanning;
1245 u8 cnt_after_linked;
1246 bool skip_scan;
1247
1248 /* early mode */
1249 /* skb wait queue */
1250 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1251
1252 /*RDG*/
1253 bool rdg_en;
1254
1255 /*AP*/
1256 u8 bssid[6];
1257 u32 vendor;
1258 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1259 u32 basic_rates; /* b/g rates */
1260 u8 ht_enable;
1261 u8 sgi_40;
1262 u8 sgi_20;
1263 u8 bw_40;
1264 u8 mode; /* wireless mode */
1265 u8 slot_time;
1266 u8 short_preamble;
1267 u8 use_cts_protect;
1268 u8 cur_40_prime_sc;
1269 u8 cur_40_prime_sc_bk;
1270 u8 cur_80_prime_sc;
1271 u64 tsf;
1272 u8 retry_short;
1273 u8 retry_long;
1274 u16 assoc_id;
1275 bool hiddenssid;
1276
1277 /*IBSS*/
1278 int beacon_interval;
1279
1280 /*AMPDU*/
1281 u8 min_space_cfg; /*For Min spacing configurations */
1282 u8 max_mss_density;
1283 u8 current_ampdu_factor;
1284 u8 current_ampdu_density;
1285
1286 /*QOS & EDCA */
1287 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1288 struct rtl_qos_parameters ac[AC_MAX];
1289
1290 /* counters */
1291 u64 last_txok_cnt;
1292 u64 last_rxok_cnt;
1293 u32 last_bt_edca_ul;
1294 u32 last_bt_edca_dl;
1295};
1296
1297struct btdm_8723 {
1298 bool all_off;
1299 bool agc_table_en;
1300 bool adc_back_off_on;
1301 bool b2_ant_hid_en;
1302 bool low_penalty_rate_adaptive;
1303 bool rf_rx_lpf_shrink;
1304 bool reject_aggre_pkt;
1305 bool tra_tdma_on;
1306 u8 tra_tdma_nav;
1307 u8 tra_tdma_ant;
1308 bool tdma_on;
1309 u8 tdma_ant;
1310 u8 tdma_nav;
1311 u8 tdma_dac_swing;
1312 u8 fw_dac_swing_lvl;
1313 bool ps_tdma_on;
1314 u8 ps_tdma_byte[5];
1315 bool pta_on;
1316 u32 val_0x6c0;
1317 u32 val_0x6c8;
1318 u32 val_0x6cc;
1319 bool sw_dac_swing_on;
1320 u32 sw_dac_swing_lvl;
1321 u32 wlan_act_hi;
1322 u32 wlan_act_lo;
1323 u32 bt_retry_index;
1324 bool dec_bt_pwr;
1325 bool ignore_wlan_act;
1326};
1327
1328struct bt_coexist_8723 {
1329 u32 high_priority_tx;
1330 u32 high_priority_rx;
1331 u32 low_priority_tx;
1332 u32 low_priority_rx;
1333 u8 c2h_bt_info;
1334 bool c2h_bt_info_req_sent;
1335 bool c2h_bt_inquiry_page;
1336 u32 bt_inq_page_start_time;
1337 u8 bt_retry_cnt;
1338 u8 c2h_bt_info_original;
1339 u8 bt_inquiry_page_cnt;
1340 struct btdm_8723 btdm;
1341};
1342
1343struct rtl_hal {
1344 struct ieee80211_hw *hw;
1345 bool driver_is_goingto_unload;
1346 bool up_first_time;
1347 bool first_init;
1348 bool being_init_adapter;
1349 bool bbrf_ready;
1350 bool mac_func_enable;
1351 bool pre_edcca_enable;
1352 struct bt_coexist_8723 hal_coex_8723;
1353
1354 enum intf_type interface;
1355 u16 hw_type; /*92c or 92d or 92s and so on */
1356 u8 ic_class;
1357 u8 oem_id;
1358 u32 version; /*version of chip */
1359 u8 state; /*stop 0, start 1 */
1360 u8 board_type;
1361
1362 /*firmware */
1363 u32 fwsize;
1364 u8 *pfirmware;
1365 u16 fw_version;
1366 u16 fw_subversion;
1367 bool h2c_setinprogress;
1368 u8 last_hmeboxnum;
1369 bool fw_ready;
1370 /*Reserve page start offset except beacon in TxQ. */
1371 u8 fw_rsvdpage_startoffset;
1372 u8 h2c_txcmd_seq;
1373 u8 current_ra_rate;
1374
1375 /* FW Cmd IO related */
1376 u16 fwcmd_iomap;
1377 u32 fwcmd_ioparam;
1378 bool set_fwcmd_inprogress;
1379 u8 current_fwcmd_io;
1380
1381 struct p2p_ps_offload_t p2p_ps_offload;
1382 bool fw_clk_change_in_progress;
1383 bool allow_sw_to_change_hwclc;
1384 u8 fw_ps_state;
1385 /**/
1386 bool driver_going2unload;
1387
1388 /*AMPDU init min space*/
1389 u8 minspace_cfg; /*For Min spacing configurations */
1390
1391 /* Dual mac */
1392 enum macphy_mode macphymode;
1393 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1394 enum band_type current_bandtypebackup;
1395 enum band_type bandset;
1396 /* dual MAC 0--Mac0 1--Mac1 */
1397 u32 interfaceindex;
1398 /* just for DualMac S3S4 */
1399 u8 macphyctl_reg;
1400 bool earlymode_enable;
1401 u8 max_earlymode_num;
1402 /* Dual mac*/
1403 bool during_mac0init_radiob;
1404 bool during_mac1init_radioa;
1405 bool reloadtxpowerindex;
1406 /* True if IMR or IQK have done
1407 for 2.4G in scan progress */
1408 bool load_imrandiqk_setting_for2g;
1409
1410 bool disable_amsdu_8k;
1411 bool master_of_dmsp;
1412 bool slave_of_dmsp;
1413
1414 u16 rx_tag;/*for 92ee*/
1415 u8 rts_en;
1416};
1417
1418struct rtl_security {
1419 /*default 0 */
1420 bool use_sw_sec;
1421
1422 bool being_setkey;
1423 bool use_defaultkey;
1424 /*Encryption Algorithm for Unicast Packet */
1425 enum rt_enc_alg pairwise_enc_algorithm;
1426 /*Encryption Algorithm for Brocast/Multicast */
1427 enum rt_enc_alg group_enc_algorithm;
1428 /*Cam Entry Bitmap */
1429 u32 hwsec_cam_bitmap;
1430 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1431 /*local Key buffer, indx 0 is for
1432 pairwise key 1-4 is for agoup key. */
1433 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1434 u8 key_len[KEY_BUF_SIZE];
1435
1436 /*The pointer of Pairwise Key,
1437 it always points to KeyBuf[4] */
1438 u8 *pairwise_key;
1439};
1440
1441#define ASSOCIATE_ENTRY_NUM 33
1442
1443struct fast_ant_training {
1444 u8 bssid[6];
1445 u8 antsel_rx_keep_0;
1446 u8 antsel_rx_keep_1;
1447 u8 antsel_rx_keep_2;
1448 u32 ant_sum[7];
1449 u32 ant_cnt[7];
1450 u32 ant_ave[7];
1451 u8 fat_state;
1452 u32 train_idx;
1453 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1454 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1455 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1456 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1457 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1458 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1459 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1460 u8 rx_idle_ant;
1461 bool becomelinked;
1462};
1463
1464struct dm_phy_dbg_info {
1465 char rx_snrdb[4];
1466 u64 num_qry_phy_status;
1467 u64 num_qry_phy_status_cck;
1468 u64 num_qry_phy_status_ofdm;
1469 u16 num_qry_beacon_pkt;
1470 u16 num_non_be_pkt;
1471 s32 rx_evm[4];
1472};
1473
1474struct rtl_dm {
1475 /*PHY status for Dynamic Management */
1476 long entry_min_undec_sm_pwdb;
1477 long undec_sm_cck;
1478 long undec_sm_pwdb; /*out dm */
1479 long entry_max_undec_sm_pwdb;
1480 s32 ofdm_pkt_cnt;
1481 bool dm_initialgain_enable;
1482 bool dynamic_txpower_enable;
1483 bool current_turbo_edca;
1484 bool is_any_nonbepkts; /*out dm */
1485 bool is_cur_rdlstate;
1486 bool txpower_trackinginit;
1487 bool disable_framebursting;
1488 bool cck_inch14;
1489 bool txpower_tracking;
1490 bool useramask;
1491 bool rfpath_rxenable[4];
1492 bool inform_fw_driverctrldm;
1493 bool current_mrc_switch;
1494 u8 txpowercount;
1495 u8 powerindex_backup[6];
1496
1497 u8 thermalvalue_rxgain;
1498 u8 thermalvalue_iqk;
1499 u8 thermalvalue_lck;
1500 u8 thermalvalue;
1501 u8 last_dtp_lvl;
1502 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1503 u8 thermalvalue_avg_index;
1504 bool done_txpower;
1505 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1506 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1507 u8 dm_flag_tmp;
1508 u8 dm_type;
1509 u8 dm_rssi_sel;
1510 u8 txpower_track_control;
1511 bool interrupt_migration;
1512 bool disable_tx_int;
1513 char ofdm_index[MAX_RF_PATH];
1514 u8 default_ofdm_index;
1515 u8 default_cck_index;
1516 char cck_index;
1517 char delta_power_index[MAX_RF_PATH];
1518 char delta_power_index_last[MAX_RF_PATH];
1519 char power_index_offset[MAX_RF_PATH];
1520 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1521 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1522 char remnant_cck_idx;
1523 bool modify_txagc_flag_path_a;
1524 bool modify_txagc_flag_path_b;
1525
1526 bool one_entry_only;
1527 struct dm_phy_dbg_info dbginfo;
1528
1529 /* Dynamic ATC switch */
1530 bool atc_status;
1531 bool large_cfo_hit;
1532 bool is_freeze;
1533 int cfo_tail[2];
1534 int cfo_ave_pre;
1535 int crystal_cap;
1536 u8 cfo_threshold;
1537 u32 packet_count;
1538 u32 packet_count_pre;
1539 u8 tx_rate;
1540
1541 /*88e tx power tracking*/
1542 u8 swing_idx_ofdm[MAX_RF_PATH];
1543 u8 swing_idx_ofdm_cur;
1544 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1545 bool swing_flag_ofdm;
1546 u8 swing_idx_cck;
1547 u8 swing_idx_cck_cur;
1548 u8 swing_idx_cck_base;
1549 bool swing_flag_cck;
1550
1551 char swing_diff_2g;
1552 char swing_diff_5g;
1553
1554 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1555 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1556 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1557 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1558 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1559 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1560 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1561 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1562 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1563 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1564 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1565 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1566 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1567 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1568
1569 /* DMSP */
1570 bool supp_phymode_switch;
1571
1572 /* DulMac */
1573 struct fast_ant_training fat_table;
1574
1575 u8 resp_tx_path;
1576 u8 path_sel;
1577 u32 patha_sum;
1578 u32 pathb_sum;
1579 u32 patha_cnt;
1580 u32 pathb_cnt;
1581
1582 u8 pre_channel;
1583 u8 *p_channel;
1584 u8 linked_interval;
1585
1586 u64 last_tx_ok_cnt;
1587 u64 last_rx_ok_cnt;
1588};
1589
1590#define EFUSE_MAX_LOGICAL_SIZE 512
1591
1592struct rtl_efuse {
1593 bool autoLoad_ok;
1594 bool bootfromefuse;
1595 u16 max_physical_size;
1596
1597 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1598 u16 efuse_usedbytes;
1599 u8 efuse_usedpercentage;
1600#ifdef EFUSE_REPG_WORKAROUND
1601 bool efuse_re_pg_sec1flag;
1602 u8 efuse_re_pg_data[8];
1603#endif
1604
1605 u8 autoload_failflag;
1606 u8 autoload_status;
1607
1608 short epromtype;
1609 u16 eeprom_vid;
1610 u16 eeprom_did;
1611 u16 eeprom_svid;
1612 u16 eeprom_smid;
1613 u8 eeprom_oemid;
1614 u16 eeprom_channelplan;
1615 u8 eeprom_version;
1616 u8 board_type;
1617 u8 external_pa;
1618
1619 u8 dev_addr[6];
1620 u8 wowlan_enable;
1621 u8 antenna_div_cfg;
1622 u8 antenna_div_type;
1623
1624 bool txpwr_fromeprom;
1625 u8 eeprom_crystalcap;
1626 u8 eeprom_tssi[2];
1627 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1628 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1629 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1630 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1631 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1632 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1633
1634 u8 internal_pa_5g[2]; /* pathA / pathB */
1635 u8 eeprom_c9;
1636 u8 eeprom_cc;
1637
1638 /*For power group */
1639 u8 eeprom_pwrgroup[2][3];
1640 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1641 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1642
1643 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1644 /*For HT 40MHZ pwr */
1645 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1646 /*For HT 40MHZ pwr */
1647 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1648
1649 /*--------------------------------------------------------*
1650 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1651 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1652 * define new arrays in Windows code.
1653 * BUT, in linux code, we use the same array for all ICs.
1654 *
1655 * The Correspondance relation between two arrays is:
1656 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1657 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1658 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1659 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1660 *
1661 * Sizes of these arrays are decided by the larger ones.
1662 */
1663 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1664 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1665 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1666 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1667
1668 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1669 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1670 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1671 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1672 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1673 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1674
1675 u8 txpwr_safetyflag; /* Band edge enable flag */
1676 u16 eeprom_txpowerdiff;
1677 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1678 u8 antenna_txpwdiff[3];
1679
1680 u8 eeprom_regulatory;
1681 u8 eeprom_thermalmeter;
1682 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1683 u16 tssi_13dbm;
1684 u8 crystalcap; /* CrystalCap. */
1685 u8 delta_iqk;
1686 u8 delta_lck;
1687
1688 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1689 bool apk_thermalmeterignore;
1690
1691 bool b1x1_recvcombine;
1692 bool b1ss_support;
1693
1694 /*channel plan */
1695 u8 channel_plan;
1696};
1697
1698struct rtl_ps_ctl {
1699 bool pwrdomain_protect;
1700 bool in_powersavemode;
1701 bool rfchange_inprogress;
1702 bool swrf_processing;
1703 bool hwradiooff;
1704 /*
1705 * just for PCIE ASPM
1706 * If it supports ASPM, Offset[560h] = 0x40,
1707 * otherwise Offset[560h] = 0x00.
1708 * */
1709 bool support_aspm;
1710 bool support_backdoor;
1711
1712 /*for LPS */
1713 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1714 bool swctrl_lps;
1715 bool leisure_ps;
1716 bool fwctrl_lps;
1717 u8 fwctrl_psmode;
1718 /*For Fw control LPS mode */
1719 u8 reg_fwctrl_lps;
1720 /*Record Fw PS mode status. */
1721 bool fw_current_inpsmode;
1722 u8 reg_max_lps_awakeintvl;
1723 bool report_linked;
1724 bool low_power_enable;/*for 32k*/
1725
1726 /*for IPS */
1727 bool inactiveps;
1728
1729 u32 rfoff_reason;
1730
1731 /*RF OFF Level */
1732 u32 cur_ps_level;
1733 u32 reg_rfps_level;
1734
1735 /*just for PCIE ASPM */
1736 u8 const_amdpci_aspm;
1737 bool pwrdown_mode;
1738
1739 enum rf_pwrstate inactive_pwrstate;
1740 enum rf_pwrstate rfpwr_state; /*cur power state */
1741
1742 /* for SW LPS*/
1743 bool sw_ps_enabled;
1744 bool state;
1745 bool state_inap;
1746 bool multi_buffered;
1747 u16 nullfunc_seq;
1748 unsigned int dtim_counter;
1749 unsigned int sleep_ms;
1750 unsigned long last_sleep_jiffies;
1751 unsigned long last_awake_jiffies;
1752 unsigned long last_delaylps_stamp_jiffies;
1753 unsigned long last_dtim;
1754 unsigned long last_beacon;
1755 unsigned long last_action;
1756 unsigned long last_slept;
1757
1758 /*For P2P PS */
1759 struct rtl_p2p_ps_info p2p_ps_info;
1760 u8 pwr_mode;
1761 u8 smart_ps;
1762};
1763
1764struct rtl_stats {
1765 u8 psaddr[ETH_ALEN];
1766 u32 mac_time[2];
1767 s8 rssi;
1768 u8 signal;
1769 u8 noise;
1770 u8 rate; /* hw desc rate */
1771 u8 received_channel;
1772 u8 control;
1773 u8 mask;
1774 u8 freq;
1775 u16 len;
1776 u64 tsf;
1777 u32 beacon_time;
1778 u8 nic_type;
1779 u16 length;
1780 u8 signalquality; /*in 0-100 index. */
1781 /*
1782 * Real power in dBm for this packet,
1783 * no beautification and aggregation.
1784 * */
1785 s32 recvsignalpower;
1786 s8 rxpower; /*in dBm Translate from PWdB */
1787 u8 signalstrength; /*in 0-100 index. */
1788 u16 hwerror:1;
1789 u16 crc:1;
1790 u16 icv:1;
1791 u16 shortpreamble:1;
1792 u16 antenna:1;
1793 u16 decrypted:1;
1794 u16 wakeup:1;
1795 u32 timestamp_low;
1796 u32 timestamp_high;
1797
1798 u8 rx_drvinfo_size;
1799 u8 rx_bufshift;
1800 bool isampdu;
1801 bool isfirst_ampdu;
1802 bool rx_is40Mhzpacket;
1803 u32 rx_pwdb_all;
1804 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1805 s8 rx_mimo_sig_qual[4];
1806 u8 rx_pwr[4]; /* per-path's pwdb */
1807 u8 rx_snr[4]; /* per-path's SNR */
1808 bool packet_matchbssid;
1809 bool is_cck;
1810 bool is_ht;
1811 bool packet_toself;
1812 bool packet_beacon; /*for rssi */
1813 char cck_adc_pwdb[4]; /*for rx path selection */
1814
1815 u8 packet_report_type;
1816
1817 u32 macid;
1818 u8 wake_match;
1819 u32 bt_rx_rssi_percentage;
1820 u32 macid_valid_entry[2];
1821};
1822
1823
1824struct rt_link_detect {
1825 /* count for roaming */
1826 u32 bcn_rx_inperiod;
1827 u32 roam_times;
1828
1829 u32 num_tx_in4period[4];
1830 u32 num_rx_in4period[4];
1831
1832 u32 num_tx_inperiod;
1833 u32 num_rx_inperiod;
1834
1835 bool busytraffic;
1836 bool tx_busy_traffic;
1837 bool rx_busy_traffic;
1838 bool higher_busytraffic;
1839 bool higher_busyrxtraffic;
1840
1841 u32 tidtx_in4period[MAX_TID_COUNT][4];
1842 u32 tidtx_inperiod[MAX_TID_COUNT];
1843 bool higher_busytxtraffic[MAX_TID_COUNT];
1844};
1845
1846struct rtl_tcb_desc {
1847 u8 packet_bw:1;
1848 u8 multicast:1;
1849 u8 broadcast:1;
1850
1851 u8 rts_stbc:1;
1852 u8 rts_enable:1;
1853 u8 cts_enable:1;
1854 u8 rts_use_shortpreamble:1;
1855 u8 rts_use_shortgi:1;
1856 u8 rts_sc:1;
1857 u8 rts_bw:1;
1858 u8 rts_rate;
1859
1860 u8 use_shortgi:1;
1861 u8 use_shortpreamble:1;
1862 u8 use_driver_rate:1;
1863 u8 disable_ratefallback:1;
1864
1865 u8 ratr_index;
1866 u8 mac_id;
1867 u8 hw_rate;
1868
1869 u8 last_inipkt:1;
1870 u8 cmd_or_init:1;
1871 u8 queue_index;
1872
1873 /* early mode */
1874 u8 empkt_num;
1875 /* The max value by HW */
1876 u32 empkt_len[10];
1877 bool btx_enable_sw_calc_duration;
1878};
1879
1880struct rtl92c_firmware_header;
1881
1882struct rtl_hal_ops {
1883 int (*init_sw_vars) (struct ieee80211_hw *hw);
1884 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1885 void (*read_chip_version)(struct ieee80211_hw *hw);
1886 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1887 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1888 u32 *p_inta, u32 *p_intb);
1889 int (*hw_init) (struct ieee80211_hw *hw);
1890 void (*hw_disable) (struct ieee80211_hw *hw);
1891 void (*hw_suspend) (struct ieee80211_hw *hw);
1892 void (*hw_resume) (struct ieee80211_hw *hw);
1893 void (*enable_interrupt) (struct ieee80211_hw *hw);
1894 void (*disable_interrupt) (struct ieee80211_hw *hw);
1895 int (*set_network_type) (struct ieee80211_hw *hw,
1896 enum nl80211_iftype type);
1897 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1898 bool check_bssid);
1899 void (*set_bw_mode) (struct ieee80211_hw *hw,
1900 enum nl80211_channel_type ch_type);
1901 u8(*switch_channel) (struct ieee80211_hw *hw);
1902 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1903 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1904 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1905 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1906 u32 add_msr, u32 rm_msr);
1907 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1908 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1909 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1910 struct ieee80211_sta *sta, u8 rssi_level);
1911 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
1912 u8 *desc, u8 queue_index,
1913 struct sk_buff *skb, dma_addr_t addr);
1914 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1915 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
1916 u8 queue_index);
1917 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
1918 u8 queue_index);
1919 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1920 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1921 u8 *pbd_desc_tx,
1922 struct ieee80211_tx_info *info,
1923 struct ieee80211_sta *sta,
1924 struct sk_buff *skb, u8 hw_queue,
1925 struct rtl_tcb_desc *ptcb_desc);
1926 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1927 u32 buffer_len, bool bIsPsPoll);
1928 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1929 bool firstseg, bool lastseg,
1930 struct sk_buff *skb);
1931 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1932 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1933 struct rtl_stats *stats,
1934 struct ieee80211_rx_status *rx_status,
1935 u8 *pdesc, struct sk_buff *skb);
1936 void (*set_channel_access) (struct ieee80211_hw *hw);
1937 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1938 void (*dm_watchdog) (struct ieee80211_hw *hw);
1939 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1940 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1941 enum rf_pwrstate rfpwr_state);
1942 void (*led_control) (struct ieee80211_hw *hw,
1943 enum led_ctl_mode ledaction);
1944 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
1945 u8 desc_name, u8 *val);
1946 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1947 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
1948 u8 hw_queue, u16 index);
1949 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1950 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1951 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1952 u8 *macaddr, bool is_group, u8 enc_algo,
1953 bool is_wepkey, bool clear_all);
1954 void (*init_sw_leds) (struct ieee80211_hw *hw);
1955 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1956 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1957 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1958 u32 data);
1959 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1960 u32 regaddr, u32 bitmask);
1961 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1962 u32 regaddr, u32 bitmask, u32 data);
1963 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1964 bool allow_all_da, bool write_into_reg);
1965 void (*linked_set_reg) (struct ieee80211_hw *hw);
1966 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1967 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1968 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1969 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1970 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1971 u8 *powerlevel);
1972 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1973 u8 *ppowerlevel, u8 channel);
1974 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1975 u8 configtype);
1976 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1977 u8 configtype);
1978 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1979 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1980 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1981 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1982 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1983 bool mstate);
1984 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1985 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1986 u32 cmd_len, u8 *p_cmdbuffer);
1987 bool (*get_btc_status) (void);
1988 bool (*is_fw_header) (struct rtl92c_firmware_header *hdr);
1989 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
1990 struct rtl_stats status, struct sk_buff *skb);
1991};
1992
1993struct rtl_intf_ops {
1994 /*com */
1995 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1996 int (*adapter_start) (struct ieee80211_hw *hw);
1997 void (*adapter_stop) (struct ieee80211_hw *hw);
1998 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1999 struct rtl_priv **buddy_priv);
2000
2001 int (*adapter_tx) (struct ieee80211_hw *hw,
2002 struct ieee80211_sta *sta,
2003 struct sk_buff *skb,
2004 struct rtl_tcb_desc *ptcb_desc);
2005 void (*flush)(struct ieee80211_hw *hw, bool drop);
2006 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2007 bool (*waitq_insert) (struct ieee80211_hw *hw,
2008 struct ieee80211_sta *sta,
2009 struct sk_buff *skb);
2010
2011 /*pci */
2012 void (*disable_aspm) (struct ieee80211_hw *hw);
2013 void (*enable_aspm) (struct ieee80211_hw *hw);
2014
2015 /*usb */
2016};
2017
2018struct rtl_mod_params {
2019 /* default: 0 = using hardware encryption */
2020 bool sw_crypto;
2021
2022 /* default: 0 = DBG_EMERG (0)*/
2023 int debug;
2024
2025 /* default: 1 = using no linked power save */
2026 bool inactiveps;
2027
2028 /* default: 1 = using linked sw power save */
2029 bool swctrl_lps;
2030
2031 /* default: 1 = using linked fw power save */
2032 bool fwctrl_lps;
2033};
2034
2035struct rtl_hal_usbint_cfg {
2036 /* data - rx */
2037 u32 in_ep_num;
2038 u32 rx_urb_num;
2039 u32 rx_max_size;
2040
2041 /* op - rx */
2042 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2043 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2044 struct sk_buff_head *);
2045
2046 /* tx */
2047 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2048 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2049 struct sk_buff *);
2050 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2051 struct sk_buff_head *);
2052
2053 /* endpoint mapping */
2054 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2055 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2056};
2057
2058struct rtl_hal_cfg {
2059 u8 bar_id;
2060 bool write_readback;
2061 char *name;
2062 char *fw_name;
2063 char *alt_fw_name;
2064 struct rtl_hal_ops *ops;
2065 struct rtl_mod_params *mod_params;
2066 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2067
2068 /*this map used for some registers or vars
2069 defined int HAL but used in MAIN */
2070 u32 maps[RTL_VAR_MAP_MAX];
2071
2072};
2073
2074struct rtl_locks {
2075 /* mutex */
2076 struct mutex conf_mutex;
2077 struct mutex ps_mutex;
2078
2079 /*spin lock */
2080 spinlock_t ips_lock;
2081 spinlock_t irq_th_lock;
2082 spinlock_t irq_pci_lock;
2083 spinlock_t tx_lock;
2084 spinlock_t h2c_lock;
2085 spinlock_t rf_ps_lock;
2086 spinlock_t rf_lock;
2087 spinlock_t lps_lock;
2088 spinlock_t waitq_lock;
2089 spinlock_t entry_list_lock;
2090 spinlock_t usb_lock;
2091
2092 /*FW clock change */
2093 spinlock_t fw_ps_lock;
2094
2095 /*Dual mac*/
2096 spinlock_t cck_and_rw_pagea_lock;
2097
2098 /*Easy concurrent*/
2099 spinlock_t check_sendpkt_lock;
2100
2101 spinlock_t iqk_lock;
2102};
2103
2104struct rtl_works {
2105 struct ieee80211_hw *hw;
2106
2107 /*timer */
2108 struct timer_list watchdog_timer;
2109 struct timer_list dualmac_easyconcurrent_retrytimer;
2110 struct timer_list fw_clockoff_timer;
2111 struct timer_list fast_antenna_training_timer;
2112 /*task */
2113 struct tasklet_struct irq_tasklet;
2114 struct tasklet_struct irq_prepare_bcn_tasklet;
2115
2116 /*work queue */
2117 struct workqueue_struct *rtl_wq;
2118 struct delayed_work watchdog_wq;
2119 struct delayed_work ips_nic_off_wq;
2120
2121 /* For SW LPS */
2122 struct delayed_work ps_work;
2123 struct delayed_work ps_rfon_wq;
2124 struct delayed_work fwevt_wq;
2125
2126 struct work_struct lps_change_work;
2127 struct work_struct fill_h2c_cmd;
2128};
2129
2130struct rtl_debug {
2131 u32 dbgp_type[DBGP_TYPE_MAX];
2132 int global_debuglevel;
2133 u64 global_debugcomponents;
2134
2135 /* add for proc debug */
2136 struct proc_dir_entry *proc_dir;
2137 char proc_name[20];
2138};
2139
2140#define MIMO_PS_STATIC 0
2141#define MIMO_PS_DYNAMIC 1
2142#define MIMO_PS_NOLIMIT 3
2143
2144struct rtl_dualmac_easy_concurrent_ctl {
2145 enum band_type currentbandtype_backfordmdp;
2146 bool close_bbandrf_for_dmsp;
2147 bool change_to_dmdp;
2148 bool change_to_dmsp;
2149 bool switch_in_process;
2150};
2151
2152struct rtl_dmsp_ctl {
2153 bool activescan_for_slaveofdmsp;
2154 bool scan_for_anothermac_fordmsp;
2155 bool scan_for_itself_fordmsp;
2156 bool writedig_for_anothermacofdmsp;
2157 u32 curdigvalue_for_anothermacofdmsp;
2158 bool changecckpdstate_for_anothermacofdmsp;
2159 u8 curcckpdstate_for_anothermacofdmsp;
2160 bool changetxhighpowerlvl_for_anothermacofdmsp;
2161 u8 curtxhighlvl_for_anothermacofdmsp;
2162 long rssivalmin_for_anothermacofdmsp;
2163};
2164
2165struct ps_t {
2166 u8 pre_ccastate;
2167 u8 cur_ccasate;
2168 u8 pre_rfstate;
2169 u8 cur_rfstate;
2170 u8 initialize;
2171 long rssi_val_min;
2172};
2173
2174struct dig_t {
2175 u32 rssi_lowthresh;
2176 u32 rssi_highthresh;
2177 u32 fa_lowthresh;
2178 u32 fa_highthresh;
2179 long last_min_undec_pwdb_for_dm;
2180 long rssi_highpower_lowthresh;
2181 long rssi_highpower_highthresh;
2182 u32 recover_cnt;
2183 u32 pre_igvalue;
2184 u32 cur_igvalue;
2185 long rssi_val;
2186 u8 dig_enable_flag;
2187 u8 dig_ext_port_stage;
2188 u8 dig_algorithm;
2189 u8 dig_twoport_algorithm;
2190 u8 dig_dbgmode;
2191 u8 dig_slgorithm_switch;
2192 u8 cursta_cstate;
2193 u8 presta_cstate;
2194 u8 curmultista_cstate;
2195 u8 stop_dig;
2196 char back_val;
2197 char back_range_max;
2198 char back_range_min;
2199 u8 rx_gain_max;
2200 u8 rx_gain_min;
2201 u8 min_undec_pwdb_for_dm;
2202 u8 rssi_val_min;
2203 u8 pre_cck_cca_thres;
2204 u8 cur_cck_cca_thres;
2205 u8 pre_cck_pd_state;
2206 u8 cur_cck_pd_state;
2207 u8 pre_cck_fa_state;
2208 u8 cur_cck_fa_state;
2209 u8 pre_ccastate;
2210 u8 cur_ccasate;
2211 u8 large_fa_hit;
2212 u8 dig_dynamic_min;
2213 u8 dig_dynamic_min_1;
2214 u8 forbidden_igi;
2215 u8 dig_state;
2216 u8 dig_highpwrstate;
2217 u8 cur_sta_cstate;
2218 u8 pre_sta_cstate;
2219 u8 cur_ap_cstate;
2220 u8 pre_ap_cstate;
2221 u8 cur_pd_thstate;
2222 u8 pre_pd_thstate;
2223 u8 cur_cs_ratiostate;
2224 u8 pre_cs_ratiostate;
2225 u8 backoff_enable_flag;
2226 char backoffval_range_max;
2227 char backoffval_range_min;
2228 u8 dig_min_0;
2229 u8 dig_min_1;
2230 u8 bt30_cur_igi;
2231 bool media_connect_0;
2232 bool media_connect_1;
2233
2234 u32 antdiv_rssi_max;
2235 u32 rssi_max;
2236};
2237
2238struct rtl_global_var {
2239 /* from this list we can get
2240 * other adapter's rtl_priv */
2241 struct list_head glb_priv_list;
2242 spinlock_t glb_list_lock;
2243};
2244
2245struct rtl_btc_info {
2246 u8 bt_type;
2247 u8 btcoexist;
2248 u8 ant_num;
2249};
2250
2251struct bt_coexist_info {
2252 struct rtl_btc_ops *btc_ops;
2253 struct rtl_btc_info btc_info;
2254 /* EEPROM BT info. */
2255 u8 eeprom_bt_coexist;
2256 u8 eeprom_bt_type;
2257 u8 eeprom_bt_ant_num;
2258 u8 eeprom_bt_ant_isol;
2259 u8 eeprom_bt_radio_shared;
2260
2261 u8 bt_coexistence;
2262 u8 bt_ant_num;
2263 u8 bt_coexist_type;
2264 u8 bt_state;
2265 u8 bt_cur_state; /* 0:on, 1:off */
2266 u8 bt_ant_isolation; /* 0:good, 1:bad */
2267 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2268 u8 bt_service;
2269 u8 bt_radio_shared_type;
2270 u8 bt_rfreg_origin_1e;
2271 u8 bt_rfreg_origin_1f;
2272 u8 bt_rssi_state;
2273 u32 ratio_tx;
2274 u32 ratio_pri;
2275 u32 bt_edca_ul;
2276 u32 bt_edca_dl;
2277
2278 bool init_set;
2279 bool bt_busy_traffic;
2280 bool bt_traffic_mode_set;
2281 bool bt_non_traffic_mode_set;
2282
2283 bool fw_coexist_all_off;
2284 bool sw_coexist_all_off;
2285 bool hw_coexist_all_off;
2286 u32 cstate;
2287 u32 previous_state;
2288 u32 cstate_h;
2289 u32 previous_state_h;
2290
2291 u8 bt_pre_rssi_state;
2292 u8 bt_pre_rssi_state1;
2293
2294 u8 reg_bt_iso;
2295 u8 reg_bt_sco;
2296 bool balance_on;
2297 u8 bt_active_zero_cnt;
2298 bool cur_bt_disabled;
2299 bool pre_bt_disabled;
2300
2301 u8 bt_profile_case;
2302 u8 bt_profile_action;
2303 bool bt_busy;
2304 bool hold_for_bt_operation;
2305 u8 lps_counter;
2306};
2307
2308struct rtl_btc_ops {
2309 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2310 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2311 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2312 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2313 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2314 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2315 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2316 enum _RT_MEDIA_STATUS mstatus);
2317 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2318 void (*btc_halt_notify) (void);
2319 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2320 u8 *tmp_buf, u8 length);
2321 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2322 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2323 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2324};
2325
2326struct proxim {
2327 bool proxim_on;
2328
2329 void *proximity_priv;
2330 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2331 struct sk_buff *skb);
2332 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2333};
2334
2335struct rtl_priv {
2336 struct ieee80211_hw *hw;
2337 struct completion firmware_loading_complete;
2338 struct list_head list;
2339 struct rtl_priv *buddy_priv;
2340 struct rtl_global_var *glb_var;
2341 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2342 struct rtl_dmsp_ctl dmsp_ctl;
2343 struct rtl_locks locks;
2344 struct rtl_works works;
2345 struct rtl_mac mac80211;
2346 struct rtl_hal rtlhal;
2347 struct rtl_regulatory regd;
2348 struct rtl_rfkill rfkill;
2349 struct rtl_io io;
2350 struct rtl_phy phy;
2351 struct rtl_dm dm;
2352 struct rtl_security sec;
2353 struct rtl_efuse efuse;
2354
2355 struct rtl_ps_ctl psc;
2356 struct rate_adaptive ra;
2357 struct dynamic_primary_cca primarycca;
2358 struct wireless_stats stats;
2359 struct rt_link_detect link_info;
2360 struct false_alarm_statistics falsealm_cnt;
2361
2362 struct rtl_rate_priv *rate_priv;
2363
2364 /* sta entry list for ap adhoc or mesh */
2365 struct list_head entry_list;
2366
2367 struct rtl_debug dbg;
2368 int max_fw_size;
2369
2370 /*
2371 *hal_cfg : for diff cards
2372 *intf_ops : for diff interrface usb/pcie
2373 */
2374 struct rtl_hal_cfg *cfg;
2375 struct rtl_intf_ops *intf_ops;
2376
2377 /*this var will be set by set_bit,
2378 and was used to indicate status of
2379 interface or hardware */
2380 unsigned long status;
2381
2382 /* tables for dm */
2383 struct dig_t dm_digtable;
2384 struct ps_t dm_pstable;
2385
2386 u32 reg_874;
2387 u32 reg_c70;
2388 u32 reg_85c;
2389 u32 reg_a74;
2390 bool reg_init; /* true if regs saved */
2391 bool bt_operation_on;
2392 __le32 *usb_data;
2393 int usb_data_index;
2394 bool initialized;
2395 bool enter_ps; /* true when entering PS */
2396 u8 rate_mask[5];
2397
2398 /* intel Proximity, should be alloc mem
2399 * in intel Proximity module and can only
2400 * be used in intel Proximity mode
2401 */
2402 struct proxim proximity;
2403
2404 /*for bt coexist use*/
2405 struct bt_coexist_info btcoexist;
2406
2407 /* separate 92ee from other ICs,
2408 * 92ee use new trx flow.
2409 */
2410 bool use_new_trx_flow;
2411
2412 /*This must be the last item so
2413 that it points to the data allocated
2414 beyond this structure like:
2415 rtl_pci_priv or rtl_usb_priv */
2416 u8 priv[0] __aligned(sizeof(void *));
2417};
2418
2419#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2420#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2421#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2422#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2423#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2424
2425
2426/***************************************
2427 Bluetooth Co-existence Related
2428****************************************/
2429
2430enum bt_ant_num {
2431 ANT_X2 = 0,
2432 ANT_X1 = 1,
2433};
2434
2435enum bt_co_type {
2436 BT_2WIRE = 0,
2437 BT_ISSC_3WIRE = 1,
2438 BT_ACCEL = 2,
2439 BT_CSR_BC4 = 3,
2440 BT_CSR_BC8 = 4,
2441 BT_RTL8756 = 5,
2442 BT_RTL8723A = 6,
2443 BT_RTL8821A = 7,
2444 BT_RTL8723B = 8,
2445 BT_RTL8192E = 9,
2446 BT_RTL8812A = 11,
2447};
2448
2449enum bt_total_ant_num {
2450 ANT_TOTAL_X2 = 0,
2451 ANT_TOTAL_X1 = 1
2452};
2453
2454enum bt_cur_state {
2455 BT_OFF = 0,
2456 BT_ON = 1,
2457};
2458
2459enum bt_service_type {
2460 BT_SCO = 0,
2461 BT_A2DP = 1,
2462 BT_HID = 2,
2463 BT_HID_IDLE = 3,
2464 BT_SCAN = 4,
2465 BT_IDLE = 5,
2466 BT_OTHER_ACTION = 6,
2467 BT_BUSY = 7,
2468 BT_OTHERBUSY = 8,
2469 BT_PAN = 9,
2470};
2471
2472enum bt_radio_shared {
2473 BT_RADIO_SHARED = 0,
2474 BT_RADIO_INDIVIDUAL = 1,
2475};
2476
2477
2478/****************************************
2479 mem access macro define start
2480 Call endian free function when
2481 1. Read/write packet content.
2482 2. Before write integer to IO.
2483 3. After read integer from IO.
2484****************************************/
2485/* Convert little data endian to host ordering */
2486#define EF1BYTE(_val) \
2487 ((u8)(_val))
2488#define EF2BYTE(_val) \
2489 (le16_to_cpu(_val))
2490#define EF4BYTE(_val) \
2491 (le32_to_cpu(_val))
2492
2493/* Read data from memory */
2494#define READEF1BYTE(_ptr) \
2495 EF1BYTE(*((u8 *)(_ptr)))
2496/* Read le16 data from memory and convert to host ordering */
2497#define READEF2BYTE(_ptr) \
2498 EF2BYTE(*(_ptr))
2499#define READEF4BYTE(_ptr) \
2500 EF4BYTE(*(_ptr))
2501
2502/* Write data to memory */
2503#define WRITEEF1BYTE(_ptr, _val) \
2504 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2505/* Write le16 data to memory in host ordering */
2506#define WRITEEF2BYTE(_ptr, _val) \
2507 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2508#define WRITEEF4BYTE(_ptr, _val) \
2509 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2510
2511/* Create a bit mask
2512 * Examples:
2513 * BIT_LEN_MASK_32(0) => 0x00000000
2514 * BIT_LEN_MASK_32(1) => 0x00000001
2515 * BIT_LEN_MASK_32(2) => 0x00000003
2516 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2517 */
2518#define BIT_LEN_MASK_32(__bitlen) \
2519 (0xFFFFFFFF >> (32 - (__bitlen)))
2520#define BIT_LEN_MASK_16(__bitlen) \
2521 (0xFFFF >> (16 - (__bitlen)))
2522#define BIT_LEN_MASK_8(__bitlen) \
2523 (0xFF >> (8 - (__bitlen)))
2524
2525/* Create an offset bit mask
2526 * Examples:
2527 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2528 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2529 */
2530#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2531 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2532#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2533 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2534#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2535 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2536
2537/*Description:
2538 * Return 4-byte value in host byte ordering from
2539 * 4-byte pointer in little-endian system.
2540 */
2541#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2542 (EF4BYTE(*((__le32 *)(__pstart))))
2543#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2544 (EF2BYTE(*((__le16 *)(__pstart))))
2545#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2546 (EF1BYTE(*((u8 *)(__pstart))))
2547
2548/*Description:
2549Translate subfield (continuous bits in little-endian) of 4-byte
2550value to host byte ordering.*/
2551#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2552 ( \
2553 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2554 BIT_LEN_MASK_32(__bitlen) \
2555 )
2556#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2557 ( \
2558 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2559 BIT_LEN_MASK_16(__bitlen) \
2560 )
2561#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2562 ( \
2563 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2564 BIT_LEN_MASK_8(__bitlen) \
2565 )
2566
2567/* Description:
2568 * Mask subfield (continuous bits in little-endian) of 4-byte value
2569 * and return the result in 4-byte value in host byte ordering.
2570 */
2571#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2572 ( \
2573 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2574 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2575 )
2576#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2577 ( \
2578 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2579 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2580 )
2581#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2582 ( \
2583 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2584 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2585 )
2586
2587/* Description:
2588 * Set subfield of little-endian 4-byte value to specified value.
2589 */
2590#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2591 *((u32 *)(__pstart)) = \
2592 ( \
2593 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2594 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2595 );
2596#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2597 *((u16 *)(__pstart)) = \
2598 ( \
2599 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2600 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2601 );
2602#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2603 *((u8 *)(__pstart)) = EF1BYTE \
2604 ( \
2605 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2606 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2607 );
2608
2609#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2610 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2611
2612/****************************************
2613 mem access macro define end
2614****************************************/
2615
2616#define byte(x, n) ((x >> (8 * n)) & 0xff)
2617
2618#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2619#define RTL_WATCH_DOG_TIME 2000
2620#define MSECS(t) msecs_to_jiffies(t)
2621#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2622#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2623#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2624#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2625#define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2626
2627#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2628#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2629#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2630/*NIC halt, re-initialize hw parameters*/
2631#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2632#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2633#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2634/*Always enable ASPM and Clock Req in initialization.*/
2635#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2636/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2637#define RT_PS_LEVEL_ASPM BIT(7)
2638/*When LPS is on, disable 2R if no packet is received or transmittd.*/
2639#define RT_RF_LPS_DISALBE_2R BIT(30)
2640#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2641#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2642 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2643#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2644 (ppsc->cur_ps_level &= (~(_ps_flg)))
2645#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2646 (ppsc->cur_ps_level |= _ps_flg)
2647
2648#define container_of_dwork_rtl(x, y, z) \
2649 container_of(container_of(x, struct delayed_work, work), y, z)
2650
2651#define FILL_OCTET_STRING(_os, _octet, _len) \
2652 (_os).octet = (u8 *)(_octet); \
2653 (_os).length = (_len);
2654
2655#define CP_MACADDR(des, src) \
2656 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2657 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2658 (des)[4] = (src)[4], (des)[5] = (src)[5])
2659
2660static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2661{
2662 return rtlpriv->io.read8_sync(rtlpriv, addr);
2663}
2664
2665static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2666{
2667 return rtlpriv->io.read16_sync(rtlpriv, addr);
2668}
2669
2670static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2671{
2672 return rtlpriv->io.read32_sync(rtlpriv, addr);
2673}
2674
2675static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2676{
2677 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2678
2679 if (rtlpriv->cfg->write_readback)
2680 rtlpriv->io.read8_sync(rtlpriv, addr);
2681}
2682
2683static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2684{
2685 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2686
2687 if (rtlpriv->cfg->write_readback)
2688 rtlpriv->io.read16_sync(rtlpriv, addr);
2689}
2690
2691static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2692 u32 addr, u32 val32)
2693{
2694 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2695
2696 if (rtlpriv->cfg->write_readback)
2697 rtlpriv->io.read32_sync(rtlpriv, addr);
2698}
2699
2700static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2701 u32 regaddr, u32 bitmask)
2702{
2703 struct rtl_priv *rtlpriv = hw->priv;
2704
2705 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2706}
2707
2708static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2709 u32 bitmask, u32 data)
2710{
2711 struct rtl_priv *rtlpriv = hw->priv;
2712
2713 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2714}
2715
2716static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2717 enum radio_path rfpath, u32 regaddr,
2718 u32 bitmask)
2719{
2720 struct rtl_priv *rtlpriv = hw->priv;
2721
2722 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2723}
2724
2725static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2726 enum radio_path rfpath, u32 regaddr,
2727 u32 bitmask, u32 data)
2728{
2729 struct rtl_priv *rtlpriv = hw->priv;
2730
2731 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2732}
2733
2734static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2735{
2736 return (_HAL_STATE_STOP == rtlhal->state);
2737}
2738
2739static inline void set_hal_start(struct rtl_hal *rtlhal)
2740{
2741 rtlhal->state = _HAL_STATE_START;
2742}
2743
2744static inline void set_hal_stop(struct rtl_hal *rtlhal)
2745{
2746 rtlhal->state = _HAL_STATE_STOP;
2747}
2748
2749static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2750{
2751 return rtlphy->rf_type;
2752}
2753
2754static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2755{
2756 return (struct ieee80211_hdr *)(skb->data);
2757}
2758
2759static inline __le16 rtl_get_fc(struct sk_buff *skb)
2760{
2761 return rtl_get_hdr(skb)->frame_control;
2762}
2763
2764static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2765{
2766 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2767}
2768
2769static inline u16 rtl_get_tid(struct sk_buff *skb)
2770{
2771 return rtl_get_tid_h(rtl_get_hdr(skb));
2772}
2773
2774static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2775 struct ieee80211_vif *vif,
2776 const u8 *bssid)
2777{
2778 return ieee80211_find_sta(vif, bssid);
2779}
2780
2781static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2782 u8 *mac_addr)
2783{
2784 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2785 return ieee80211_find_sta(mac->vif, mac_addr);
2786}
2787
2788#endif