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1/*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/circ_buf.h>
18#include <linux/slab.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_data/macb.h>
27#include <linux/platform_device.h>
28#include <linux/phy.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_mdio.h>
32#include <linux/of_net.h>
33#include <linux/pinctrl/consumer.h>
34
35#include "macb.h"
36
37#define MACB_RX_BUFFER_SIZE 128
38#define RX_BUFFER_MULTIPLE 64 /* bytes */
39#define RX_RING_SIZE 512 /* must be power of 2 */
40#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41
42#define TX_RING_SIZE 128 /* must be power of 2 */
43#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44
45/* level of occupied TX descriptors under which we wake up TX process */
46#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47
48#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
50#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
55/*
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 */
59#define MACB_HALT_TIMEOUT 1230
60
61/* Ring buffer accessors */
62static unsigned int macb_tx_ring_wrap(unsigned int index)
63{
64 return index & (TX_RING_SIZE - 1);
65}
66
67static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68{
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
70}
71
72static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73{
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
75}
76
77static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
78{
79 dma_addr_t offset;
80
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82
83 return bp->tx_ring_dma + offset;
84}
85
86static unsigned int macb_rx_ring_wrap(unsigned int index)
87{
88 return index & (RX_RING_SIZE - 1);
89}
90
91static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92{
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
94}
95
96static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97{
98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
99}
100
101void macb_set_hwaddr(struct macb *bp)
102{
103 u32 bottom;
104 u16 top;
105
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
107 macb_or_gem_writel(bp, SA1B, bottom);
108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
109 macb_or_gem_writel(bp, SA1T, top);
110
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
118}
119EXPORT_SYMBOL_GPL(macb_set_hwaddr);
120
121void macb_get_hwaddr(struct macb *bp)
122{
123 struct macb_platform_data *pdata;
124 u32 bottom;
125 u16 top;
126 u8 addr[6];
127 int i;
128
129 pdata = dev_get_platdata(&bp->pdev->dev);
130
131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
135
136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
143 } else {
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
150 }
151
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
154 return;
155 }
156 }
157
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
160}
161EXPORT_SYMBOL_GPL(macb_get_hwaddr);
162
163static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
164{
165 struct macb *bp = bus->priv;
166 int value;
167
168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
172 | MACB_BF(CODE, MACB_MAN_CODE)));
173
174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
176 cpu_relax();
177
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
179
180 return value;
181}
182
183static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
184 u16 value)
185{
186 struct macb *bp = bus->priv;
187
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
192 | MACB_BF(CODE, MACB_MAN_CODE)
193 | MACB_BF(DATA, value)));
194
195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
197 cpu_relax();
198
199 return 0;
200}
201
202/**
203 * macb_set_tx_clk() - Set a clock to a new frequency
204 * @clk Pointer to the clock to change
205 * @rate New frequency in Hz
206 * @dev Pointer to the struct net_device
207 */
208static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
209{
210 long ferr, rate, rate_rounded;
211
212 switch (speed) {
213 case SPEED_10:
214 rate = 2500000;
215 break;
216 case SPEED_100:
217 rate = 25000000;
218 break;
219 case SPEED_1000:
220 rate = 125000000;
221 break;
222 default:
223 return;
224 }
225
226 rate_rounded = clk_round_rate(clk, rate);
227 if (rate_rounded < 0)
228 return;
229
230 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
231 * is not satisfied.
232 */
233 ferr = abs(rate_rounded - rate);
234 ferr = DIV_ROUND_UP(ferr, rate / 100000);
235 if (ferr > 5)
236 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
237 rate);
238
239 if (clk_set_rate(clk, rate_rounded))
240 netdev_err(dev, "adjusting tx_clk failed.\n");
241}
242
243static void macb_handle_link_change(struct net_device *dev)
244{
245 struct macb *bp = netdev_priv(dev);
246 struct phy_device *phydev = bp->phy_dev;
247 unsigned long flags;
248
249 int status_change = 0;
250
251 spin_lock_irqsave(&bp->lock, flags);
252
253 if (phydev->link) {
254 if ((bp->speed != phydev->speed) ||
255 (bp->duplex != phydev->duplex)) {
256 u32 reg;
257
258 reg = macb_readl(bp, NCFGR);
259 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
260 if (macb_is_gem(bp))
261 reg &= ~GEM_BIT(GBE);
262
263 if (phydev->duplex)
264 reg |= MACB_BIT(FD);
265 if (phydev->speed == SPEED_100)
266 reg |= MACB_BIT(SPD);
267 if (phydev->speed == SPEED_1000)
268 reg |= GEM_BIT(GBE);
269
270 macb_or_gem_writel(bp, NCFGR, reg);
271
272 bp->speed = phydev->speed;
273 bp->duplex = phydev->duplex;
274 status_change = 1;
275 }
276 }
277
278 if (phydev->link != bp->link) {
279 if (!phydev->link) {
280 bp->speed = 0;
281 bp->duplex = -1;
282 }
283 bp->link = phydev->link;
284
285 status_change = 1;
286 }
287
288 spin_unlock_irqrestore(&bp->lock, flags);
289
290 if (!IS_ERR(bp->tx_clk))
291 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
292
293 if (status_change) {
294 if (phydev->link) {
295 netif_carrier_on(dev);
296 netdev_info(dev, "link up (%d/%s)\n",
297 phydev->speed,
298 phydev->duplex == DUPLEX_FULL ?
299 "Full" : "Half");
300 } else {
301 netif_carrier_off(dev);
302 netdev_info(dev, "link down\n");
303 }
304 }
305}
306
307/* based on au1000_eth. c*/
308static int macb_mii_probe(struct net_device *dev)
309{
310 struct macb *bp = netdev_priv(dev);
311 struct macb_platform_data *pdata;
312 struct phy_device *phydev;
313 int phy_irq;
314 int ret;
315
316 phydev = phy_find_first(bp->mii_bus);
317 if (!phydev) {
318 netdev_err(dev, "no PHY found\n");
319 return -ENXIO;
320 }
321
322 pdata = dev_get_platdata(&bp->pdev->dev);
323 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
324 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
325 if (!ret) {
326 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
327 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
328 }
329 }
330
331 /* attach the mac to the phy */
332 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
333 bp->phy_interface);
334 if (ret) {
335 netdev_err(dev, "Could not attach to PHY\n");
336 return ret;
337 }
338
339 /* mask with MAC supported features */
340 if (macb_is_gem(bp))
341 phydev->supported &= PHY_GBIT_FEATURES;
342 else
343 phydev->supported &= PHY_BASIC_FEATURES;
344
345 phydev->advertising = phydev->supported;
346
347 bp->link = 0;
348 bp->speed = 0;
349 bp->duplex = -1;
350 bp->phy_dev = phydev;
351
352 return 0;
353}
354
355int macb_mii_init(struct macb *bp)
356{
357 struct macb_platform_data *pdata;
358 struct device_node *np;
359 int err = -ENXIO, i;
360
361 /* Enable management port */
362 macb_writel(bp, NCR, MACB_BIT(MPE));
363
364 bp->mii_bus = mdiobus_alloc();
365 if (bp->mii_bus == NULL) {
366 err = -ENOMEM;
367 goto err_out;
368 }
369
370 bp->mii_bus->name = "MACB_mii_bus";
371 bp->mii_bus->read = &macb_mdio_read;
372 bp->mii_bus->write = &macb_mdio_write;
373 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
374 bp->pdev->name, bp->pdev->id);
375 bp->mii_bus->priv = bp;
376 bp->mii_bus->parent = &bp->dev->dev;
377 pdata = dev_get_platdata(&bp->pdev->dev);
378
379 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
380 if (!bp->mii_bus->irq) {
381 err = -ENOMEM;
382 goto err_out_free_mdiobus;
383 }
384
385 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
386
387 np = bp->pdev->dev.of_node;
388 if (np) {
389 /* try dt phy registration */
390 err = of_mdiobus_register(bp->mii_bus, np);
391
392 /* fallback to standard phy registration if no phy were
393 found during dt phy registration */
394 if (!err && !phy_find_first(bp->mii_bus)) {
395 for (i = 0; i < PHY_MAX_ADDR; i++) {
396 struct phy_device *phydev;
397
398 phydev = mdiobus_scan(bp->mii_bus, i);
399 if (IS_ERR(phydev)) {
400 err = PTR_ERR(phydev);
401 break;
402 }
403 }
404
405 if (err)
406 goto err_out_unregister_bus;
407 }
408 } else {
409 for (i = 0; i < PHY_MAX_ADDR; i++)
410 bp->mii_bus->irq[i] = PHY_POLL;
411
412 if (pdata)
413 bp->mii_bus->phy_mask = pdata->phy_mask;
414
415 err = mdiobus_register(bp->mii_bus);
416 }
417
418 if (err)
419 goto err_out_free_mdio_irq;
420
421 err = macb_mii_probe(bp->dev);
422 if (err)
423 goto err_out_unregister_bus;
424
425 return 0;
426
427err_out_unregister_bus:
428 mdiobus_unregister(bp->mii_bus);
429err_out_free_mdio_irq:
430 kfree(bp->mii_bus->irq);
431err_out_free_mdiobus:
432 mdiobus_free(bp->mii_bus);
433err_out:
434 return err;
435}
436EXPORT_SYMBOL_GPL(macb_mii_init);
437
438static void macb_update_stats(struct macb *bp)
439{
440 u32 __iomem *reg = bp->regs + MACB_PFR;
441 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
442 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
443
444 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
445
446 for(; p < end; p++, reg++)
447 *p += __raw_readl(reg);
448}
449
450static int macb_halt_tx(struct macb *bp)
451{
452 unsigned long halt_time, timeout;
453 u32 status;
454
455 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
456
457 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
458 do {
459 halt_time = jiffies;
460 status = macb_readl(bp, TSR);
461 if (!(status & MACB_BIT(TGO)))
462 return 0;
463
464 usleep_range(10, 250);
465 } while (time_before(halt_time, timeout));
466
467 return -ETIMEDOUT;
468}
469
470static void macb_tx_error_task(struct work_struct *work)
471{
472 struct macb *bp = container_of(work, struct macb, tx_error_task);
473 struct macb_tx_skb *tx_skb;
474 struct sk_buff *skb;
475 unsigned int tail;
476
477 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
478 bp->tx_tail, bp->tx_head);
479
480 /* Make sure nobody is trying to queue up new packets */
481 netif_stop_queue(bp->dev);
482
483 /*
484 * Stop transmission now
485 * (in case we have just queued new packets)
486 */
487 if (macb_halt_tx(bp))
488 /* Just complain for now, reinitializing TX path can be good */
489 netdev_err(bp->dev, "BUG: halt tx timed out\n");
490
491 /* No need for the lock here as nobody will interrupt us anymore */
492
493 /*
494 * Treat frames in TX queue including the ones that caused the error.
495 * Free transmit buffers in upper layer.
496 */
497 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
498 struct macb_dma_desc *desc;
499 u32 ctrl;
500
501 desc = macb_tx_desc(bp, tail);
502 ctrl = desc->ctrl;
503 tx_skb = macb_tx_skb(bp, tail);
504 skb = tx_skb->skb;
505
506 if (ctrl & MACB_BIT(TX_USED)) {
507 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
508 macb_tx_ring_wrap(tail), skb->data);
509 bp->stats.tx_packets++;
510 bp->stats.tx_bytes += skb->len;
511 } else {
512 /*
513 * "Buffers exhausted mid-frame" errors may only happen
514 * if the driver is buggy, so complain loudly about those.
515 * Statistics are updated by hardware.
516 */
517 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
518 netdev_err(bp->dev,
519 "BUG: TX buffers exhausted mid-frame\n");
520
521 desc->ctrl = ctrl | MACB_BIT(TX_USED);
522 }
523
524 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
525 DMA_TO_DEVICE);
526 tx_skb->skb = NULL;
527 dev_kfree_skb(skb);
528 }
529
530 /* Make descriptor updates visible to hardware */
531 wmb();
532
533 /* Reinitialize the TX desc queue */
534 macb_writel(bp, TBQP, bp->tx_ring_dma);
535 /* Make TX ring reflect state of hardware */
536 bp->tx_head = bp->tx_tail = 0;
537
538 /* Now we are ready to start transmission again */
539 netif_wake_queue(bp->dev);
540
541 /* Housework before enabling TX IRQ */
542 macb_writel(bp, TSR, macb_readl(bp, TSR));
543 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
544}
545
546static void macb_tx_interrupt(struct macb *bp)
547{
548 unsigned int tail;
549 unsigned int head;
550 u32 status;
551
552 status = macb_readl(bp, TSR);
553 macb_writel(bp, TSR, status);
554
555 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
556 macb_writel(bp, ISR, MACB_BIT(TCOMP));
557
558 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
559 (unsigned long)status);
560
561 head = bp->tx_head;
562 for (tail = bp->tx_tail; tail != head; tail++) {
563 struct macb_tx_skb *tx_skb;
564 struct sk_buff *skb;
565 struct macb_dma_desc *desc;
566 u32 ctrl;
567
568 desc = macb_tx_desc(bp, tail);
569
570 /* Make hw descriptor updates visible to CPU */
571 rmb();
572
573 ctrl = desc->ctrl;
574
575 if (!(ctrl & MACB_BIT(TX_USED)))
576 break;
577
578 tx_skb = macb_tx_skb(bp, tail);
579 skb = tx_skb->skb;
580
581 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
582 macb_tx_ring_wrap(tail), skb->data);
583 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
584 DMA_TO_DEVICE);
585 bp->stats.tx_packets++;
586 bp->stats.tx_bytes += skb->len;
587 tx_skb->skb = NULL;
588 dev_kfree_skb_irq(skb);
589 }
590
591 bp->tx_tail = tail;
592 if (netif_queue_stopped(bp->dev)
593 && CIRC_CNT(bp->tx_head, bp->tx_tail,
594 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
595 netif_wake_queue(bp->dev);
596}
597
598static void gem_rx_refill(struct macb *bp)
599{
600 unsigned int entry;
601 struct sk_buff *skb;
602 dma_addr_t paddr;
603
604 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
605 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
606
607 /* Make hw descriptor updates visible to CPU */
608 rmb();
609
610 bp->rx_prepared_head++;
611
612 if (bp->rx_skbuff[entry] == NULL) {
613 /* allocate sk_buff for this free entry in ring */
614 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
615 if (unlikely(skb == NULL)) {
616 netdev_err(bp->dev,
617 "Unable to allocate sk_buff\n");
618 break;
619 }
620
621 /* now fill corresponding descriptor entry */
622 paddr = dma_map_single(&bp->pdev->dev, skb->data,
623 bp->rx_buffer_size, DMA_FROM_DEVICE);
624 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
625 dev_kfree_skb(skb);
626 break;
627 }
628
629 bp->rx_skbuff[entry] = skb;
630
631 if (entry == RX_RING_SIZE - 1)
632 paddr |= MACB_BIT(RX_WRAP);
633 bp->rx_ring[entry].addr = paddr;
634 bp->rx_ring[entry].ctrl = 0;
635
636 /* properly align Ethernet header */
637 skb_reserve(skb, NET_IP_ALIGN);
638 }
639 }
640
641 /* Make descriptor updates visible to hardware */
642 wmb();
643
644 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
645 bp->rx_prepared_head, bp->rx_tail);
646}
647
648/* Mark DMA descriptors from begin up to and not including end as unused */
649static void discard_partial_frame(struct macb *bp, unsigned int begin,
650 unsigned int end)
651{
652 unsigned int frag;
653
654 for (frag = begin; frag != end; frag++) {
655 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
656 desc->addr &= ~MACB_BIT(RX_USED);
657 }
658
659 /* Make descriptor updates visible to hardware */
660 wmb();
661
662 /*
663 * When this happens, the hardware stats registers for
664 * whatever caused this is updated, so we don't have to record
665 * anything.
666 */
667}
668
669static int gem_rx(struct macb *bp, int budget)
670{
671 unsigned int len;
672 unsigned int entry;
673 struct sk_buff *skb;
674 struct macb_dma_desc *desc;
675 int count = 0;
676
677 while (count < budget) {
678 u32 addr, ctrl;
679
680 entry = macb_rx_ring_wrap(bp->rx_tail);
681 desc = &bp->rx_ring[entry];
682
683 /* Make hw descriptor updates visible to CPU */
684 rmb();
685
686 addr = desc->addr;
687 ctrl = desc->ctrl;
688
689 if (!(addr & MACB_BIT(RX_USED)))
690 break;
691
692 bp->rx_tail++;
693 count++;
694
695 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
696 netdev_err(bp->dev,
697 "not whole frame pointed by descriptor\n");
698 bp->stats.rx_dropped++;
699 break;
700 }
701 skb = bp->rx_skbuff[entry];
702 if (unlikely(!skb)) {
703 netdev_err(bp->dev,
704 "inconsistent Rx descriptor chain\n");
705 bp->stats.rx_dropped++;
706 break;
707 }
708 /* now everything is ready for receiving packet */
709 bp->rx_skbuff[entry] = NULL;
710 len = MACB_BFEXT(RX_FRMLEN, ctrl);
711
712 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
713
714 skb_put(skb, len);
715 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
716 dma_unmap_single(&bp->pdev->dev, addr,
717 bp->rx_buffer_size, DMA_FROM_DEVICE);
718
719 skb->protocol = eth_type_trans(skb, bp->dev);
720 skb_checksum_none_assert(skb);
721
722 bp->stats.rx_packets++;
723 bp->stats.rx_bytes += skb->len;
724
725#if defined(DEBUG) && defined(VERBOSE_DEBUG)
726 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
727 skb->len, skb->csum);
728 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
729 skb->mac_header, 16, true);
730 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
731 skb->data, 32, true);
732#endif
733
734 netif_receive_skb(skb);
735 }
736
737 gem_rx_refill(bp);
738
739 return count;
740}
741
742static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
743 unsigned int last_frag)
744{
745 unsigned int len;
746 unsigned int frag;
747 unsigned int offset;
748 struct sk_buff *skb;
749 struct macb_dma_desc *desc;
750
751 desc = macb_rx_desc(bp, last_frag);
752 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
753
754 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
755 macb_rx_ring_wrap(first_frag),
756 macb_rx_ring_wrap(last_frag), len);
757
758 /*
759 * The ethernet header starts NET_IP_ALIGN bytes into the
760 * first buffer. Since the header is 14 bytes, this makes the
761 * payload word-aligned.
762 *
763 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
764 * the two padding bytes into the skb so that we avoid hitting
765 * the slowpath in memcpy(), and pull them off afterwards.
766 */
767 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
768 if (!skb) {
769 bp->stats.rx_dropped++;
770 for (frag = first_frag; ; frag++) {
771 desc = macb_rx_desc(bp, frag);
772 desc->addr &= ~MACB_BIT(RX_USED);
773 if (frag == last_frag)
774 break;
775 }
776
777 /* Make descriptor updates visible to hardware */
778 wmb();
779
780 return 1;
781 }
782
783 offset = 0;
784 len += NET_IP_ALIGN;
785 skb_checksum_none_assert(skb);
786 skb_put(skb, len);
787
788 for (frag = first_frag; ; frag++) {
789 unsigned int frag_len = bp->rx_buffer_size;
790
791 if (offset + frag_len > len) {
792 BUG_ON(frag != last_frag);
793 frag_len = len - offset;
794 }
795 skb_copy_to_linear_data_offset(skb, offset,
796 macb_rx_buffer(bp, frag), frag_len);
797 offset += bp->rx_buffer_size;
798 desc = macb_rx_desc(bp, frag);
799 desc->addr &= ~MACB_BIT(RX_USED);
800
801 if (frag == last_frag)
802 break;
803 }
804
805 /* Make descriptor updates visible to hardware */
806 wmb();
807
808 __skb_pull(skb, NET_IP_ALIGN);
809 skb->protocol = eth_type_trans(skb, bp->dev);
810
811 bp->stats.rx_packets++;
812 bp->stats.rx_bytes += skb->len;
813 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
814 skb->len, skb->csum);
815 netif_receive_skb(skb);
816
817 return 0;
818}
819
820static int macb_rx(struct macb *bp, int budget)
821{
822 int received = 0;
823 unsigned int tail;
824 int first_frag = -1;
825
826 for (tail = bp->rx_tail; budget > 0; tail++) {
827 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
828 u32 addr, ctrl;
829
830 /* Make hw descriptor updates visible to CPU */
831 rmb();
832
833 addr = desc->addr;
834 ctrl = desc->ctrl;
835
836 if (!(addr & MACB_BIT(RX_USED)))
837 break;
838
839 if (ctrl & MACB_BIT(RX_SOF)) {
840 if (first_frag != -1)
841 discard_partial_frame(bp, first_frag, tail);
842 first_frag = tail;
843 }
844
845 if (ctrl & MACB_BIT(RX_EOF)) {
846 int dropped;
847 BUG_ON(first_frag == -1);
848
849 dropped = macb_rx_frame(bp, first_frag, tail);
850 first_frag = -1;
851 if (!dropped) {
852 received++;
853 budget--;
854 }
855 }
856 }
857
858 if (first_frag != -1)
859 bp->rx_tail = first_frag;
860 else
861 bp->rx_tail = tail;
862
863 return received;
864}
865
866static int macb_poll(struct napi_struct *napi, int budget)
867{
868 struct macb *bp = container_of(napi, struct macb, napi);
869 int work_done;
870 u32 status;
871
872 status = macb_readl(bp, RSR);
873 macb_writel(bp, RSR, status);
874
875 work_done = 0;
876
877 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
878 (unsigned long)status, budget);
879
880 work_done = bp->macbgem_ops.mog_rx(bp, budget);
881 if (work_done < budget) {
882 napi_complete(napi);
883
884 /* Packets received while interrupts were disabled */
885 status = macb_readl(bp, RSR);
886 if (status) {
887 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
888 macb_writel(bp, ISR, MACB_BIT(RCOMP));
889 napi_reschedule(napi);
890 } else {
891 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
892 }
893 }
894
895 /* TODO: Handle errors */
896
897 return work_done;
898}
899
900static irqreturn_t macb_interrupt(int irq, void *dev_id)
901{
902 struct net_device *dev = dev_id;
903 struct macb *bp = netdev_priv(dev);
904 u32 status;
905
906 status = macb_readl(bp, ISR);
907
908 if (unlikely(!status))
909 return IRQ_NONE;
910
911 spin_lock(&bp->lock);
912
913 while (status) {
914 /* close possible race with dev_close */
915 if (unlikely(!netif_running(dev))) {
916 macb_writel(bp, IDR, -1);
917 break;
918 }
919
920 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
921
922 if (status & MACB_RX_INT_FLAGS) {
923 /*
924 * There's no point taking any more interrupts
925 * until we have processed the buffers. The
926 * scheduling call may fail if the poll routine
927 * is already scheduled, so disable interrupts
928 * now.
929 */
930 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
931 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
932 macb_writel(bp, ISR, MACB_BIT(RCOMP));
933
934 if (napi_schedule_prep(&bp->napi)) {
935 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
936 __napi_schedule(&bp->napi);
937 }
938 }
939
940 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
941 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
942 schedule_work(&bp->tx_error_task);
943
944 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
945 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
946
947 break;
948 }
949
950 if (status & MACB_BIT(TCOMP))
951 macb_tx_interrupt(bp);
952
953 /*
954 * Link change detection isn't possible with RMII, so we'll
955 * add that if/when we get our hands on a full-blown MII PHY.
956 */
957
958 if (status & MACB_BIT(ISR_ROVR)) {
959 /* We missed at least one packet */
960 if (macb_is_gem(bp))
961 bp->hw_stats.gem.rx_overruns++;
962 else
963 bp->hw_stats.macb.rx_overruns++;
964
965 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
966 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
967 }
968
969 if (status & MACB_BIT(HRESP)) {
970 /*
971 * TODO: Reset the hardware, and maybe move the
972 * netdev_err to a lower-priority context as well
973 * (work queue?)
974 */
975 netdev_err(dev, "DMA bus error: HRESP not OK\n");
976
977 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
978 macb_writel(bp, ISR, MACB_BIT(HRESP));
979 }
980
981 status = macb_readl(bp, ISR);
982 }
983
984 spin_unlock(&bp->lock);
985
986 return IRQ_HANDLED;
987}
988
989#ifdef CONFIG_NET_POLL_CONTROLLER
990/*
991 * Polling receive - used by netconsole and other diagnostic tools
992 * to allow network i/o with interrupts disabled.
993 */
994static void macb_poll_controller(struct net_device *dev)
995{
996 unsigned long flags;
997
998 local_irq_save(flags);
999 macb_interrupt(dev->irq, dev);
1000 local_irq_restore(flags);
1001}
1002#endif
1003
1004static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1005{
1006 struct macb *bp = netdev_priv(dev);
1007 dma_addr_t mapping;
1008 unsigned int len, entry;
1009 struct macb_dma_desc *desc;
1010 struct macb_tx_skb *tx_skb;
1011 u32 ctrl;
1012 unsigned long flags;
1013
1014#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1015 netdev_vdbg(bp->dev,
1016 "start_xmit: len %u head %p data %p tail %p end %p\n",
1017 skb->len, skb->head, skb->data,
1018 skb_tail_pointer(skb), skb_end_pointer(skb));
1019 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1020 skb->data, 16, true);
1021#endif
1022
1023 len = skb->len;
1024 spin_lock_irqsave(&bp->lock, flags);
1025
1026 /* This is a hard error, log it. */
1027 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
1028 netif_stop_queue(dev);
1029 spin_unlock_irqrestore(&bp->lock, flags);
1030 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1031 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1032 bp->tx_head, bp->tx_tail);
1033 return NETDEV_TX_BUSY;
1034 }
1035
1036 entry = macb_tx_ring_wrap(bp->tx_head);
1037 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
1038 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1039 len, DMA_TO_DEVICE);
1040 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
1041 dev_kfree_skb_any(skb);
1042 goto unlock;
1043 }
1044
1045 bp->tx_head++;
1046 tx_skb = &bp->tx_skb[entry];
1047 tx_skb->skb = skb;
1048 tx_skb->mapping = mapping;
1049 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1050 skb->data, (unsigned long)mapping);
1051
1052 ctrl = MACB_BF(TX_FRMLEN, len);
1053 ctrl |= MACB_BIT(TX_LAST);
1054 if (entry == (TX_RING_SIZE - 1))
1055 ctrl |= MACB_BIT(TX_WRAP);
1056
1057 desc = &bp->tx_ring[entry];
1058 desc->addr = mapping;
1059 desc->ctrl = ctrl;
1060
1061 /* Make newly initialized descriptor visible to hardware */
1062 wmb();
1063
1064 skb_tx_timestamp(skb);
1065
1066 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1067
1068 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1069 netif_stop_queue(dev);
1070
1071unlock:
1072 spin_unlock_irqrestore(&bp->lock, flags);
1073
1074 return NETDEV_TX_OK;
1075}
1076
1077static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1078{
1079 if (!macb_is_gem(bp)) {
1080 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1081 } else {
1082 bp->rx_buffer_size = size;
1083
1084 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1085 netdev_dbg(bp->dev,
1086 "RX buffer must be multiple of %d bytes, expanding\n",
1087 RX_BUFFER_MULTIPLE);
1088 bp->rx_buffer_size =
1089 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1090 }
1091 }
1092
1093 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1094 bp->dev->mtu, bp->rx_buffer_size);
1095}
1096
1097static void gem_free_rx_buffers(struct macb *bp)
1098{
1099 struct sk_buff *skb;
1100 struct macb_dma_desc *desc;
1101 dma_addr_t addr;
1102 int i;
1103
1104 if (!bp->rx_skbuff)
1105 return;
1106
1107 for (i = 0; i < RX_RING_SIZE; i++) {
1108 skb = bp->rx_skbuff[i];
1109
1110 if (skb == NULL)
1111 continue;
1112
1113 desc = &bp->rx_ring[i];
1114 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1115 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1116 DMA_FROM_DEVICE);
1117 dev_kfree_skb_any(skb);
1118 skb = NULL;
1119 }
1120
1121 kfree(bp->rx_skbuff);
1122 bp->rx_skbuff = NULL;
1123}
1124
1125static void macb_free_rx_buffers(struct macb *bp)
1126{
1127 if (bp->rx_buffers) {
1128 dma_free_coherent(&bp->pdev->dev,
1129 RX_RING_SIZE * bp->rx_buffer_size,
1130 bp->rx_buffers, bp->rx_buffers_dma);
1131 bp->rx_buffers = NULL;
1132 }
1133}
1134
1135static void macb_free_consistent(struct macb *bp)
1136{
1137 if (bp->tx_skb) {
1138 kfree(bp->tx_skb);
1139 bp->tx_skb = NULL;
1140 }
1141 bp->macbgem_ops.mog_free_rx_buffers(bp);
1142 if (bp->rx_ring) {
1143 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1144 bp->rx_ring, bp->rx_ring_dma);
1145 bp->rx_ring = NULL;
1146 }
1147 if (bp->tx_ring) {
1148 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1149 bp->tx_ring, bp->tx_ring_dma);
1150 bp->tx_ring = NULL;
1151 }
1152}
1153
1154static int gem_alloc_rx_buffers(struct macb *bp)
1155{
1156 int size;
1157
1158 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1159 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1160 if (!bp->rx_skbuff)
1161 return -ENOMEM;
1162 else
1163 netdev_dbg(bp->dev,
1164 "Allocated %d RX struct sk_buff entries at %p\n",
1165 RX_RING_SIZE, bp->rx_skbuff);
1166 return 0;
1167}
1168
1169static int macb_alloc_rx_buffers(struct macb *bp)
1170{
1171 int size;
1172
1173 size = RX_RING_SIZE * bp->rx_buffer_size;
1174 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1175 &bp->rx_buffers_dma, GFP_KERNEL);
1176 if (!bp->rx_buffers)
1177 return -ENOMEM;
1178 else
1179 netdev_dbg(bp->dev,
1180 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1181 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1182 return 0;
1183}
1184
1185static int macb_alloc_consistent(struct macb *bp)
1186{
1187 int size;
1188
1189 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1190 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1191 if (!bp->tx_skb)
1192 goto out_err;
1193
1194 size = RX_RING_BYTES;
1195 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1196 &bp->rx_ring_dma, GFP_KERNEL);
1197 if (!bp->rx_ring)
1198 goto out_err;
1199 netdev_dbg(bp->dev,
1200 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1201 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1202
1203 size = TX_RING_BYTES;
1204 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1205 &bp->tx_ring_dma, GFP_KERNEL);
1206 if (!bp->tx_ring)
1207 goto out_err;
1208 netdev_dbg(bp->dev,
1209 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1210 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1211
1212 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1213 goto out_err;
1214
1215 return 0;
1216
1217out_err:
1218 macb_free_consistent(bp);
1219 return -ENOMEM;
1220}
1221
1222static void gem_init_rings(struct macb *bp)
1223{
1224 int i;
1225
1226 for (i = 0; i < TX_RING_SIZE; i++) {
1227 bp->tx_ring[i].addr = 0;
1228 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1229 }
1230 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1231
1232 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1233
1234 gem_rx_refill(bp);
1235}
1236
1237static void macb_init_rings(struct macb *bp)
1238{
1239 int i;
1240 dma_addr_t addr;
1241
1242 addr = bp->rx_buffers_dma;
1243 for (i = 0; i < RX_RING_SIZE; i++) {
1244 bp->rx_ring[i].addr = addr;
1245 bp->rx_ring[i].ctrl = 0;
1246 addr += bp->rx_buffer_size;
1247 }
1248 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1249
1250 for (i = 0; i < TX_RING_SIZE; i++) {
1251 bp->tx_ring[i].addr = 0;
1252 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1253 }
1254 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1255
1256 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1257}
1258
1259static void macb_reset_hw(struct macb *bp)
1260{
1261 /*
1262 * Disable RX and TX (XXX: Should we halt the transmission
1263 * more gracefully?)
1264 */
1265 macb_writel(bp, NCR, 0);
1266
1267 /* Clear the stats registers (XXX: Update stats first?) */
1268 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1269
1270 /* Clear all status flags */
1271 macb_writel(bp, TSR, -1);
1272 macb_writel(bp, RSR, -1);
1273
1274 /* Disable all interrupts */
1275 macb_writel(bp, IDR, -1);
1276 macb_readl(bp, ISR);
1277}
1278
1279static u32 gem_mdc_clk_div(struct macb *bp)
1280{
1281 u32 config;
1282 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1283
1284 if (pclk_hz <= 20000000)
1285 config = GEM_BF(CLK, GEM_CLK_DIV8);
1286 else if (pclk_hz <= 40000000)
1287 config = GEM_BF(CLK, GEM_CLK_DIV16);
1288 else if (pclk_hz <= 80000000)
1289 config = GEM_BF(CLK, GEM_CLK_DIV32);
1290 else if (pclk_hz <= 120000000)
1291 config = GEM_BF(CLK, GEM_CLK_DIV48);
1292 else if (pclk_hz <= 160000000)
1293 config = GEM_BF(CLK, GEM_CLK_DIV64);
1294 else
1295 config = GEM_BF(CLK, GEM_CLK_DIV96);
1296
1297 return config;
1298}
1299
1300static u32 macb_mdc_clk_div(struct macb *bp)
1301{
1302 u32 config;
1303 unsigned long pclk_hz;
1304
1305 if (macb_is_gem(bp))
1306 return gem_mdc_clk_div(bp);
1307
1308 pclk_hz = clk_get_rate(bp->pclk);
1309 if (pclk_hz <= 20000000)
1310 config = MACB_BF(CLK, MACB_CLK_DIV8);
1311 else if (pclk_hz <= 40000000)
1312 config = MACB_BF(CLK, MACB_CLK_DIV16);
1313 else if (pclk_hz <= 80000000)
1314 config = MACB_BF(CLK, MACB_CLK_DIV32);
1315 else
1316 config = MACB_BF(CLK, MACB_CLK_DIV64);
1317
1318 return config;
1319}
1320
1321/*
1322 * Get the DMA bus width field of the network configuration register that we
1323 * should program. We find the width from decoding the design configuration
1324 * register to find the maximum supported data bus width.
1325 */
1326static u32 macb_dbw(struct macb *bp)
1327{
1328 if (!macb_is_gem(bp))
1329 return 0;
1330
1331 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1332 case 4:
1333 return GEM_BF(DBW, GEM_DBW128);
1334 case 2:
1335 return GEM_BF(DBW, GEM_DBW64);
1336 case 1:
1337 default:
1338 return GEM_BF(DBW, GEM_DBW32);
1339 }
1340}
1341
1342/*
1343 * Configure the receive DMA engine
1344 * - use the correct receive buffer size
1345 * - set the possibility to use INCR16 bursts
1346 * (if not supported by FIFO, it will fallback to default)
1347 * - set both rx/tx packet buffers to full memory size
1348 * These are configurable parameters for GEM.
1349 */
1350static void macb_configure_dma(struct macb *bp)
1351{
1352 u32 dmacfg;
1353
1354 if (macb_is_gem(bp)) {
1355 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1356 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1357 dmacfg |= GEM_BF(FBLDO, 16);
1358 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1359 dmacfg &= ~GEM_BIT(ENDIA);
1360 gem_writel(bp, DMACFG, dmacfg);
1361 }
1362}
1363
1364/*
1365 * Configure peripheral capacities according to integration options used
1366 */
1367static void macb_configure_caps(struct macb *bp)
1368{
1369 if (macb_is_gem(bp)) {
1370 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1371 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1372 }
1373}
1374
1375static void macb_init_hw(struct macb *bp)
1376{
1377 u32 config;
1378
1379 macb_reset_hw(bp);
1380 macb_set_hwaddr(bp);
1381
1382 config = macb_mdc_clk_div(bp);
1383 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1384 config |= MACB_BIT(PAE); /* PAuse Enable */
1385 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1386 config |= MACB_BIT(BIG); /* Receive oversized frames */
1387 if (bp->dev->flags & IFF_PROMISC)
1388 config |= MACB_BIT(CAF); /* Copy All Frames */
1389 if (!(bp->dev->flags & IFF_BROADCAST))
1390 config |= MACB_BIT(NBC); /* No BroadCast */
1391 config |= macb_dbw(bp);
1392 macb_writel(bp, NCFGR, config);
1393 bp->speed = SPEED_10;
1394 bp->duplex = DUPLEX_HALF;
1395
1396 macb_configure_dma(bp);
1397 macb_configure_caps(bp);
1398
1399 /* Initialize TX and RX buffers */
1400 macb_writel(bp, RBQP, bp->rx_ring_dma);
1401 macb_writel(bp, TBQP, bp->tx_ring_dma);
1402
1403 /* Enable TX and RX */
1404 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1405
1406 /* Enable interrupts */
1407 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1408 | MACB_TX_INT_FLAGS
1409 | MACB_BIT(HRESP)));
1410
1411}
1412
1413/*
1414 * The hash address register is 64 bits long and takes up two
1415 * locations in the memory map. The least significant bits are stored
1416 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1417 *
1418 * The unicast hash enable and the multicast hash enable bits in the
1419 * network configuration register enable the reception of hash matched
1420 * frames. The destination address is reduced to a 6 bit index into
1421 * the 64 bit hash register using the following hash function. The
1422 * hash function is an exclusive or of every sixth bit of the
1423 * destination address.
1424 *
1425 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1426 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1427 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1428 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1429 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1430 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1431 *
1432 * da[0] represents the least significant bit of the first byte
1433 * received, that is, the multicast/unicast indicator, and da[47]
1434 * represents the most significant bit of the last byte received. If
1435 * the hash index, hi[n], points to a bit that is set in the hash
1436 * register then the frame will be matched according to whether the
1437 * frame is multicast or unicast. A multicast match will be signalled
1438 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1439 * index points to a bit set in the hash register. A unicast match
1440 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1441 * and the hash index points to a bit set in the hash register. To
1442 * receive all multicast frames, the hash register should be set with
1443 * all ones and the multicast hash enable bit should be set in the
1444 * network configuration register.
1445 */
1446
1447static inline int hash_bit_value(int bitnr, __u8 *addr)
1448{
1449 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1450 return 1;
1451 return 0;
1452}
1453
1454/*
1455 * Return the hash index value for the specified address.
1456 */
1457static int hash_get_index(__u8 *addr)
1458{
1459 int i, j, bitval;
1460 int hash_index = 0;
1461
1462 for (j = 0; j < 6; j++) {
1463 for (i = 0, bitval = 0; i < 8; i++)
1464 bitval ^= hash_bit_value(i*6 + j, addr);
1465
1466 hash_index |= (bitval << j);
1467 }
1468
1469 return hash_index;
1470}
1471
1472/*
1473 * Add multicast addresses to the internal multicast-hash table.
1474 */
1475static void macb_sethashtable(struct net_device *dev)
1476{
1477 struct netdev_hw_addr *ha;
1478 unsigned long mc_filter[2];
1479 unsigned int bitnr;
1480 struct macb *bp = netdev_priv(dev);
1481
1482 mc_filter[0] = mc_filter[1] = 0;
1483
1484 netdev_for_each_mc_addr(ha, dev) {
1485 bitnr = hash_get_index(ha->addr);
1486 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1487 }
1488
1489 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1490 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1491}
1492
1493/*
1494 * Enable/Disable promiscuous and multicast modes.
1495 */
1496void macb_set_rx_mode(struct net_device *dev)
1497{
1498 unsigned long cfg;
1499 struct macb *bp = netdev_priv(dev);
1500
1501 cfg = macb_readl(bp, NCFGR);
1502
1503 if (dev->flags & IFF_PROMISC)
1504 /* Enable promiscuous mode */
1505 cfg |= MACB_BIT(CAF);
1506 else if (dev->flags & (~IFF_PROMISC))
1507 /* Disable promiscuous mode */
1508 cfg &= ~MACB_BIT(CAF);
1509
1510 if (dev->flags & IFF_ALLMULTI) {
1511 /* Enable all multicast mode */
1512 macb_or_gem_writel(bp, HRB, -1);
1513 macb_or_gem_writel(bp, HRT, -1);
1514 cfg |= MACB_BIT(NCFGR_MTI);
1515 } else if (!netdev_mc_empty(dev)) {
1516 /* Enable specific multicasts */
1517 macb_sethashtable(dev);
1518 cfg |= MACB_BIT(NCFGR_MTI);
1519 } else if (dev->flags & (~IFF_ALLMULTI)) {
1520 /* Disable all multicast mode */
1521 macb_or_gem_writel(bp, HRB, 0);
1522 macb_or_gem_writel(bp, HRT, 0);
1523 cfg &= ~MACB_BIT(NCFGR_MTI);
1524 }
1525
1526 macb_writel(bp, NCFGR, cfg);
1527}
1528EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1529
1530static int macb_open(struct net_device *dev)
1531{
1532 struct macb *bp = netdev_priv(dev);
1533 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1534 int err;
1535
1536 netdev_dbg(bp->dev, "open\n");
1537
1538 /* carrier starts down */
1539 netif_carrier_off(dev);
1540
1541 /* if the phy is not yet register, retry later*/
1542 if (!bp->phy_dev)
1543 return -EAGAIN;
1544
1545 /* RX buffers initialization */
1546 macb_init_rx_buffer_size(bp, bufsz);
1547
1548 err = macb_alloc_consistent(bp);
1549 if (err) {
1550 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1551 err);
1552 return err;
1553 }
1554
1555 napi_enable(&bp->napi);
1556
1557 bp->macbgem_ops.mog_init_rings(bp);
1558 macb_init_hw(bp);
1559
1560 /* schedule a link state check */
1561 phy_start(bp->phy_dev);
1562
1563 netif_start_queue(dev);
1564
1565 return 0;
1566}
1567
1568static int macb_close(struct net_device *dev)
1569{
1570 struct macb *bp = netdev_priv(dev);
1571 unsigned long flags;
1572
1573 netif_stop_queue(dev);
1574 napi_disable(&bp->napi);
1575
1576 if (bp->phy_dev)
1577 phy_stop(bp->phy_dev);
1578
1579 spin_lock_irqsave(&bp->lock, flags);
1580 macb_reset_hw(bp);
1581 netif_carrier_off(dev);
1582 spin_unlock_irqrestore(&bp->lock, flags);
1583
1584 macb_free_consistent(bp);
1585
1586 return 0;
1587}
1588
1589static void gem_update_stats(struct macb *bp)
1590{
1591 u32 __iomem *reg = bp->regs + GEM_OTX;
1592 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1593 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1594
1595 for (; p < end; p++, reg++)
1596 *p += __raw_readl(reg);
1597}
1598
1599static struct net_device_stats *gem_get_stats(struct macb *bp)
1600{
1601 struct gem_stats *hwstat = &bp->hw_stats.gem;
1602 struct net_device_stats *nstat = &bp->stats;
1603
1604 gem_update_stats(bp);
1605
1606 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1607 hwstat->rx_alignment_errors +
1608 hwstat->rx_resource_errors +
1609 hwstat->rx_overruns +
1610 hwstat->rx_oversize_frames +
1611 hwstat->rx_jabbers +
1612 hwstat->rx_undersized_frames +
1613 hwstat->rx_length_field_frame_errors);
1614 nstat->tx_errors = (hwstat->tx_late_collisions +
1615 hwstat->tx_excessive_collisions +
1616 hwstat->tx_underrun +
1617 hwstat->tx_carrier_sense_errors);
1618 nstat->multicast = hwstat->rx_multicast_frames;
1619 nstat->collisions = (hwstat->tx_single_collision_frames +
1620 hwstat->tx_multiple_collision_frames +
1621 hwstat->tx_excessive_collisions);
1622 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1623 hwstat->rx_jabbers +
1624 hwstat->rx_undersized_frames +
1625 hwstat->rx_length_field_frame_errors);
1626 nstat->rx_over_errors = hwstat->rx_resource_errors;
1627 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1628 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1629 nstat->rx_fifo_errors = hwstat->rx_overruns;
1630 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1631 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1632 nstat->tx_fifo_errors = hwstat->tx_underrun;
1633
1634 return nstat;
1635}
1636
1637struct net_device_stats *macb_get_stats(struct net_device *dev)
1638{
1639 struct macb *bp = netdev_priv(dev);
1640 struct net_device_stats *nstat = &bp->stats;
1641 struct macb_stats *hwstat = &bp->hw_stats.macb;
1642
1643 if (macb_is_gem(bp))
1644 return gem_get_stats(bp);
1645
1646 /* read stats from hardware */
1647 macb_update_stats(bp);
1648
1649 /* Convert HW stats into netdevice stats */
1650 nstat->rx_errors = (hwstat->rx_fcs_errors +
1651 hwstat->rx_align_errors +
1652 hwstat->rx_resource_errors +
1653 hwstat->rx_overruns +
1654 hwstat->rx_oversize_pkts +
1655 hwstat->rx_jabbers +
1656 hwstat->rx_undersize_pkts +
1657 hwstat->sqe_test_errors +
1658 hwstat->rx_length_mismatch);
1659 nstat->tx_errors = (hwstat->tx_late_cols +
1660 hwstat->tx_excessive_cols +
1661 hwstat->tx_underruns +
1662 hwstat->tx_carrier_errors);
1663 nstat->collisions = (hwstat->tx_single_cols +
1664 hwstat->tx_multiple_cols +
1665 hwstat->tx_excessive_cols);
1666 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1667 hwstat->rx_jabbers +
1668 hwstat->rx_undersize_pkts +
1669 hwstat->rx_length_mismatch);
1670 nstat->rx_over_errors = hwstat->rx_resource_errors +
1671 hwstat->rx_overruns;
1672 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1673 nstat->rx_frame_errors = hwstat->rx_align_errors;
1674 nstat->rx_fifo_errors = hwstat->rx_overruns;
1675 /* XXX: What does "missed" mean? */
1676 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1677 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1678 nstat->tx_fifo_errors = hwstat->tx_underruns;
1679 /* Don't know about heartbeat or window errors... */
1680
1681 return nstat;
1682}
1683EXPORT_SYMBOL_GPL(macb_get_stats);
1684
1685static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1686{
1687 struct macb *bp = netdev_priv(dev);
1688 struct phy_device *phydev = bp->phy_dev;
1689
1690 if (!phydev)
1691 return -ENODEV;
1692
1693 return phy_ethtool_gset(phydev, cmd);
1694}
1695
1696static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1697{
1698 struct macb *bp = netdev_priv(dev);
1699 struct phy_device *phydev = bp->phy_dev;
1700
1701 if (!phydev)
1702 return -ENODEV;
1703
1704 return phy_ethtool_sset(phydev, cmd);
1705}
1706
1707static int macb_get_regs_len(struct net_device *netdev)
1708{
1709 return MACB_GREGS_NBR * sizeof(u32);
1710}
1711
1712static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1713 void *p)
1714{
1715 struct macb *bp = netdev_priv(dev);
1716 unsigned int tail, head;
1717 u32 *regs_buff = p;
1718
1719 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1720 | MACB_GREGS_VERSION;
1721
1722 tail = macb_tx_ring_wrap(bp->tx_tail);
1723 head = macb_tx_ring_wrap(bp->tx_head);
1724
1725 regs_buff[0] = macb_readl(bp, NCR);
1726 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1727 regs_buff[2] = macb_readl(bp, NSR);
1728 regs_buff[3] = macb_readl(bp, TSR);
1729 regs_buff[4] = macb_readl(bp, RBQP);
1730 regs_buff[5] = macb_readl(bp, TBQP);
1731 regs_buff[6] = macb_readl(bp, RSR);
1732 regs_buff[7] = macb_readl(bp, IMR);
1733
1734 regs_buff[8] = tail;
1735 regs_buff[9] = head;
1736 regs_buff[10] = macb_tx_dma(bp, tail);
1737 regs_buff[11] = macb_tx_dma(bp, head);
1738
1739 if (macb_is_gem(bp)) {
1740 regs_buff[12] = gem_readl(bp, USRIO);
1741 regs_buff[13] = gem_readl(bp, DMACFG);
1742 }
1743}
1744
1745const struct ethtool_ops macb_ethtool_ops = {
1746 .get_settings = macb_get_settings,
1747 .set_settings = macb_set_settings,
1748 .get_regs_len = macb_get_regs_len,
1749 .get_regs = macb_get_regs,
1750 .get_link = ethtool_op_get_link,
1751 .get_ts_info = ethtool_op_get_ts_info,
1752};
1753EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1754
1755int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1756{
1757 struct macb *bp = netdev_priv(dev);
1758 struct phy_device *phydev = bp->phy_dev;
1759
1760 if (!netif_running(dev))
1761 return -EINVAL;
1762
1763 if (!phydev)
1764 return -ENODEV;
1765
1766 return phy_mii_ioctl(phydev, rq, cmd);
1767}
1768EXPORT_SYMBOL_GPL(macb_ioctl);
1769
1770static const struct net_device_ops macb_netdev_ops = {
1771 .ndo_open = macb_open,
1772 .ndo_stop = macb_close,
1773 .ndo_start_xmit = macb_start_xmit,
1774 .ndo_set_rx_mode = macb_set_rx_mode,
1775 .ndo_get_stats = macb_get_stats,
1776 .ndo_do_ioctl = macb_ioctl,
1777 .ndo_validate_addr = eth_validate_addr,
1778 .ndo_change_mtu = eth_change_mtu,
1779 .ndo_set_mac_address = eth_mac_addr,
1780#ifdef CONFIG_NET_POLL_CONTROLLER
1781 .ndo_poll_controller = macb_poll_controller,
1782#endif
1783};
1784
1785#if defined(CONFIG_OF)
1786static const struct of_device_id macb_dt_ids[] = {
1787 { .compatible = "cdns,at32ap7000-macb" },
1788 { .compatible = "cdns,at91sam9260-macb" },
1789 { .compatible = "cdns,macb" },
1790 { .compatible = "cdns,pc302-gem" },
1791 { .compatible = "cdns,gem" },
1792 { /* sentinel */ }
1793};
1794MODULE_DEVICE_TABLE(of, macb_dt_ids);
1795#endif
1796
1797static int __init macb_probe(struct platform_device *pdev)
1798{
1799 struct macb_platform_data *pdata;
1800 struct resource *regs;
1801 struct net_device *dev;
1802 struct macb *bp;
1803 struct phy_device *phydev;
1804 u32 config;
1805 int err = -ENXIO;
1806 struct pinctrl *pinctrl;
1807 const char *mac;
1808
1809 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1810 if (!regs) {
1811 dev_err(&pdev->dev, "no mmio resource defined\n");
1812 goto err_out;
1813 }
1814
1815 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1816 if (IS_ERR(pinctrl)) {
1817 err = PTR_ERR(pinctrl);
1818 if (err == -EPROBE_DEFER)
1819 goto err_out;
1820
1821 dev_warn(&pdev->dev, "No pinctrl provided\n");
1822 }
1823
1824 err = -ENOMEM;
1825 dev = alloc_etherdev(sizeof(*bp));
1826 if (!dev)
1827 goto err_out;
1828
1829 SET_NETDEV_DEV(dev, &pdev->dev);
1830
1831 /* TODO: Actually, we have some interesting features... */
1832 dev->features |= 0;
1833
1834 bp = netdev_priv(dev);
1835 bp->pdev = pdev;
1836 bp->dev = dev;
1837
1838 spin_lock_init(&bp->lock);
1839 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1840
1841 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
1842 if (IS_ERR(bp->pclk)) {
1843 err = PTR_ERR(bp->pclk);
1844 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
1845 goto err_out_free_dev;
1846 }
1847
1848 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
1849 if (IS_ERR(bp->hclk)) {
1850 err = PTR_ERR(bp->hclk);
1851 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1852 goto err_out_free_dev;
1853 }
1854
1855 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1856
1857 err = clk_prepare_enable(bp->pclk);
1858 if (err) {
1859 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1860 goto err_out_free_dev;
1861 }
1862
1863 err = clk_prepare_enable(bp->hclk);
1864 if (err) {
1865 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1866 goto err_out_disable_pclk;
1867 }
1868
1869 if (!IS_ERR(bp->tx_clk)) {
1870 err = clk_prepare_enable(bp->tx_clk);
1871 if (err) {
1872 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1873 err);
1874 goto err_out_disable_hclk;
1875 }
1876 }
1877
1878 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
1879 if (!bp->regs) {
1880 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1881 err = -ENOMEM;
1882 goto err_out_disable_clocks;
1883 }
1884
1885 dev->irq = platform_get_irq(pdev, 0);
1886 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1887 dev->name, dev);
1888 if (err) {
1889 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1890 dev->irq, err);
1891 goto err_out_disable_clocks;
1892 }
1893
1894 dev->netdev_ops = &macb_netdev_ops;
1895 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1896 dev->ethtool_ops = &macb_ethtool_ops;
1897
1898 dev->base_addr = regs->start;
1899
1900 /* setup appropriated routines according to adapter type */
1901 if (macb_is_gem(bp)) {
1902 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1903 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1904 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1905 bp->macbgem_ops.mog_rx = gem_rx;
1906 } else {
1907 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1908 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1909 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1910 bp->macbgem_ops.mog_rx = macb_rx;
1911 }
1912
1913 /* Set MII management clock divider */
1914 config = macb_mdc_clk_div(bp);
1915 config |= macb_dbw(bp);
1916 macb_writel(bp, NCFGR, config);
1917
1918 mac = of_get_mac_address(pdev->dev.of_node);
1919 if (mac)
1920 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1921 else
1922 macb_get_hwaddr(bp);
1923
1924 err = of_get_phy_mode(pdev->dev.of_node);
1925 if (err < 0) {
1926 pdata = dev_get_platdata(&pdev->dev);
1927 if (pdata && pdata->is_rmii)
1928 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1929 else
1930 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1931 } else {
1932 bp->phy_interface = err;
1933 }
1934
1935 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1936 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1937 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1938#if defined(CONFIG_ARCH_AT91)
1939 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1940 MACB_BIT(CLKEN)));
1941#else
1942 macb_or_gem_writel(bp, USRIO, 0);
1943#endif
1944 else
1945#if defined(CONFIG_ARCH_AT91)
1946 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1947#else
1948 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1949#endif
1950
1951 err = register_netdev(dev);
1952 if (err) {
1953 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1954 goto err_out_disable_clocks;
1955 }
1956
1957 err = macb_mii_init(bp);
1958 if (err)
1959 goto err_out_unregister_netdev;
1960
1961 platform_set_drvdata(pdev, dev);
1962
1963 netif_carrier_off(dev);
1964
1965 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1966 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1967 dev->irq, dev->dev_addr);
1968
1969 phydev = bp->phy_dev;
1970 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1971 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1972
1973 return 0;
1974
1975err_out_unregister_netdev:
1976 unregister_netdev(dev);
1977err_out_disable_clocks:
1978 if (!IS_ERR(bp->tx_clk))
1979 clk_disable_unprepare(bp->tx_clk);
1980err_out_disable_hclk:
1981 clk_disable_unprepare(bp->hclk);
1982err_out_disable_pclk:
1983 clk_disable_unprepare(bp->pclk);
1984err_out_free_dev:
1985 free_netdev(dev);
1986err_out:
1987 return err;
1988}
1989
1990static int __exit macb_remove(struct platform_device *pdev)
1991{
1992 struct net_device *dev;
1993 struct macb *bp;
1994
1995 dev = platform_get_drvdata(pdev);
1996
1997 if (dev) {
1998 bp = netdev_priv(dev);
1999 if (bp->phy_dev)
2000 phy_disconnect(bp->phy_dev);
2001 mdiobus_unregister(bp->mii_bus);
2002 kfree(bp->mii_bus->irq);
2003 mdiobus_free(bp->mii_bus);
2004 unregister_netdev(dev);
2005 if (!IS_ERR(bp->tx_clk))
2006 clk_disable_unprepare(bp->tx_clk);
2007 clk_disable_unprepare(bp->hclk);
2008 clk_disable_unprepare(bp->pclk);
2009 free_netdev(dev);
2010 }
2011
2012 return 0;
2013}
2014
2015#ifdef CONFIG_PM
2016static int macb_suspend(struct device *dev)
2017{
2018 struct platform_device *pdev = to_platform_device(dev);
2019 struct net_device *netdev = platform_get_drvdata(pdev);
2020 struct macb *bp = netdev_priv(netdev);
2021
2022 netif_carrier_off(netdev);
2023 netif_device_detach(netdev);
2024
2025 if (!IS_ERR(bp->tx_clk))
2026 clk_disable_unprepare(bp->tx_clk);
2027 clk_disable_unprepare(bp->hclk);
2028 clk_disable_unprepare(bp->pclk);
2029
2030 return 0;
2031}
2032
2033static int macb_resume(struct device *dev)
2034{
2035 struct platform_device *pdev = to_platform_device(dev);
2036 struct net_device *netdev = platform_get_drvdata(pdev);
2037 struct macb *bp = netdev_priv(netdev);
2038
2039 clk_prepare_enable(bp->pclk);
2040 clk_prepare_enable(bp->hclk);
2041 if (!IS_ERR(bp->tx_clk))
2042 clk_prepare_enable(bp->tx_clk);
2043
2044 netif_device_attach(netdev);
2045
2046 return 0;
2047}
2048#endif
2049
2050static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2051
2052static struct platform_driver macb_driver = {
2053 .remove = __exit_p(macb_remove),
2054 .driver = {
2055 .name = "macb",
2056 .owner = THIS_MODULE,
2057 .of_match_table = of_match_ptr(macb_dt_ids),
2058 .pm = &macb_pm_ops,
2059 },
2060};
2061
2062module_platform_driver_probe(macb_driver, macb_probe);
2063
2064MODULE_LICENSE("GPL");
2065MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2066MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2067MODULE_ALIAS("platform:macb");