1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * st_spi_fsm.c	- ST Fast Sequence Mode (FSM) Serial Flash Controller
   4 *
   5 * Author: Angus Clark <angus.clark@st.com>
   6 *
   7 * Copyright (C) 2010-2014 STMicroelectronics Limited
   8 *
   9 * JEDEC probe based on drivers/mtd/devices/m25p80.c
 
 
 
 
 
  10 */
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/regmap.h>
  14#include <linux/platform_device.h>
  15#include <linux/mfd/syscon.h>
  16#include <linux/mtd/mtd.h>
  17#include <linux/mtd/partitions.h>
  18#include <linux/mtd/spi-nor.h>
  19#include <linux/sched.h>
  20#include <linux/delay.h>
  21#include <linux/io.h>
  22#include <linux/of.h>
  23#include <linux/clk.h>
  24
  25#include "serial_flash_cmds.h"
  26
  27/*
  28 * FSM SPI Controller Registers
  29 */
  30#define SPI_CLOCKDIV			0x0010
  31#define SPI_MODESELECT			0x0018
  32#define SPI_CONFIGDATA			0x0020
  33#define SPI_STA_MODE_CHANGE		0x0028
  34#define SPI_FAST_SEQ_TRANSFER_SIZE	0x0100
  35#define SPI_FAST_SEQ_ADD1		0x0104
  36#define SPI_FAST_SEQ_ADD2		0x0108
  37#define SPI_FAST_SEQ_ADD_CFG		0x010c
  38#define SPI_FAST_SEQ_OPC1		0x0110
  39#define SPI_FAST_SEQ_OPC2		0x0114
  40#define SPI_FAST_SEQ_OPC3		0x0118
  41#define SPI_FAST_SEQ_OPC4		0x011c
  42#define SPI_FAST_SEQ_OPC5		0x0120
  43#define SPI_MODE_BITS			0x0124
  44#define SPI_DUMMY_BITS			0x0128
  45#define SPI_FAST_SEQ_FLASH_STA_DATA	0x012c
  46#define SPI_FAST_SEQ_1			0x0130
  47#define SPI_FAST_SEQ_2			0x0134
  48#define SPI_FAST_SEQ_3			0x0138
  49#define SPI_FAST_SEQ_4			0x013c
  50#define SPI_FAST_SEQ_CFG		0x0140
  51#define SPI_FAST_SEQ_STA		0x0144
  52#define SPI_QUAD_BOOT_SEQ_INIT_1	0x0148
  53#define SPI_QUAD_BOOT_SEQ_INIT_2	0x014c
  54#define SPI_QUAD_BOOT_READ_SEQ_1	0x0150
  55#define SPI_QUAD_BOOT_READ_SEQ_2	0x0154
  56#define SPI_PROGRAM_ERASE_TIME		0x0158
  57#define SPI_MULT_PAGE_REPEAT_SEQ_1	0x015c
  58#define SPI_MULT_PAGE_REPEAT_SEQ_2	0x0160
  59#define SPI_STATUS_WR_TIME_REG		0x0164
  60#define SPI_FAST_SEQ_DATA_REG		0x0300
  61
  62/*
  63 * Register: SPI_MODESELECT
  64 */
  65#define SPI_MODESELECT_CONTIG		0x01
  66#define SPI_MODESELECT_FASTREAD		0x02
  67#define SPI_MODESELECT_DUALIO		0x04
  68#define SPI_MODESELECT_FSM		0x08
  69#define SPI_MODESELECT_QUADBOOT		0x10
  70
  71/*
  72 * Register: SPI_CONFIGDATA
  73 */
  74#define SPI_CFG_DEVICE_ST		0x1
  75#define SPI_CFG_DEVICE_ATMEL		0x4
  76#define SPI_CFG_MIN_CS_HIGH(x)		(((x) & 0xfff) << 4)
  77#define SPI_CFG_CS_SETUPHOLD(x)		(((x) & 0xff) << 16)
  78#define SPI_CFG_DATA_HOLD(x)		(((x) & 0xff) << 24)
  79
  80#define SPI_CFG_DEFAULT_MIN_CS_HIGH    SPI_CFG_MIN_CS_HIGH(0x0AA)
  81#define SPI_CFG_DEFAULT_CS_SETUPHOLD   SPI_CFG_CS_SETUPHOLD(0xA0)
  82#define SPI_CFG_DEFAULT_DATA_HOLD      SPI_CFG_DATA_HOLD(0x00)
  83
  84/*
  85 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
  86 */
  87#define TRANSFER_SIZE(x)		((x) * 8)
  88
  89/*
  90 * Register: SPI_FAST_SEQ_ADD_CFG
  91 */
  92#define ADR_CFG_CYCLES_ADD1(x)		((x) << 0)
  93#define ADR_CFG_PADS_1_ADD1		(0x0 << 6)
  94#define ADR_CFG_PADS_2_ADD1		(0x1 << 6)
  95#define ADR_CFG_PADS_4_ADD1		(0x3 << 6)
  96#define ADR_CFG_CSDEASSERT_ADD1		(1   << 8)
  97#define ADR_CFG_CYCLES_ADD2(x)		((x) << (0+16))
  98#define ADR_CFG_PADS_1_ADD2		(0x0 << (6+16))
  99#define ADR_CFG_PADS_2_ADD2		(0x1 << (6+16))
 100#define ADR_CFG_PADS_4_ADD2		(0x3 << (6+16))
 101#define ADR_CFG_CSDEASSERT_ADD2		(1   << (8+16))
 102
 103/*
 104 * Register: SPI_FAST_SEQ_n
 105 */
 106#define SEQ_OPC_OPCODE(x)		((x) << 0)
 107#define SEQ_OPC_CYCLES(x)		((x) << 8)
 108#define SEQ_OPC_PADS_1			(0x0 << 14)
 109#define SEQ_OPC_PADS_2			(0x1 << 14)
 110#define SEQ_OPC_PADS_4			(0x3 << 14)
 111#define SEQ_OPC_CSDEASSERT		(1   << 16)
 112
 113/*
 114 * Register: SPI_FAST_SEQ_CFG
 115 */
 116#define SEQ_CFG_STARTSEQ		(1 << 0)
 117#define SEQ_CFG_SWRESET			(1 << 5)
 118#define SEQ_CFG_CSDEASSERT		(1 << 6)
 119#define SEQ_CFG_READNOTWRITE		(1 << 7)
 120#define SEQ_CFG_ERASE			(1 << 8)
 121#define SEQ_CFG_PADS_1			(0x0 << 16)
 122#define SEQ_CFG_PADS_2			(0x1 << 16)
 123#define SEQ_CFG_PADS_4			(0x3 << 16)
 124
 125/*
 126 * Register: SPI_MODE_BITS
 127 */
 128#define MODE_DATA(x)			(x & 0xff)
 129#define MODE_CYCLES(x)			((x & 0x3f) << 16)
 130#define MODE_PADS_1			(0x0 << 22)
 131#define MODE_PADS_2			(0x1 << 22)
 132#define MODE_PADS_4			(0x3 << 22)
 133#define DUMMY_CSDEASSERT		(1   << 24)
 134
 135/*
 136 * Register: SPI_DUMMY_BITS
 137 */
 138#define DUMMY_CYCLES(x)			((x & 0x3f) << 16)
 139#define DUMMY_PADS_1			(0x0 << 22)
 140#define DUMMY_PADS_2			(0x1 << 22)
 141#define DUMMY_PADS_4			(0x3 << 22)
 142#define DUMMY_CSDEASSERT		(1   << 24)
 143
 144/*
 145 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
 146 */
 147#define STA_DATA_BYTE1(x)		((x & 0xff) << 0)
 148#define STA_DATA_BYTE2(x)		((x & 0xff) << 8)
 149#define STA_PADS_1			(0x0 << 16)
 150#define STA_PADS_2			(0x1 << 16)
 151#define STA_PADS_4			(0x3 << 16)
 152#define STA_CSDEASSERT			(0x1 << 20)
 153#define STA_RDNOTWR			(0x1 << 21)
 154
 155/*
 156 * FSM SPI Instruction Opcodes
 157 */
 158#define STFSM_OPC_CMD			0x1
 159#define STFSM_OPC_ADD			0x2
 160#define STFSM_OPC_STA			0x3
 161#define STFSM_OPC_MODE			0x4
 162#define STFSM_OPC_DUMMY		0x5
 163#define STFSM_OPC_DATA			0x6
 164#define STFSM_OPC_WAIT			0x7
 165#define STFSM_OPC_JUMP			0x8
 166#define STFSM_OPC_GOTO			0x9
 167#define STFSM_OPC_STOP			0xF
 168
 169/*
 170 * FSM SPI Instructions (== opcode + operand).
 171 */
 172#define STFSM_INSTR(cmd, op)		((cmd) | ((op) << 4))
 173
 174#define STFSM_INST_CMD1			STFSM_INSTR(STFSM_OPC_CMD,	1)
 175#define STFSM_INST_CMD2			STFSM_INSTR(STFSM_OPC_CMD,	2)
 176#define STFSM_INST_CMD3			STFSM_INSTR(STFSM_OPC_CMD,	3)
 177#define STFSM_INST_CMD4			STFSM_INSTR(STFSM_OPC_CMD,	4)
 178#define STFSM_INST_CMD5			STFSM_INSTR(STFSM_OPC_CMD,	5)
 179#define STFSM_INST_ADD1			STFSM_INSTR(STFSM_OPC_ADD,	1)
 180#define STFSM_INST_ADD2			STFSM_INSTR(STFSM_OPC_ADD,	2)
 181
 182#define STFSM_INST_DATA_WRITE		STFSM_INSTR(STFSM_OPC_DATA,	1)
 183#define STFSM_INST_DATA_READ		STFSM_INSTR(STFSM_OPC_DATA,	2)
 184
 185#define STFSM_INST_STA_RD1		STFSM_INSTR(STFSM_OPC_STA,	0x1)
 186#define STFSM_INST_STA_WR1		STFSM_INSTR(STFSM_OPC_STA,	0x1)
 187#define STFSM_INST_STA_RD2		STFSM_INSTR(STFSM_OPC_STA,	0x2)
 188#define STFSM_INST_STA_WR1_2		STFSM_INSTR(STFSM_OPC_STA,	0x3)
 189
 190#define STFSM_INST_MODE			STFSM_INSTR(STFSM_OPC_MODE,	0)
 191#define STFSM_INST_DUMMY		STFSM_INSTR(STFSM_OPC_DUMMY,	0)
 192#define STFSM_INST_WAIT			STFSM_INSTR(STFSM_OPC_WAIT,	0)
 193#define STFSM_INST_STOP			STFSM_INSTR(STFSM_OPC_STOP,	0)
 194
 195#define STFSM_DEFAULT_EMI_FREQ 100000000UL                        /* 100 MHz */
 196#define STFSM_DEFAULT_WR_TIME  (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
 197
 198#define STFSM_FLASH_SAFE_FREQ  10000000UL                         /* 10 MHz */
 199
 200#define STFSM_MAX_WAIT_SEQ_MS  1000     /* FSM execution time */
 201
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 202/* S25FLxxxS commands */
 203#define S25FL_CMD_WRITE4_1_1_4 0x34
 204#define S25FL_CMD_SE4          0xdc
 205#define S25FL_CMD_CLSR         0x30
 206#define S25FL_CMD_DYBWR                0xe1
 207#define S25FL_CMD_DYBRD                0xe0
 208#define S25FL_CMD_WRITE4       0x12    /* Note, opcode clashes with
 209					* 'SPINOR_OP_WRITE_1_4_4'
 210					* as found on N25Qxxx devices! */
 211
 212/* Status register */
 213#define FLASH_STATUS_BUSY      0x01
 214#define FLASH_STATUS_WEL       0x02
 215#define FLASH_STATUS_BP0       0x04
 216#define FLASH_STATUS_BP1       0x08
 217#define FLASH_STATUS_BP2       0x10
 218#define FLASH_STATUS_SRWP0     0x80
 219#define FLASH_STATUS_TIMEOUT   0xff
 220/* S25FL Error Flags */
 221#define S25FL_STATUS_E_ERR     0x20
 222#define S25FL_STATUS_P_ERR     0x40
 223
 224#define N25Q_CMD_WRVCR         0x81
 225#define N25Q_CMD_RDVCR         0x85
 226#define N25Q_CMD_RDVECR        0x65
 227#define N25Q_CMD_RDNVCR        0xb5
 228#define N25Q_CMD_WRNVCR        0xb1
 229
 230#define FLASH_PAGESIZE         256			/* In Bytes    */
 231#define FLASH_PAGESIZE_32      (FLASH_PAGESIZE / 4)	/* In uint32_t */
 232#define FLASH_MAX_BUSY_WAIT    (300 * HZ)	/* Maximum 'CHIPERASE' time */
 233
 234/*
 235 * Flags to tweak operation of default read/write/erase routines
 236 */
 237#define CFG_READ_TOGGLE_32BIT_ADDR     0x00000001
 238#define CFG_WRITE_TOGGLE_32BIT_ADDR    0x00000002
 
 239#define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008
 240#define CFG_S25FL_CHECK_ERROR_FLAGS    0x00000010
 241
 242struct stfsm_seq {
 243	uint32_t data_size;
 244	uint32_t addr1;
 245	uint32_t addr2;
 246	uint32_t addr_cfg;
 247	uint32_t seq_opc[5];
 248	uint32_t mode;
 249	uint32_t dummy;
 250	uint32_t status;
 251	uint8_t  seq[16];
 252	uint32_t seq_cfg;
 253} __packed __aligned(4);
 254
 255struct stfsm {
 256	struct device		*dev;
 257	void __iomem		*base;
 
 258	struct mtd_info		mtd;
 259	struct mutex		lock;
 260	struct flash_info       *info;
 261	struct clk              *clk;
 262
 263	uint32_t                configuration;
 264	uint32_t                fifo_dir_delay;
 265	bool                    booted_from_spi;
 266	bool                    reset_signal;
 267	bool                    reset_por;
 268
 269	struct stfsm_seq stfsm_seq_read;
 270	struct stfsm_seq stfsm_seq_write;
 271	struct stfsm_seq stfsm_seq_en_32bit_addr;
 272};
 273
 274/* Parameters to configure a READ or WRITE FSM sequence */
 275struct seq_rw_config {
 276	uint32_t        flags;          /* flags to support config */
 277	uint8_t         cmd;            /* FLASH command */
 278	int             write;          /* Write Sequence */
 279	uint8_t         addr_pads;      /* No. of addr pads (MODE & DUMMY) */
 280	uint8_t         data_pads;      /* No. of data pads */
 281	uint8_t         mode_data;      /* MODE data */
 282	uint8_t         mode_cycles;    /* No. of MODE cycles */
 283	uint8_t         dummy_cycles;   /* No. of DUMMY cycles */
 284};
 285
 286/* SPI Flash Device Table */
 287struct flash_info {
 288	char            *name;
 289	/*
 290	 * JEDEC id zero means "no ID" (most older chips); otherwise it has
 291	 * a high byte of zero plus three data bytes: the manufacturer id,
 292	 * then a two byte device id.
 293	 */
 294	u32             jedec_id;
 295	u16             ext_id;
 296	/*
 297	 * The size listed here is what works with SPINOR_OP_SE, which isn't
 298	 * necessarily called a "sector" by the vendor.
 299	 */
 300	unsigned        sector_size;
 301	u16             n_sectors;
 302	u32             flags;
 303	/*
 304	 * Note, where FAST_READ is supported, freq_max specifies the
 305	 * FAST_READ frequency, not the READ frequency.
 306	 */
 307	u32             max_freq;
 308	int             (*config)(struct stfsm *);
 309};
 310
 311static int stfsm_n25q_config(struct stfsm *fsm);
 312static int stfsm_mx25_config(struct stfsm *fsm);
 313static int stfsm_s25fl_config(struct stfsm *fsm);
 314static int stfsm_w25q_config(struct stfsm *fsm);
 315
 316static struct flash_info flash_types[] = {
 317	/*
 318	 * ST Microelectronics/Numonyx --
 319	 * (newer production versions may have feature updates
 320	 * (eg faster operating frequency)
 321	 */
 322#define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
 323	{ "m25p40",  0x202013, 0,  64 * 1024,   8, M25P_FLAG, 25, NULL },
 324	{ "m25p80",  0x202014, 0,  64 * 1024,  16, M25P_FLAG, 25, NULL },
 325	{ "m25p16",  0x202015, 0,  64 * 1024,  32, M25P_FLAG, 25, NULL },
 326	{ "m25p32",  0x202016, 0,  64 * 1024,  64, M25P_FLAG, 50, NULL },
 327	{ "m25p64",  0x202017, 0,  64 * 1024, 128, M25P_FLAG, 50, NULL },
 328	{ "m25p128", 0x202018, 0, 256 * 1024,  64, M25P_FLAG, 50, NULL },
 329
 330#define M25PX_FLAG (FLASH_FLAG_READ_WRITE      |	\
 331		    FLASH_FLAG_READ_FAST        |	\
 332		    FLASH_FLAG_READ_1_1_2       |	\
 333		    FLASH_FLAG_WRITE_1_1_2)
 334	{ "m25px32", 0x207116, 0,  64 * 1024,  64, M25PX_FLAG, 75, NULL },
 335	{ "m25px64", 0x207117, 0,  64 * 1024, 128, M25PX_FLAG, 75, NULL },
 336
 337	/* Macronix MX25xxx
 338	 *     - Support for 'FLASH_FLAG_WRITE_1_4_4' is omitted for devices
 339	 *       where operating frequency must be reduced.
 340	 */
 341#define MX25_FLAG (FLASH_FLAG_READ_WRITE       |	\
 342		   FLASH_FLAG_READ_FAST         |	\
 343		   FLASH_FLAG_READ_1_1_2        |	\
 344		   FLASH_FLAG_READ_1_2_2        |	\
 345		   FLASH_FLAG_READ_1_1_4        |	\
 
 346		   FLASH_FLAG_SE_4K             |	\
 347		   FLASH_FLAG_SE_32K)
 348	{ "mx25l3255e",  0xc29e16, 0, 64 * 1024, 64,
 349	  (MX25_FLAG | FLASH_FLAG_WRITE_1_4_4), 86,
 350	  stfsm_mx25_config},
 351	{ "mx25l25635e", 0xc22019, 0, 64*1024, 512,
 352	  (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70,
 353	  stfsm_mx25_config },
 354	{ "mx25l25655e", 0xc22619, 0, 64*1024, 512,
 355	  (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70,
 356	  stfsm_mx25_config},
 357
 358#define N25Q_FLAG (FLASH_FLAG_READ_WRITE       |	\
 359		   FLASH_FLAG_READ_FAST         |	\
 360		   FLASH_FLAG_READ_1_1_2        |	\
 361		   FLASH_FLAG_READ_1_2_2        |	\
 362		   FLASH_FLAG_READ_1_1_4        |	\
 363		   FLASH_FLAG_READ_1_4_4        |	\
 364		   FLASH_FLAG_WRITE_1_1_2       |	\
 365		   FLASH_FLAG_WRITE_1_2_2       |	\
 366		   FLASH_FLAG_WRITE_1_1_4       |	\
 367		   FLASH_FLAG_WRITE_1_4_4)
 368	{ "n25q128", 0x20ba18, 0, 64 * 1024,  256, N25Q_FLAG, 108,
 369	  stfsm_n25q_config },
 370	{ "n25q256", 0x20ba19, 0, 64 * 1024,  512,
 371	  N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config },
 372
 373	/*
 374	 * Spansion S25FLxxxP
 375	 *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
 376	 */
 377#define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE  |	\
 378			FLASH_FLAG_READ_1_1_2   |	\
 379			FLASH_FLAG_READ_1_2_2   |	\
 380			FLASH_FLAG_READ_1_1_4   |	\
 381			FLASH_FLAG_READ_1_4_4   |	\
 382			FLASH_FLAG_WRITE_1_1_4  |	\
 383			FLASH_FLAG_READ_FAST)
 384	{ "s25fl032p",  0x010215, 0x4d00,  64 * 1024,  64, S25FLXXXP_FLAG, 80,
 385	  stfsm_s25fl_config},
 386	{ "s25fl129p0", 0x012018, 0x4d00, 256 * 1024,  64, S25FLXXXP_FLAG, 80,
 387	  stfsm_s25fl_config },
 388	{ "s25fl129p1", 0x012018, 0x4d01,  64 * 1024, 256, S25FLXXXP_FLAG, 80,
 389	  stfsm_s25fl_config },
 390
 391	/*
 392	 * Spansion S25FLxxxS
 393	 *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
 394	 *     - RESET# signal supported by die but not bristled out on all
 395	 *       package types.  The package type is a function of board design,
 396	 *       so this information is captured in the board's flags.
 397	 *     - Supports 'DYB' sector protection. Depending on variant, sectors
 398	 *       may default to locked state on power-on.
 399	 */
 400#define S25FLXXXS_FLAG (S25FLXXXP_FLAG         |	\
 401			FLASH_FLAG_RESET        |	\
 402			FLASH_FLAG_DYB_LOCKING)
 403	{ "s25fl128s0", 0x012018, 0x0300,  256 * 1024, 64, S25FLXXXS_FLAG, 80,
 404	  stfsm_s25fl_config },
 405	{ "s25fl128s1", 0x012018, 0x0301,  64 * 1024, 256, S25FLXXXS_FLAG, 80,
 406	  stfsm_s25fl_config },
 407	{ "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
 408	  S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config },
 409	{ "s25fl256s1", 0x010219, 0x4d01,  64 * 1024, 512,
 410	  S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config },
 411
 412	/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
 413#define W25X_FLAG (FLASH_FLAG_READ_WRITE       |	\
 414		   FLASH_FLAG_READ_FAST         |	\
 415		   FLASH_FLAG_READ_1_1_2        |	\
 416		   FLASH_FLAG_WRITE_1_1_2)
 417	{ "w25x40",  0xef3013, 0,  64 * 1024,   8, W25X_FLAG, 75, NULL },
 418	{ "w25x80",  0xef3014, 0,  64 * 1024,  16, W25X_FLAG, 75, NULL },
 419	{ "w25x16",  0xef3015, 0,  64 * 1024,  32, W25X_FLAG, 75, NULL },
 420	{ "w25x32",  0xef3016, 0,  64 * 1024,  64, W25X_FLAG, 75, NULL },
 421	{ "w25x64",  0xef3017, 0,  64 * 1024, 128, W25X_FLAG, 75, NULL },
 422
 423	/* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
 424#define W25Q_FLAG (FLASH_FLAG_READ_WRITE       |	\
 425		   FLASH_FLAG_READ_FAST         |	\
 426		   FLASH_FLAG_READ_1_1_2        |	\
 427		   FLASH_FLAG_READ_1_2_2        |	\
 428		   FLASH_FLAG_READ_1_1_4        |	\
 429		   FLASH_FLAG_READ_1_4_4        |	\
 430		   FLASH_FLAG_WRITE_1_1_4)
 431	{ "w25q80",  0xef4014, 0,  64 * 1024,  16, W25Q_FLAG, 80,
 432	  stfsm_w25q_config },
 433	{ "w25q16",  0xef4015, 0,  64 * 1024,  32, W25Q_FLAG, 80,
 434	  stfsm_w25q_config },
 435	{ "w25q32",  0xef4016, 0,  64 * 1024,  64, W25Q_FLAG, 80,
 436	  stfsm_w25q_config },
 437	{ "w25q64",  0xef4017, 0,  64 * 1024, 128, W25Q_FLAG, 80,
 438	  stfsm_w25q_config },
 439
 440	/* Sentinel */
 441	{ NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
 442};
 443
 444/*
 445 * FSM message sequence configurations:
 446 *
 447 * All configs are presented in order of preference
 448 */
 449
 450/* Default READ configurations, in order of preference */
 451static struct seq_rw_config default_read_configs[] = {
 452	{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4,	0, 4, 4, 0x00, 2, 4},
 453	{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4,	0, 1, 4, 0x00, 4, 0},
 454	{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2,	0, 2, 2, 0x00, 4, 0},
 455	{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2,	0, 1, 2, 0x00, 0, 8},
 456	{FLASH_FLAG_READ_FAST,	SPINOR_OP_READ_FAST,	0, 1, 1, 0x00, 0, 8},
 457	{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ,		0, 1, 1, 0x00, 0, 0},
 458	{0x00,			0,			0, 0, 0, 0x00, 0, 0},
 459};
 460
 461/* Default WRITE configurations */
 462static struct seq_rw_config default_write_configs[] = {
 463	{FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
 464	{FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
 465	{FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
 466	{FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
 467	{FLASH_FLAG_READ_WRITE,  SPINOR_OP_WRITE,       1, 1, 1, 0x00, 0, 0},
 468	{0x00,			 0,			0, 0, 0, 0x00, 0, 0},
 469};
 470
 471/*
 472 * [N25Qxxx] Configuration
 473 */
 474#define N25Q_VCR_DUMMY_CYCLES(x)	(((x) & 0xf) << 4)
 475#define N25Q_VCR_XIP_DISABLED		((uint8_t)0x1 << 3)
 476#define N25Q_VCR_WRAP_CONT		0x3
 477
 478/* N25Q 3-byte Address READ configurations
 479 *	- 'FAST' variants configured for 8 dummy cycles.
 480 *
 481 * Note, the number of dummy cycles used for 'FAST' READ operations is
 482 * configurable and would normally be tuned according to the READ command and
 483 * operating frequency.  However, this applies universally to all 'FAST' READ
 484 * commands, including those used by the SPIBoot controller, and remains in
 485 * force until the device is power-cycled.  Since the SPIBoot controller is
 486 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8
 487 * cycles.
 488 */
 489static struct seq_rw_config n25q_read3_configs[] = {
 490	{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4,	0, 4, 4, 0x00, 0, 8},
 491	{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4,	0, 1, 4, 0x00, 0, 8},
 492	{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2,	0, 2, 2, 0x00, 0, 8},
 493	{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2,	0, 1, 2, 0x00, 0, 8},
 494	{FLASH_FLAG_READ_FAST,	SPINOR_OP_READ_FAST,	0, 1, 1, 0x00, 0, 8},
 495	{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ,	        0, 1, 1, 0x00, 0, 0},
 496	{0x00,			0,			0, 0, 0, 0x00, 0, 0},
 497};
 498
 499/* N25Q 4-byte Address READ configurations
 500 *	- use special 4-byte address READ commands (reduces overheads, and
 501 *        reduces risk of hitting watchdog reset issues).
 502 *	- 'FAST' variants configured for 8 dummy cycles (see note above.)
 503 */
 504static struct seq_rw_config n25q_read4_configs[] = {
 505	{FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
 506	{FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
 507	{FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
 508	{FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
 509	{FLASH_FLAG_READ_FAST,	SPINOR_OP_READ_FAST_4B,  0, 1, 1, 0x00, 0, 8},
 510	{FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B,       0, 1, 1, 0x00, 0, 0},
 511	{0x00,			0,                       0, 0, 0, 0x00, 0, 0},
 512};
 513
 514/*
 515 * [MX25xxx] Configuration
 516 */
 517#define MX25_STATUS_QE			(0x1 << 6)
 518
 519static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
 520{
 521	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 522			   SEQ_OPC_CYCLES(8) |
 523			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B) |
 524			   SEQ_OPC_CSDEASSERT);
 525
 526	seq->seq[0] = STFSM_INST_CMD1;
 527	seq->seq[1] = STFSM_INST_WAIT;
 528	seq->seq[2] = STFSM_INST_STOP;
 529
 530	seq->seq_cfg = (SEQ_CFG_PADS_1 |
 531			SEQ_CFG_ERASE |
 532			SEQ_CFG_READNOTWRITE |
 533			SEQ_CFG_CSDEASSERT |
 534			SEQ_CFG_STARTSEQ);
 535
 536	return 0;
 537}
 538
 539/*
 540 * [S25FLxxx] Configuration
 541 */
 542#define STFSM_S25FL_CONFIG_QE		(0x1 << 1)
 543
 544/*
 545 * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank
 546 * Register, Extended Address Modes, and a 32-bit address command set.  The
 547 * 32-bit address command set is used here, since it avoids any problems with
 548 * entering a state that is incompatible with the SPIBoot Controller.
 549 */
 550static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
 551	{FLASH_FLAG_READ_1_4_4,  SPINOR_OP_READ_1_4_4_4B,  0, 4, 4, 0x00, 2, 4},
 552	{FLASH_FLAG_READ_1_1_4,  SPINOR_OP_READ_1_1_4_4B,  0, 1, 4, 0x00, 0, 8},
 553	{FLASH_FLAG_READ_1_2_2,  SPINOR_OP_READ_1_2_2_4B,  0, 2, 2, 0x00, 4, 0},
 554	{FLASH_FLAG_READ_1_1_2,  SPINOR_OP_READ_1_1_2_4B,  0, 1, 2, 0x00, 0, 8},
 555	{FLASH_FLAG_READ_FAST,   SPINOR_OP_READ_FAST_4B,   0, 1, 1, 0x00, 0, 8},
 556	{FLASH_FLAG_READ_WRITE,  SPINOR_OP_READ_4B,        0, 1, 1, 0x00, 0, 0},
 557	{0x00,                   0,                        0, 0, 0, 0x00, 0, 0},
 558};
 559
 560static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
 561	{FLASH_FLAG_WRITE_1_1_4, S25FL_CMD_WRITE4_1_1_4, 1, 1, 4, 0x00, 0, 0},
 562	{FLASH_FLAG_READ_WRITE,  S25FL_CMD_WRITE4,       1, 1, 1, 0x00, 0, 0},
 563	{0x00,                   0,                      0, 0, 0, 0x00, 0, 0},
 564};
 565
 566/*
 567 * [W25Qxxx] Configuration
 568 */
 569#define W25Q_STATUS_QE			(0x1 << 1)
 570
 571static struct stfsm_seq stfsm_seq_read_jedec = {
 572	.data_size = TRANSFER_SIZE(8),
 573	.seq_opc[0] = (SEQ_OPC_PADS_1 |
 574		       SEQ_OPC_CYCLES(8) |
 575		       SEQ_OPC_OPCODE(SPINOR_OP_RDID)),
 576	.seq = {
 577		STFSM_INST_CMD1,
 578		STFSM_INST_DATA_READ,
 579		STFSM_INST_STOP,
 580	},
 581	.seq_cfg = (SEQ_CFG_PADS_1 |
 582		    SEQ_CFG_READNOTWRITE |
 583		    SEQ_CFG_CSDEASSERT |
 584		    SEQ_CFG_STARTSEQ),
 585};
 586
 587static struct stfsm_seq stfsm_seq_read_status_fifo = {
 588	.data_size = TRANSFER_SIZE(4),
 589	.seq_opc[0] = (SEQ_OPC_PADS_1 |
 590		       SEQ_OPC_CYCLES(8) |
 591		       SEQ_OPC_OPCODE(SPINOR_OP_RDSR)),
 592	.seq = {
 593		STFSM_INST_CMD1,
 594		STFSM_INST_DATA_READ,
 595		STFSM_INST_STOP,
 596	},
 597	.seq_cfg = (SEQ_CFG_PADS_1 |
 598		    SEQ_CFG_READNOTWRITE |
 599		    SEQ_CFG_CSDEASSERT |
 600		    SEQ_CFG_STARTSEQ),
 601};
 602
 603static struct stfsm_seq stfsm_seq_erase_sector = {
 604	/* 'addr_cfg' configured during initialisation */
 605	.seq_opc = {
 606		(SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 607		 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 608
 609		(SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 610		 SEQ_OPC_OPCODE(SPINOR_OP_SE)),
 611	},
 612	.seq = {
 613		STFSM_INST_CMD1,
 614		STFSM_INST_CMD2,
 615		STFSM_INST_ADD1,
 616		STFSM_INST_ADD2,
 617		STFSM_INST_STOP,
 618	},
 619	.seq_cfg = (SEQ_CFG_PADS_1 |
 620		    SEQ_CFG_READNOTWRITE |
 621		    SEQ_CFG_CSDEASSERT |
 622		    SEQ_CFG_STARTSEQ),
 623};
 624
 625static struct stfsm_seq stfsm_seq_erase_chip = {
 626	.seq_opc = {
 627		(SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 628		 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 629
 630		(SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 631		 SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT),
 632	},
 633	.seq = {
 634		STFSM_INST_CMD1,
 635		STFSM_INST_CMD2,
 636		STFSM_INST_WAIT,
 637		STFSM_INST_STOP,
 638	},
 639	.seq_cfg = (SEQ_CFG_PADS_1 |
 640		    SEQ_CFG_ERASE |
 641		    SEQ_CFG_READNOTWRITE |
 642		    SEQ_CFG_CSDEASSERT |
 643		    SEQ_CFG_STARTSEQ),
 644};
 645
 646static struct stfsm_seq stfsm_seq_write_status = {
 647	.seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 648		       SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 649	.seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 650		       SEQ_OPC_OPCODE(SPINOR_OP_WRSR)),
 651	.seq = {
 652		STFSM_INST_CMD1,
 653		STFSM_INST_CMD2,
 654		STFSM_INST_STA_WR1,
 655		STFSM_INST_STOP,
 656	},
 657	.seq_cfg = (SEQ_CFG_PADS_1 |
 658		    SEQ_CFG_READNOTWRITE |
 659		    SEQ_CFG_CSDEASSERT |
 660		    SEQ_CFG_STARTSEQ),
 661};
 662
 663/* Dummy sequence to read one byte of data from flash into the FIFO */
 664static const struct stfsm_seq stfsm_seq_load_fifo_byte = {
 665	.data_size = TRANSFER_SIZE(1),
 666	.seq_opc[0] = (SEQ_OPC_PADS_1 |
 667		       SEQ_OPC_CYCLES(8) |
 668		       SEQ_OPC_OPCODE(SPINOR_OP_RDID)),
 669	.seq = {
 670		STFSM_INST_CMD1,
 671		STFSM_INST_DATA_READ,
 
 672		STFSM_INST_STOP,
 673	},
 674	.seq_cfg = (SEQ_CFG_PADS_1 |
 675		    SEQ_CFG_READNOTWRITE |
 676		    SEQ_CFG_CSDEASSERT |
 677		    SEQ_CFG_STARTSEQ),
 678};
 679
 680static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
 681{
 682	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 683			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B));
 684	seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 685			   SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
 686			   SEQ_OPC_CSDEASSERT);
 687
 688	seq->seq[0] = STFSM_INST_CMD2;
 689	seq->seq[1] = STFSM_INST_CMD1;
 690	seq->seq[2] = STFSM_INST_WAIT;
 691	seq->seq[3] = STFSM_INST_STOP;
 692
 693	seq->seq_cfg = (SEQ_CFG_PADS_1 |
 694			SEQ_CFG_ERASE |
 695			SEQ_CFG_READNOTWRITE |
 696			SEQ_CFG_CSDEASSERT |
 697			SEQ_CFG_STARTSEQ);
 698
 699	return 0;
 700}
 701
 702static inline int stfsm_is_idle(struct stfsm *fsm)
 703{
 704	return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
 705}
 706
 707static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
 708{
 709	return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
 710}
 711
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 712static inline void stfsm_load_seq(struct stfsm *fsm,
 713				  const struct stfsm_seq *seq)
 714{
 715	void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
 716	const uint32_t *src = (const uint32_t *)seq;
 717	int words = sizeof(*seq) / sizeof(*src);
 718
 719	BUG_ON(!stfsm_is_idle(fsm));
 720
 721	while (words--) {
 722		writel(*src, dst);
 723		src++;
 724		dst += 4;
 725	}
 726}
 727
 728static void stfsm_wait_seq(struct stfsm *fsm)
 729{
 730	unsigned long deadline;
 731	int timeout = 0;
 732
 733	deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
 734
 735	while (!timeout) {
 736		if (time_after_eq(jiffies, deadline))
 737			timeout = 1;
 738
 739		if (stfsm_is_idle(fsm))
 740			return;
 741
 742		cond_resched();
 743	}
 744
 745	dev_err(fsm->dev, "timeout on sequence completion\n");
 746}
 747
 748static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size)
 749{
 750	uint32_t remaining = size >> 2;
 751	uint32_t avail;
 752	uint32_t words;
 753
 754	dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
 755
 756	BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3));
 757
 758	while (remaining) {
 759		for (;;) {
 760			avail = stfsm_fifo_available(fsm);
 761			if (avail)
 762				break;
 763			udelay(1);
 764		}
 765		words = min(avail, remaining);
 766		remaining -= words;
 767
 768		readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
 769		buf += words;
 770	}
 771}
 772
 773/*
 774 * Clear the data FIFO
 775 *
 776 * Typically, this is only required during driver initialisation, where no
 777 * assumptions can be made regarding the state of the FIFO.
 778 *
 779 * The process of clearing the FIFO is complicated by fact that while it is
 780 * possible for the FIFO to contain an arbitrary number of bytes [1], the
 781 * SPI_FAST_SEQ_STA register only reports the number of complete 32-bit words
 782 * present.  Furthermore, data can only be drained from the FIFO by reading
 783 * complete 32-bit words.
 784 *
 785 * With this in mind, a two stage process is used to the clear the FIFO:
 786 *
 787 *     1. Read any complete 32-bit words from the FIFO, as reported by the
 788 *        SPI_FAST_SEQ_STA register.
 789 *
 790 *     2. Mop up any remaining bytes.  At this point, it is not known if there
 791 *        are 0, 1, 2, or 3 bytes in the FIFO.  To handle all cases, a dummy FSM
 792 *        sequence is used to load one byte at a time, until a complete 32-bit
 793 *        word is formed; at most, 4 bytes will need to be loaded.
 794 *
 795 * [1] It is theoretically possible for the FIFO to contain an arbitrary number
 796 *     of bits.  However, since there are no known use-cases that leave
 797 *     incomplete bytes in the FIFO, only words and bytes are considered here.
 798 */
 799static void stfsm_clear_fifo(struct stfsm *fsm)
 800{
 801	const struct stfsm_seq *seq = &stfsm_seq_load_fifo_byte;
 802	uint32_t words, i;
 803
 804	/* 1. Clear any 32-bit words */
 805	words = stfsm_fifo_available(fsm);
 806	if (words) {
 807		for (i = 0; i < words; i++)
 808			readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
 809		dev_dbg(fsm->dev, "cleared %d words from FIFO\n", words);
 810	}
 811
 812	/*
 813	 * 2. Clear any remaining bytes
 814	 *    - Load the FIFO, one byte at a time, until a complete 32-bit word
 815	 *      is available.
 816	 */
 817	for (i = 0, words = 0; i < 4 && !words; i++) {
 818		stfsm_load_seq(fsm, seq);
 819		stfsm_wait_seq(fsm);
 820		words = stfsm_fifo_available(fsm);
 821	}
 822
 823	/*    - A single word must be available now */
 824	if (words != 1) {
 825		dev_err(fsm->dev, "failed to clear bytes from the data FIFO\n");
 826		return;
 827	}
 828
 829	/*    - Read the 32-bit word */
 830	readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
 831
 832	dev_dbg(fsm->dev, "cleared %d byte(s) from the data FIFO\n", 4 - i);
 833}
 834
 835static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf,
 836			    uint32_t size)
 837{
 838	uint32_t words = size >> 2;
 839
 840	dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size);
 841
 842	BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3));
 843
 844	writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
 845
 846	return size;
 847}
 848
 849static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
 850{
 851	struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;
 852	uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
 853
 854	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 855			   SEQ_OPC_CYCLES(8) |
 856			   SEQ_OPC_OPCODE(cmd) |
 857			   SEQ_OPC_CSDEASSERT);
 858
 859	stfsm_load_seq(fsm, seq);
 860
 861	stfsm_wait_seq(fsm);
 862
 863	return 0;
 864}
 865
 866static uint8_t stfsm_wait_busy(struct stfsm *fsm)
 867{
 868	struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;
 869	unsigned long deadline;
 870	uint32_t status;
 871	int timeout = 0;
 872
 873	/* Use RDRS1 */
 874	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 875			   SEQ_OPC_CYCLES(8) |
 876			   SEQ_OPC_OPCODE(SPINOR_OP_RDSR));
 877
 878	/* Load read_status sequence */
 879	stfsm_load_seq(fsm, seq);
 880
 881	/*
 882	 * Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS)
 883	 */
 884	deadline = jiffies + FLASH_MAX_BUSY_WAIT;
 885	while (!timeout) {
 886		if (time_after_eq(jiffies, deadline))
 887			timeout = 1;
 888
 889		stfsm_wait_seq(fsm);
 890
 891		stfsm_read_fifo(fsm, &status, 4);
 892
 893		if ((status & FLASH_STATUS_BUSY) == 0)
 894			return 0;
 895
 896		if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) &&
 897		    ((status & S25FL_STATUS_P_ERR) ||
 898		     (status & S25FL_STATUS_E_ERR)))
 899			return (uint8_t)(status & 0xff);
 900
 901		if (!timeout)
 902			/* Restart */
 903			writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG);
 904
 905		cond_resched();
 906	}
 907
 908	dev_err(fsm->dev, "timeout on wait_busy\n");
 909
 910	return FLASH_STATUS_TIMEOUT;
 911}
 912
 913static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd,
 914			     uint8_t *data, int bytes)
 915{
 916	struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;
 917	uint32_t tmp;
 918	uint8_t *t = (uint8_t *)&tmp;
 919	int i;
 920
 921	dev_dbg(fsm->dev, "read 'status' register [0x%02x], %d byte(s)\n",
 922		cmd, bytes);
 923
 924	BUG_ON(bytes != 1 && bytes != 2);
 925
 926	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 927			   SEQ_OPC_OPCODE(cmd));
 928
 929	stfsm_load_seq(fsm, seq);
 930
 931	stfsm_read_fifo(fsm, &tmp, 4);
 932
 933	for (i = 0; i < bytes; i++)
 934		data[i] = t[i];
 935
 936	stfsm_wait_seq(fsm);
 937
 938	return 0;
 939}
 940
 941static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd,
 942			    uint16_t data, int bytes, int wait_busy)
 943{
 944	struct stfsm_seq *seq = &stfsm_seq_write_status;
 945
 946	dev_dbg(fsm->dev,
 947		"write 'status' register [0x%02x], %d byte(s), 0x%04x\n"
 948		" %s wait-busy\n", cmd, bytes, data, wait_busy ? "with" : "no");
 949
 950	BUG_ON(bytes != 1 && bytes != 2);
 
 
 951
 952	seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 953			   SEQ_OPC_OPCODE(cmd));
 
 
 
 
 
 
 
 
 
 
 954
 955	seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT;
 956	seq->seq[2] = (bytes == 1) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2;
 957
 958	stfsm_load_seq(fsm, seq);
 959
 960	stfsm_wait_seq(fsm);
 961
 962	if (wait_busy)
 963		stfsm_wait_busy(fsm);
 964
 965	return 0;
 966}
 967
 968/*
 969 * SoC reset on 'boot-from-spi' systems
 970 *
 971 * Certain modes of operation cause the Flash device to enter a particular state
 972 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit
 973 * Addr' commands).  On boot-from-spi systems, it is important to consider what
 974 * happens if a warm reset occurs during this period.  The SPIBoot controller
 975 * assumes that Flash device is in its default reset state, 24-bit address mode,
 976 * and ready to accept commands.  This can be achieved using some form of
 977 * on-board logic/controller to force a device POR in response to a SoC-level
 978 * reset or by making use of the device reset signal if available (limited
 979 * number of devices only).
 980 *
 981 * Failure to take such precautions can cause problems following a warm reset.
 982 * For some operations (e.g. ERASE), there is little that can be done.  For
 983 * other modes of operation (e.g. 32-bit addressing), options are often
 984 * available that can help minimise the window in which a reset could cause a
 985 * problem.
 986 *
 987 */
 988static bool stfsm_can_handle_soc_reset(struct stfsm *fsm)
 989{
 990	/* Reset signal is available on the board and supported by the device */
 991	if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)
 992		return true;
 993
 994	/* Board-level logic forces a power-on-reset */
 995	if (fsm->reset_por)
 996		return true;
 997
 998	/* Reset is not properly handled and may result in failure to reboot */
 999	return false;
1000}
1001
1002/* Configure 'addr_cfg' according to addressing mode */
1003static void stfsm_prepare_erasesec_seq(struct stfsm *fsm,
1004				       struct stfsm_seq *seq)
1005{
1006	int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8;
1007
1008	seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) |
1009			 ADR_CFG_PADS_1_ADD1 |
1010			 ADR_CFG_CYCLES_ADD2(16) |
1011			 ADR_CFG_PADS_1_ADD2 |
1012			 ADR_CFG_CSDEASSERT_ADD2);
1013}
1014
1015/* Search for preferred configuration based on available flags */
1016static struct seq_rw_config *
1017stfsm_search_seq_rw_configs(struct stfsm *fsm,
1018			    struct seq_rw_config cfgs[])
1019{
1020	struct seq_rw_config *config;
1021	int flags = fsm->info->flags;
1022
1023	for (config = cfgs; config->cmd != 0; config++)
1024		if ((config->flags & flags) == config->flags)
1025			return config;
1026
1027	return NULL;
1028}
1029
1030/* Prepare a READ/WRITE sequence according to configuration parameters */
1031static void stfsm_prepare_rw_seq(struct stfsm *fsm,
1032				 struct stfsm_seq *seq,
1033				 struct seq_rw_config *cfg)
1034{
1035	int addr1_cycles, addr2_cycles;
1036	int i = 0;
1037
1038	memset(seq, 0, sizeof(*seq));
1039
1040	/* Add READ/WRITE OPC  */
1041	seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
1042			     SEQ_OPC_CYCLES(8) |
1043			     SEQ_OPC_OPCODE(cfg->cmd));
1044
1045	/* Add WREN OPC for a WRITE sequence */
1046	if (cfg->write)
1047		seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
1048				     SEQ_OPC_CYCLES(8) |
1049				     SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
1050				     SEQ_OPC_CSDEASSERT);
1051
1052	/* Address configuration (24 or 32-bit addresses) */
1053	addr1_cycles  = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
1054	addr1_cycles /= cfg->addr_pads;
1055	addr2_cycles  = 16 / cfg->addr_pads;
1056	seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 |	/* ADD1 cycles */
1057			 (cfg->addr_pads - 1) << 6 |	/* ADD1 pads */
1058			 (addr2_cycles & 0x3f) << 16 |	/* ADD2 cycles */
1059			 ((cfg->addr_pads - 1) << 22));	/* ADD2 pads */
1060
1061	/* Data/Sequence configuration */
1062	seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
1063			SEQ_CFG_STARTSEQ |
1064			SEQ_CFG_CSDEASSERT);
1065	if (!cfg->write)
1066		seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
1067
1068	/* Mode configuration (no. of pads taken from addr cfg) */
1069	seq->mode = ((cfg->mode_data & 0xff) << 0 |	/* data */
1070		     (cfg->mode_cycles & 0x3f) << 16 |	/* cycles */
1071		     (cfg->addr_pads - 1) << 22);	/* pads */
1072
1073	/* Dummy configuration (no. of pads taken from addr cfg) */
1074	seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 |	/* cycles */
1075		      (cfg->addr_pads - 1) << 22);		/* pads */
1076
1077
1078	/* Instruction sequence */
1079	i = 0;
1080	if (cfg->write)
1081		seq->seq[i++] = STFSM_INST_CMD2;
1082
1083	seq->seq[i++] = STFSM_INST_CMD1;
1084
1085	seq->seq[i++] = STFSM_INST_ADD1;
1086	seq->seq[i++] = STFSM_INST_ADD2;
1087
1088	if (cfg->mode_cycles)
1089		seq->seq[i++] = STFSM_INST_MODE;
1090
1091	if (cfg->dummy_cycles)
1092		seq->seq[i++] = STFSM_INST_DUMMY;
1093
1094	seq->seq[i++] =
1095		cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
1096	seq->seq[i++] = STFSM_INST_STOP;
1097}
1098
1099static int stfsm_search_prepare_rw_seq(struct stfsm *fsm,
1100				       struct stfsm_seq *seq,
1101				       struct seq_rw_config *cfgs)
1102{
1103	struct seq_rw_config *config;
1104
1105	config = stfsm_search_seq_rw_configs(fsm, cfgs);
1106	if (!config) {
1107		dev_err(fsm->dev, "failed to find suitable config\n");
1108		return -EINVAL;
1109	}
1110
1111	stfsm_prepare_rw_seq(fsm, seq, config);
1112
1113	return 0;
1114}
1115
1116/* Prepare a READ/WRITE/ERASE 'default' sequences */
1117static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)
1118{
1119	uint32_t flags = fsm->info->flags;
1120	int ret;
1121
1122	/* Configure 'READ' sequence */
1123	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1124					  default_read_configs);
1125	if (ret) {
1126		dev_err(fsm->dev,
1127			"failed to prep READ sequence with flags [0x%08x]\n",
1128			flags);
1129		return ret;
1130	}
1131
1132	/* Configure 'WRITE' sequence */
1133	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1134					  default_write_configs);
1135	if (ret) {
1136		dev_err(fsm->dev,
1137			"failed to prep WRITE sequence with flags [0x%08x]\n",
1138			flags);
1139		return ret;
1140	}
1141
1142	/* Configure 'ERASE_SECTOR' sequence */
1143	stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
1144
1145	return 0;
1146}
1147
1148static int stfsm_mx25_config(struct stfsm *fsm)
1149{
1150	uint32_t flags = fsm->info->flags;
1151	uint32_t data_pads;
1152	uint8_t sta;
1153	int ret;
1154	bool soc_reset;
1155
1156	/*
1157	 * Use default READ/WRITE sequences
1158	 */
1159	ret = stfsm_prepare_rwe_seqs_default(fsm);
1160	if (ret)
1161		return ret;
1162
1163	/*
1164	 * Configure 32-bit Address Support
1165	 */
1166	if (flags & FLASH_FLAG_32BIT_ADDR) {
1167		/* Configure 'enter_32bitaddr' FSM sequence */
1168		stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
1169
1170		soc_reset = stfsm_can_handle_soc_reset(fsm);
1171		if (soc_reset || !fsm->booted_from_spi)
1172			/* If we can handle SoC resets, we enable 32-bit address
1173			 * mode pervasively */
1174			stfsm_enter_32bit_addr(fsm, 1);
1175
1176		else
1177			/* Else, enable/disable 32-bit addressing before/after
1178			 * each operation */
1179			fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR |
1180					      CFG_WRITE_TOGGLE_32BIT_ADDR |
1181					      CFG_ERASESEC_TOGGLE_32BIT_ADDR);
 
 
 
 
 
 
1182	}
1183
1184	/* Check status of 'QE' bit, update if required. */
1185	stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1);
1186	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1187	if (data_pads == 4) {
1188		if (!(sta & MX25_STATUS_QE)) {
1189			/* Set 'QE' */
1190			sta |= MX25_STATUS_QE;
1191
1192			stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1193		}
1194	} else {
1195		if (sta & MX25_STATUS_QE) {
1196			/* Clear 'QE' */
1197			sta &= ~MX25_STATUS_QE;
1198
1199			stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1200		}
1201	}
1202
1203	return 0;
1204}
1205
1206static int stfsm_n25q_config(struct stfsm *fsm)
1207{
1208	uint32_t flags = fsm->info->flags;
1209	uint8_t vcr;
1210	int ret = 0;
1211	bool soc_reset;
1212
1213	/* Configure 'READ' sequence */
1214	if (flags & FLASH_FLAG_32BIT_ADDR)
1215		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1216						  n25q_read4_configs);
1217	else
1218		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1219						  n25q_read3_configs);
1220	if (ret) {
1221		dev_err(fsm->dev,
1222			"failed to prepare READ sequence with flags [0x%08x]\n",
1223			flags);
1224		return ret;
1225	}
1226
1227	/* Configure 'WRITE' sequence (default configs) */
1228	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1229					  default_write_configs);
1230	if (ret) {
1231		dev_err(fsm->dev,
1232			"preparing WRITE sequence using flags [0x%08x] failed\n",
1233			flags);
1234		return ret;
1235	}
1236
1237	/* * Configure 'ERASE_SECTOR' sequence */
1238	stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
1239
1240	/* Configure 32-bit address support */
1241	if (flags & FLASH_FLAG_32BIT_ADDR) {
1242		stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
1243
1244		soc_reset = stfsm_can_handle_soc_reset(fsm);
1245		if (soc_reset || !fsm->booted_from_spi) {
1246			/*
1247			 * If we can handle SoC resets, we enable 32-bit
1248			 * address mode pervasively
1249			 */
1250			stfsm_enter_32bit_addr(fsm, 1);
1251		} else {
1252			/*
1253			 * If not, enable/disable for WRITE and ERASE
1254			 * operations (READ uses special commands)
1255			 */
1256			fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR |
1257					      CFG_ERASESEC_TOGGLE_32BIT_ADDR);
1258		}
1259	}
1260
1261	/*
1262	 * Configure device to use 8 dummy cycles
1263	 */
1264	vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED |
1265	       N25Q_VCR_WRAP_CONT);
1266	stfsm_write_status(fsm, N25Q_CMD_WRVCR, vcr, 1, 0);
1267
1268	return 0;
1269}
1270
1271static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq)
1272{
1273	seq->seq_opc[1] = (SEQ_OPC_PADS_1 |
1274			   SEQ_OPC_CYCLES(8) |
1275			   SEQ_OPC_OPCODE(S25FL_CMD_SE4));
1276
1277	seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1278			 ADR_CFG_PADS_1_ADD1 |
1279			 ADR_CFG_CYCLES_ADD2(16) |
1280			 ADR_CFG_PADS_1_ADD2 |
1281			 ADR_CFG_CSDEASSERT_ADD2);
1282}
1283
1284static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby)
1285{
1286	uint32_t tmp;
1287	struct stfsm_seq seq = {
1288		.data_size = TRANSFER_SIZE(4),
1289		.seq_opc[0] = (SEQ_OPC_PADS_1 |
1290			       SEQ_OPC_CYCLES(8) |
1291			       SEQ_OPC_OPCODE(S25FL_CMD_DYBRD)),
1292		.addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1293			     ADR_CFG_PADS_1_ADD1 |
1294			     ADR_CFG_CYCLES_ADD2(16) |
1295			     ADR_CFG_PADS_1_ADD2),
1296		.addr1 = (offs >> 16) & 0xffff,
1297		.addr2 = offs & 0xffff,
1298		.seq = {
1299			STFSM_INST_CMD1,
1300			STFSM_INST_ADD1,
1301			STFSM_INST_ADD2,
1302			STFSM_INST_DATA_READ,
1303			STFSM_INST_STOP,
1304		},
1305		.seq_cfg = (SEQ_CFG_PADS_1 |
1306			    SEQ_CFG_READNOTWRITE |
1307			    SEQ_CFG_CSDEASSERT |
1308			    SEQ_CFG_STARTSEQ),
1309	};
1310
1311	stfsm_load_seq(fsm, &seq);
1312
1313	stfsm_read_fifo(fsm, &tmp, 4);
1314
1315	*dby = (uint8_t)(tmp >> 24);
1316
1317	stfsm_wait_seq(fsm);
1318}
1319
1320static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby)
1321{
1322	struct stfsm_seq seq = {
1323		.seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1324			       SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
1325			       SEQ_OPC_CSDEASSERT),
1326		.seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1327			       SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)),
1328		.addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1329			     ADR_CFG_PADS_1_ADD1 |
1330			     ADR_CFG_CYCLES_ADD2(16) |
1331			     ADR_CFG_PADS_1_ADD2),
1332		.status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT,
1333		.addr1 = (offs >> 16) & 0xffff,
1334		.addr2 = offs & 0xffff,
1335		.seq = {
1336			STFSM_INST_CMD1,
1337			STFSM_INST_CMD2,
1338			STFSM_INST_ADD1,
1339			STFSM_INST_ADD2,
1340			STFSM_INST_STA_WR1,
1341			STFSM_INST_STOP,
1342		},
1343		.seq_cfg = (SEQ_CFG_PADS_1 |
1344			    SEQ_CFG_READNOTWRITE |
1345			    SEQ_CFG_CSDEASSERT |
1346			    SEQ_CFG_STARTSEQ),
1347	};
1348
1349	stfsm_load_seq(fsm, &seq);
1350	stfsm_wait_seq(fsm);
1351
1352	stfsm_wait_busy(fsm);
1353}
1354
1355static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm)
1356{
1357	struct stfsm_seq seq = {
1358		.seq_opc[0] = (SEQ_OPC_PADS_1 |
1359			       SEQ_OPC_CYCLES(8) |
1360			       SEQ_OPC_OPCODE(S25FL_CMD_CLSR) |
1361			       SEQ_OPC_CSDEASSERT),
1362		.seq_opc[1] = (SEQ_OPC_PADS_1 |
1363			       SEQ_OPC_CYCLES(8) |
1364			       SEQ_OPC_OPCODE(SPINOR_OP_WRDI) |
1365			       SEQ_OPC_CSDEASSERT),
1366		.seq = {
1367			STFSM_INST_CMD1,
1368			STFSM_INST_CMD2,
1369			STFSM_INST_WAIT,
1370			STFSM_INST_STOP,
1371		},
1372		.seq_cfg = (SEQ_CFG_PADS_1 |
1373			    SEQ_CFG_ERASE |
1374			    SEQ_CFG_READNOTWRITE |
1375			    SEQ_CFG_CSDEASSERT |
1376			    SEQ_CFG_STARTSEQ),
1377	};
1378
1379	stfsm_load_seq(fsm, &seq);
1380
1381	stfsm_wait_seq(fsm);
1382
1383	return 0;
1384}
1385
1386static int stfsm_s25fl_config(struct stfsm *fsm)
1387{
1388	struct flash_info *info = fsm->info;
1389	uint32_t flags = info->flags;
1390	uint32_t data_pads;
1391	uint32_t offs;
1392	uint16_t sta_wr;
1393	uint8_t sr1, cr1, dyb;
1394	int update_sr = 0;
1395	int ret;
1396
1397	if (flags & FLASH_FLAG_32BIT_ADDR) {
1398		/*
1399		 * Prepare Read/Write/Erase sequences according to S25FLxxx
1400		 * 32-bit address command set
1401		 */
1402		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1403						  stfsm_s25fl_read4_configs);
1404		if (ret)
1405			return ret;
1406
1407		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1408						  stfsm_s25fl_write4_configs);
1409		if (ret)
1410			return ret;
1411
1412		stfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector);
1413
1414	} else {
1415		/* Use default configurations for 24-bit addressing */
1416		ret = stfsm_prepare_rwe_seqs_default(fsm);
1417		if (ret)
1418			return ret;
1419	}
1420
1421	/*
1422	 * For devices that support 'DYB' sector locking, check lock status and
1423	 * unlock sectors if necessary (some variants power-on with sectors
1424	 * locked by default)
1425	 */
1426	if (flags & FLASH_FLAG_DYB_LOCKING) {
1427		offs = 0;
1428		for (offs = 0; offs < info->sector_size * info->n_sectors;) {
1429			stfsm_s25fl_read_dyb(fsm, offs, &dyb);
1430			if (dyb == 0x00)
1431				stfsm_s25fl_write_dyb(fsm, offs, 0xff);
1432
1433			/* Handle bottom/top 4KiB parameter sectors */
1434			if ((offs < info->sector_size * 2) ||
1435			    (offs >= (info->sector_size - info->n_sectors * 4)))
1436				offs += 0x1000;
1437			else
1438				offs += 0x10000;
1439		}
1440	}
1441
1442	/* Check status of 'QE' bit, update if required. */
1443	stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1);
1444	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
 
1445	if (data_pads == 4) {
1446		if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {
1447			/* Set 'QE' */
1448			cr1 |= STFSM_S25FL_CONFIG_QE;
1449
1450			update_sr = 1;
 
 
 
 
 
1451		}
1452	} else {
1453		if (cr1 & STFSM_S25FL_CONFIG_QE) {
1454			/* Clear 'QE' */
1455			cr1 &= ~STFSM_S25FL_CONFIG_QE;
1456
1457			update_sr = 1;
 
 
 
 
 
1458		}
1459	}
1460	if (update_sr) {
1461		stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1462		sta_wr = ((uint16_t)cr1  << 8) | sr1;
1463		stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1);
1464	}
1465
1466	/*
1467	 * S25FLxxx devices support Program and Error error flags.
1468	 * Configure driver to check flags and clear if necessary.
1469	 */
1470	fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS;
1471
1472	return 0;
1473}
1474
1475static int stfsm_w25q_config(struct stfsm *fsm)
1476{
1477	uint32_t data_pads;
1478	uint8_t sr1, sr2;
1479	uint16_t sr_wr;
1480	int update_sr = 0;
1481	int ret;
1482
1483	ret = stfsm_prepare_rwe_seqs_default(fsm);
1484	if (ret)
1485		return ret;
1486
1487	/* Check status of 'QE' bit, update if required. */
1488	stfsm_read_status(fsm, SPINOR_OP_RDCR, &sr2, 1);
1489	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1490	if (data_pads == 4) {
1491		if (!(sr2 & W25Q_STATUS_QE)) {
1492			/* Set 'QE' */
1493			sr2 |= W25Q_STATUS_QE;
1494			update_sr = 1;
1495		}
1496	} else {
1497		if (sr2 & W25Q_STATUS_QE) {
1498			/* Clear 'QE' */
1499			sr2 &= ~W25Q_STATUS_QE;
1500			update_sr = 1;
1501		}
1502	}
1503	if (update_sr) {
1504		/* Write status register */
1505		stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1506		sr_wr = ((uint16_t)sr2 << 8) | sr1;
1507		stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1);
1508	}
1509
1510	return 0;
1511}
1512
1513static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
1514		      uint32_t offset)
1515{
1516	struct stfsm_seq *seq = &fsm->stfsm_seq_read;
1517	uint32_t data_pads;
1518	uint32_t read_mask;
1519	uint32_t size_ub;
1520	uint32_t size_lb;
1521	uint32_t size_mop;
1522	uint32_t tmp[4];
1523	uint32_t page_buf[FLASH_PAGESIZE_32];
1524	uint8_t *p;
1525
1526	dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset);
1527
1528	/* Enter 32-bit address mode, if required */
1529	if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
1530		stfsm_enter_32bit_addr(fsm, 1);
1531
1532	/* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */
1533	data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
1534	read_mask = (data_pads << 2) - 1;
1535
1536	/* Handle non-aligned buf */
1537	p = ((uintptr_t)buf & 0x3) ? (uint8_t *)page_buf : buf;
1538
1539	/* Handle non-aligned size */
1540	size_ub = (size + read_mask) & ~read_mask;
1541	size_lb = size & ~read_mask;
1542	size_mop = size & read_mask;
1543
1544	seq->data_size = TRANSFER_SIZE(size_ub);
1545	seq->addr1 = (offset >> 16) & 0xffff;
1546	seq->addr2 = offset & 0xffff;
1547
1548	stfsm_load_seq(fsm, seq);
1549
1550	if (size_lb)
1551		stfsm_read_fifo(fsm, (uint32_t *)p, size_lb);
1552
1553	if (size_mop) {
1554		stfsm_read_fifo(fsm, tmp, read_mask + 1);
1555		memcpy(p + size_lb, &tmp, size_mop);
1556	}
1557
1558	/* Handle non-aligned buf */
1559	if ((uintptr_t)buf & 0x3)
1560		memcpy(buf, page_buf, size);
1561
1562	/* Wait for sequence to finish */
1563	stfsm_wait_seq(fsm);
1564
1565	stfsm_clear_fifo(fsm);
1566
1567	/* Exit 32-bit address mode, if required */
1568	if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
1569		stfsm_enter_32bit_addr(fsm, 0);
1570
1571	return 0;
1572}
1573
1574static int stfsm_write(struct stfsm *fsm, const uint8_t *buf,
1575		       uint32_t size, uint32_t offset)
1576{
1577	struct stfsm_seq *seq = &fsm->stfsm_seq_write;
1578	uint32_t data_pads;
1579	uint32_t write_mask;
1580	uint32_t size_ub;
1581	uint32_t size_lb;
1582	uint32_t size_mop;
1583	uint32_t tmp[4];
1584	uint32_t i;
1585	uint32_t page_buf[FLASH_PAGESIZE_32];
1586	uint8_t *t = (uint8_t *)&tmp;
1587	const uint8_t *p;
1588	int ret;
 
1589
1590	dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset);
1591
1592	/* Enter 32-bit address mode, if required */
1593	if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)
1594		stfsm_enter_32bit_addr(fsm, 1);
1595
1596	/* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */
1597	data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
1598	write_mask = (data_pads << 2) - 1;
1599
1600	/* Handle non-aligned buf */
1601	if ((uintptr_t)buf & 0x3) {
1602		memcpy(page_buf, buf, size);
1603		p = (uint8_t *)page_buf;
1604	} else {
1605		p = buf;
1606	}
1607
1608	/* Handle non-aligned size */
1609	size_ub = (size + write_mask) & ~write_mask;
1610	size_lb = size & ~write_mask;
1611	size_mop = size & write_mask;
1612
1613	seq->data_size = TRANSFER_SIZE(size_ub);
1614	seq->addr1 = (offset >> 16) & 0xffff;
1615	seq->addr2 = offset & 0xffff;
1616
1617	/* Need to set FIFO to write mode, before writing data to FIFO (see
1618	 * GNBvb79594)
1619	 */
1620	writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG);
1621
1622	/*
1623	 * Before writing data to the FIFO, apply a small delay to allow a
1624	 * potential change of FIFO direction to complete.
1625	 */
1626	if (fsm->fifo_dir_delay == 0)
1627		readl(fsm->base + SPI_FAST_SEQ_CFG);
1628	else
1629		udelay(fsm->fifo_dir_delay);
1630
1631
1632	/* Write data to FIFO, before starting sequence (see GNBvd79593) */
1633	if (size_lb) {
1634		stfsm_write_fifo(fsm, (uint32_t *)p, size_lb);
1635		p += size_lb;
1636	}
1637
1638	/* Handle non-aligned size */
1639	if (size_mop) {
1640		memset(t, 0xff, write_mask + 1);	/* fill with 0xff's */
1641		for (i = 0; i < size_mop; i++)
1642			t[i] = *p++;
1643
1644		stfsm_write_fifo(fsm, tmp, write_mask + 1);
1645	}
1646
1647	/* Start sequence */
1648	stfsm_load_seq(fsm, seq);
1649
1650	/* Wait for sequence to finish */
1651	stfsm_wait_seq(fsm);
1652
1653	/* Wait for completion */
1654	ret = stfsm_wait_busy(fsm);
1655	if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)
1656		stfsm_s25fl_clear_status_reg(fsm);
1657
1658	/* Exit 32-bit address mode, if required */
1659	if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)
1660		stfsm_enter_32bit_addr(fsm, 0);
 
 
 
1661
1662	return 0;
1663}
1664
1665/*
1666 * Read an address range from the flash chip. The address range
1667 * may be any size provided it is within the physical boundaries.
1668 */
1669static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
1670			  size_t *retlen, u_char *buf)
1671{
1672	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1673	uint32_t bytes;
1674
1675	dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n",
1676		__func__, (u32)from, len);
1677
1678	mutex_lock(&fsm->lock);
1679
1680	while (len > 0) {
1681		bytes = min_t(size_t, len, FLASH_PAGESIZE);
1682
1683		stfsm_read(fsm, buf, bytes, from);
1684
1685		buf += bytes;
1686		from += bytes;
1687		len -= bytes;
1688
1689		*retlen += bytes;
1690	}
1691
1692	mutex_unlock(&fsm->lock);
1693
1694	return 0;
1695}
1696
1697static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset)
1698{
1699	struct stfsm_seq *seq = &stfsm_seq_erase_sector;
1700	int ret;
1701
1702	dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset);
1703
1704	/* Enter 32-bit address mode, if required */
1705	if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)
1706		stfsm_enter_32bit_addr(fsm, 1);
1707
1708	seq->addr1 = (offset >> 16) & 0xffff;
1709	seq->addr2 = offset & 0xffff;
1710
1711	stfsm_load_seq(fsm, seq);
1712
1713	stfsm_wait_seq(fsm);
1714
1715	/* Wait for completion */
1716	ret = stfsm_wait_busy(fsm);
1717	if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)
1718		stfsm_s25fl_clear_status_reg(fsm);
1719
1720	/* Exit 32-bit address mode, if required */
1721	if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)
1722		stfsm_enter_32bit_addr(fsm, 0);
1723
1724	return ret;
1725}
1726
1727static int stfsm_erase_chip(struct stfsm *fsm)
1728{
1729	const struct stfsm_seq *seq = &stfsm_seq_erase_chip;
1730
1731	dev_dbg(fsm->dev, "erasing chip\n");
1732
1733	stfsm_load_seq(fsm, seq);
1734
1735	stfsm_wait_seq(fsm);
1736
1737	return stfsm_wait_busy(fsm);
1738}
1739
1740/*
1741 * Write an address range to the flash chip.  Data must be written in
1742 * FLASH_PAGESIZE chunks.  The address range may be any size provided
1743 * it is within the physical boundaries.
1744 */
1745static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
1746			   size_t *retlen, const u_char *buf)
1747{
1748	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1749
1750	u32 page_offs;
1751	u32 bytes;
1752	uint8_t *b = (uint8_t *)buf;
1753	int ret = 0;
1754
1755	dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len);
1756
1757	/* Offset within page */
1758	page_offs = to % FLASH_PAGESIZE;
1759
1760	mutex_lock(&fsm->lock);
1761
1762	while (len) {
1763		/* Write up to page boundary */
1764		bytes = min_t(size_t, FLASH_PAGESIZE - page_offs, len);
1765
1766		ret = stfsm_write(fsm, b, bytes, to);
1767		if (ret)
1768			goto out1;
1769
1770		b += bytes;
1771		len -= bytes;
1772		to += bytes;
1773
1774		/* We are now page-aligned */
1775		page_offs = 0;
1776
1777		*retlen += bytes;
1778
1779	}
1780
1781out1:
1782	mutex_unlock(&fsm->lock);
1783
1784	return ret;
1785}
1786
1787/*
1788 * Erase an address range on the flash chip. The address range may extend
1789 * one or more erase sectors.  Return an error is there is a problem erasing.
1790 */
1791static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
1792{
1793	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1794	u32 addr, len;
1795	int ret;
1796
1797	dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__,
1798		(long long)instr->addr, (long long)instr->len);
1799
1800	addr = instr->addr;
1801	len = instr->len;
1802
1803	mutex_lock(&fsm->lock);
1804
1805	/* Whole-chip erase? */
1806	if (len == mtd->size) {
1807		ret = stfsm_erase_chip(fsm);
1808		if (ret)
1809			goto out1;
1810	} else {
1811		while (len) {
1812			ret = stfsm_erase_sector(fsm, addr);
1813			if (ret)
1814				goto out1;
1815
1816			addr += mtd->erasesize;
1817			len -= mtd->erasesize;
1818		}
1819	}
1820
1821	mutex_unlock(&fsm->lock);
1822
 
 
 
1823	return 0;
1824
1825out1:
 
1826	mutex_unlock(&fsm->lock);
1827
1828	return ret;
1829}
1830
1831static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec)
1832{
1833	const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
1834	uint32_t tmp[2];
1835
1836	stfsm_load_seq(fsm, seq);
1837
1838	stfsm_read_fifo(fsm, tmp, 8);
1839
1840	memcpy(jedec, tmp, 5);
1841
1842	stfsm_wait_seq(fsm);
1843}
1844
1845static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
1846{
1847	struct flash_info	*info;
1848	u16                     ext_jedec;
1849	u32			jedec;
1850	u8			id[5];
1851
1852	stfsm_read_jedec(fsm, id);
1853
1854	jedec     = id[0] << 16 | id[1] << 8 | id[2];
1855	/*
1856	 * JEDEC also defines an optional "extended device information"
1857	 * string for after vendor-specific data, after the three bytes
1858	 * we use here. Supporting some chips might require using it.
1859	 */
1860	ext_jedec = id[3] << 8  | id[4];
1861
1862	dev_dbg(fsm->dev, "JEDEC =  0x%08x [%5ph]\n", jedec, id);
 
1863
1864	for (info = flash_types; info->name; info++) {
1865		if (info->jedec_id == jedec) {
1866			if (info->ext_id && info->ext_id != ext_jedec)
1867				continue;
1868			return info;
1869		}
1870	}
1871	dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
1872
1873	return NULL;
1874}
1875
1876static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
1877{
1878	int ret, timeout = 10;
1879
1880	/* Wait for controller to accept mode change */
1881	while (--timeout) {
1882		ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
1883		if (ret & 0x1)
1884			break;
1885		udelay(1);
1886	}
1887
1888	if (!timeout)
1889		return -EBUSY;
1890
1891	writel(mode, fsm->base + SPI_MODESELECT);
1892
1893	return 0;
1894}
1895
1896static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
1897{
1898	uint32_t emi_freq;
1899	uint32_t clk_div;
1900
1901	emi_freq = clk_get_rate(fsm->clk);
 
1902
1903	/*
1904	 * Calculate clk_div - values between 2 and 128
1905	 * Multiple of 2, rounded up
1906	 */
1907	clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
1908	if (clk_div < 2)
1909		clk_div = 2;
1910	else if (clk_div > 128)
1911		clk_div = 128;
1912
1913	/*
1914	 * Determine a suitable delay for the IP to complete a change of
1915	 * direction of the FIFO. The required delay is related to the clock
1916	 * divider used. The following heuristics are based on empirical tests,
1917	 * using a 100MHz EMI clock.
1918	 */
1919	if (clk_div <= 4)
1920		fsm->fifo_dir_delay = 0;
1921	else if (clk_div <= 10)
1922		fsm->fifo_dir_delay = 1;
1923	else
1924		fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
1925
1926	dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
1927		emi_freq, spi_freq, clk_div);
1928
1929	writel(clk_div, fsm->base + SPI_CLOCKDIV);
1930}
1931
1932static int stfsm_init(struct stfsm *fsm)
1933{
1934	int ret;
1935
1936	/* Perform a soft reset of the FSM controller */
1937	writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
1938	udelay(1);
1939	writel(0, fsm->base + SPI_FAST_SEQ_CFG);
1940
1941	/* Set clock to 'safe' frequency initially */
1942	stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
1943
1944	/* Switch to FSM */
1945	ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
1946	if (ret)
1947		return ret;
1948
1949	/* Set timing parameters */
1950	writel(SPI_CFG_DEVICE_ST            |
1951	       SPI_CFG_DEFAULT_MIN_CS_HIGH  |
1952	       SPI_CFG_DEFAULT_CS_SETUPHOLD |
1953	       SPI_CFG_DEFAULT_DATA_HOLD,
1954	       fsm->base + SPI_CONFIGDATA);
1955	writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
1956
1957	/*
1958	 * Set the FSM 'WAIT' delay to the minimum workable value.  Note, for
1959	 * our purposes, the WAIT instruction is used purely to achieve
1960	 * "sequence validity" rather than actually implement a delay.
1961	 */
1962	writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME);
1963
1964	/* Clear FIFO, just in case */
1965	stfsm_clear_fifo(fsm);
1966
1967	return 0;
1968}
1969
1970static void stfsm_fetch_platform_configs(struct platform_device *pdev)
1971{
1972	struct stfsm *fsm = platform_get_drvdata(pdev);
1973	struct device_node *np = pdev->dev.of_node;
1974	struct regmap *regmap;
1975	uint32_t boot_device_reg;
1976	uint32_t boot_device_spi;
1977	uint32_t boot_device;     /* Value we read from *boot_device_reg */
1978	int ret;
1979
1980	/* Booting from SPI NOR Flash is the default */
1981	fsm->booted_from_spi = true;
1982
1983	regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1984	if (IS_ERR(regmap))
1985		goto boot_device_fail;
1986
1987	fsm->reset_signal = of_property_read_bool(np, "st,reset-signal");
1988
1989	fsm->reset_por = of_property_read_bool(np, "st,reset-por");
1990
1991	/* Where in the syscon the boot device information lives */
1992	ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg);
1993	if (ret)
1994		goto boot_device_fail;
1995
1996	/* Boot device value when booted from SPI NOR */
1997	ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi);
1998	if (ret)
1999		goto boot_device_fail;
2000
2001	ret = regmap_read(regmap, boot_device_reg, &boot_device);
2002	if (ret)
2003		goto boot_device_fail;
2004
2005	if (boot_device != boot_device_spi)
2006		fsm->booted_from_spi = false;
2007
2008	return;
2009
2010boot_device_fail:
2011	dev_warn(&pdev->dev,
2012		 "failed to fetch boot device, assuming boot from SPI\n");
2013}
2014
2015static int stfsm_probe(struct platform_device *pdev)
2016{
2017	struct device_node *np = pdev->dev.of_node;
 
2018	struct flash_info *info;
 
2019	struct stfsm *fsm;
2020	int ret;
2021
2022	if (!np) {
2023		dev_err(&pdev->dev, "No DT found\n");
2024		return -EINVAL;
2025	}
 
2026
2027	fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
2028	if (!fsm)
2029		return -ENOMEM;
2030
2031	fsm->dev = &pdev->dev;
2032
2033	platform_set_drvdata(pdev, fsm);
2034
2035	fsm->base = devm_platform_ioremap_resource(pdev, 0);
2036	if (IS_ERR(fsm->base))
2037		return PTR_ERR(fsm->base);
 
 
2038
2039	fsm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2040	if (IS_ERR(fsm->clk)) {
2041		dev_err(fsm->dev, "Couldn't find EMI clock.\n");
2042		return PTR_ERR(fsm->clk);
 
2043	}
2044
2045	mutex_init(&fsm->lock);
2046
2047	ret = stfsm_init(fsm);
2048	if (ret) {
2049		dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
2050		return ret;
2051	}
2052
2053	stfsm_fetch_platform_configs(pdev);
2054
2055	/* Detect SPI FLASH device */
2056	info = stfsm_jedec_probe(fsm);
2057	if (!info)
2058		return -ENODEV;
2059	fsm->info = info;
2060
2061	/* Use device size to determine address width */
2062	if (info->sector_size * info->n_sectors > 0x1000000)
2063		info->flags |= FLASH_FLAG_32BIT_ADDR;
2064
2065	/*
2066	 * Configure READ/WRITE/ERASE sequences according to platform and
2067	 * device flags.
2068	 */
2069	if (info->config)
2070		ret = info->config(fsm);
2071	else
 
 
2072		ret = stfsm_prepare_rwe_seqs_default(fsm);
2073	if (ret)
2074		return ret;
 
2075
2076	fsm->mtd.name		= info->name;
2077	fsm->mtd.dev.parent	= &pdev->dev;
2078	mtd_set_of_node(&fsm->mtd, np);
2079	fsm->mtd.type		= MTD_NORFLASH;
2080	fsm->mtd.writesize	= 4;
2081	fsm->mtd.writebufsize	= fsm->mtd.writesize;
2082	fsm->mtd.flags		= MTD_CAP_NORFLASH;
2083	fsm->mtd.size		= info->sector_size * info->n_sectors;
2084	fsm->mtd.erasesize	= info->sector_size;
2085
2086	fsm->mtd._read  = stfsm_mtd_read;
2087	fsm->mtd._write = stfsm_mtd_write;
2088	fsm->mtd._erase = stfsm_mtd_erase;
2089
2090	dev_info(&pdev->dev,
2091		"Found serial flash device: %s\n"
2092		" size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
2093		info->name,
2094		(long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
2095		fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
2096
2097	return mtd_device_register(&fsm->mtd, NULL, 0);
2098}
2099
2100static void stfsm_remove(struct platform_device *pdev)
2101{
2102	struct stfsm *fsm = platform_get_drvdata(pdev);
2103
2104	WARN_ON(mtd_device_unregister(&fsm->mtd));
2105}
2106
2107#ifdef CONFIG_PM_SLEEP
2108static int stfsmfsm_suspend(struct device *dev)
2109{
2110	struct stfsm *fsm = dev_get_drvdata(dev);
2111
2112	clk_disable_unprepare(fsm->clk);
2113
2114	return 0;
2115}
2116
2117static int stfsmfsm_resume(struct device *dev)
2118{
2119	struct stfsm *fsm = dev_get_drvdata(dev);
2120
2121	return clk_prepare_enable(fsm->clk);
2122}
2123#endif
2124
2125static SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume);
2126
2127static const struct of_device_id stfsm_match[] = {
2128	{ .compatible = "st,spi-fsm", },
2129	{},
2130};
2131MODULE_DEVICE_TABLE(of, stfsm_match);
2132
2133static struct platform_driver stfsm_driver = {
2134	.probe		= stfsm_probe,
2135	.remove_new	= stfsm_remove,
2136	.driver		= {
2137		.name	= "st-spi-fsm",
 
2138		.of_match_table = stfsm_match,
2139		.pm     = &stfsm_pm_ops,
2140	},
2141};
2142module_platform_driver(stfsm_driver);
2143
2144MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
2145MODULE_DESCRIPTION("ST SPI FSM driver");
2146MODULE_LICENSE("GPL");