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1/*
2 * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/i2c.h>
31#include <linux/interrupt.h>
32#include <linux/completion.h>
33#include <linux/mutex.h>
34#include <linux/delay.h>
35#include <linux/io.h>
36
37#define DRV_NAME "pmcmsptwi"
38
39#define MSP_TWI_SF_CLK_REG_OFFSET 0x00
40#define MSP_TWI_HS_CLK_REG_OFFSET 0x04
41#define MSP_TWI_CFG_REG_OFFSET 0x08
42#define MSP_TWI_CMD_REG_OFFSET 0x0c
43#define MSP_TWI_ADD_REG_OFFSET 0x10
44#define MSP_TWI_DAT_0_REG_OFFSET 0x14
45#define MSP_TWI_DAT_1_REG_OFFSET 0x18
46#define MSP_TWI_INT_STS_REG_OFFSET 0x1c
47#define MSP_TWI_INT_MSK_REG_OFFSET 0x20
48#define MSP_TWI_BUSY_REG_OFFSET 0x24
49
50#define MSP_TWI_INT_STS_DONE (1 << 0)
51#define MSP_TWI_INT_STS_LOST_ARBITRATION (1 << 1)
52#define MSP_TWI_INT_STS_NO_RESPONSE (1 << 2)
53#define MSP_TWI_INT_STS_DATA_COLLISION (1 << 3)
54#define MSP_TWI_INT_STS_BUSY (1 << 4)
55#define MSP_TWI_INT_STS_ALL 0x1f
56
57#define MSP_MAX_BYTES_PER_RW 8
58#define MSP_MAX_POLL 5
59#define MSP_POLL_DELAY 10
60#define MSP_IRQ_TIMEOUT (MSP_MAX_POLL * MSP_POLL_DELAY)
61
62/* IO Operation macros */
63#define pmcmsptwi_readl __raw_readl
64#define pmcmsptwi_writel __raw_writel
65
66/* TWI command type */
67enum pmcmsptwi_cmd_type {
68 MSP_TWI_CMD_WRITE = 0, /* Write only */
69 MSP_TWI_CMD_READ = 1, /* Read only */
70 MSP_TWI_CMD_WRITE_READ = 2, /* Write then Read */
71};
72
73/* The possible results of the xferCmd */
74enum pmcmsptwi_xfer_result {
75 MSP_TWI_XFER_OK = 0,
76 MSP_TWI_XFER_TIMEOUT,
77 MSP_TWI_XFER_BUSY,
78 MSP_TWI_XFER_DATA_COLLISION,
79 MSP_TWI_XFER_NO_RESPONSE,
80 MSP_TWI_XFER_LOST_ARBITRATION,
81};
82
83/* Corresponds to a PMCTWI clock configuration register */
84struct pmcmsptwi_clock {
85 u8 filter; /* Bits 15:12, default = 0x03 */
86 u16 clock; /* Bits 9:0, default = 0x001f */
87};
88
89struct pmcmsptwi_clockcfg {
90 struct pmcmsptwi_clock standard; /* The standard/fast clock config */
91 struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
92};
93
94/* Corresponds to the main TWI configuration register */
95struct pmcmsptwi_cfg {
96 u8 arbf; /* Bits 15:12, default=0x03 */
97 u8 nak; /* Bits 11:8, default=0x03 */
98 u8 add10; /* Bit 7, default=0x00 */
99 u8 mst_code; /* Bits 6:4, default=0x00 */
100 u8 arb; /* Bit 1, default=0x01 */
101 u8 highspeed; /* Bit 0, default=0x00 */
102};
103
104/* A single pmctwi command to issue */
105struct pmcmsptwi_cmd {
106 u16 addr; /* The slave address (7 or 10 bits) */
107 enum pmcmsptwi_cmd_type type; /* The command type */
108 u8 write_len; /* Number of bytes in the write buffer */
109 u8 read_len; /* Number of bytes in the read buffer */
110 u8 *write_data; /* Buffer of characters to send */
111 u8 *read_data; /* Buffer to fill with incoming data */
112};
113
114/* The private data */
115struct pmcmsptwi_data {
116 void __iomem *iobase; /* iomapped base for IO */
117 int irq; /* IRQ to use (0 disables) */
118 struct completion wait; /* Completion for xfer */
119 struct mutex lock; /* Used for threadsafeness */
120 enum pmcmsptwi_xfer_result last_result; /* result of last xfer */
121};
122
123/* The default settings */
124static const struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
125 .standard = {
126 .filter = 0x3,
127 .clock = 0x1f,
128 },
129 .highspeed = {
130 .filter = 0x3,
131 .clock = 0x1f,
132 },
133};
134
135static const struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
136 .arbf = 0x03,
137 .nak = 0x03,
138 .add10 = 0x00,
139 .mst_code = 0x00,
140 .arb = 0x01,
141 .highspeed = 0x00,
142};
143
144static struct pmcmsptwi_data pmcmsptwi_data;
145
146static struct i2c_adapter pmcmsptwi_adapter;
147
148/* inline helper functions */
149static inline u32 pmcmsptwi_clock_to_reg(
150 const struct pmcmsptwi_clock *clock)
151{
152 return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
153}
154
155static inline void pmcmsptwi_reg_to_clock(
156 u32 reg, struct pmcmsptwi_clock *clock)
157{
158 clock->filter = (reg >> 12) & 0xf;
159 clock->clock = reg & 0x03ff;
160}
161
162static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
163{
164 return ((cfg->arbf & 0xf) << 12) |
165 ((cfg->nak & 0xf) << 8) |
166 ((cfg->add10 & 0x1) << 7) |
167 ((cfg->mst_code & 0x7) << 4) |
168 ((cfg->arb & 0x1) << 1) |
169 (cfg->highspeed & 0x1);
170}
171
172static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
173{
174 cfg->arbf = (reg >> 12) & 0xf;
175 cfg->nak = (reg >> 8) & 0xf;
176 cfg->add10 = (reg >> 7) & 0x1;
177 cfg->mst_code = (reg >> 4) & 0x7;
178 cfg->arb = (reg >> 1) & 0x1;
179 cfg->highspeed = reg & 0x1;
180}
181
182/*
183 * Sets the current clock configuration
184 */
185static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
186 struct pmcmsptwi_data *data)
187{
188 mutex_lock(&data->lock);
189 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
190 data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
191 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
192 data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
193 mutex_unlock(&data->lock);
194}
195
196/*
197 * Gets the current TWI bus configuration
198 */
199static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
200 struct pmcmsptwi_data *data)
201{
202 mutex_lock(&data->lock);
203 pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
204 data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
205 mutex_unlock(&data->lock);
206}
207
208/*
209 * Sets the current TWI bus configuration
210 */
211static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
212 struct pmcmsptwi_data *data)
213{
214 mutex_lock(&data->lock);
215 pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
216 data->iobase + MSP_TWI_CFG_REG_OFFSET);
217 mutex_unlock(&data->lock);
218}
219
220/*
221 * Parses the 'int_sts' register and returns a well-defined error code
222 */
223static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
224{
225 if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
226 dev_dbg(&pmcmsptwi_adapter.dev,
227 "Result: Lost arbitration\n");
228 return MSP_TWI_XFER_LOST_ARBITRATION;
229 } else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
230 dev_dbg(&pmcmsptwi_adapter.dev,
231 "Result: No response\n");
232 return MSP_TWI_XFER_NO_RESPONSE;
233 } else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
234 dev_dbg(&pmcmsptwi_adapter.dev,
235 "Result: Data collision\n");
236 return MSP_TWI_XFER_DATA_COLLISION;
237 } else if (reg & MSP_TWI_INT_STS_BUSY) {
238 dev_dbg(&pmcmsptwi_adapter.dev,
239 "Result: Bus busy\n");
240 return MSP_TWI_XFER_BUSY;
241 }
242
243 dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
244 return MSP_TWI_XFER_OK;
245}
246
247/*
248 * In interrupt mode, handle the interrupt.
249 * NOTE: Assumes data->lock is held.
250 */
251static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
252{
253 struct pmcmsptwi_data *data = ptr;
254
255 u32 reason = pmcmsptwi_readl(data->iobase +
256 MSP_TWI_INT_STS_REG_OFFSET);
257 pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
258
259 dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
260 if (!(reason & MSP_TWI_INT_STS_DONE))
261 return IRQ_NONE;
262
263 data->last_result = pmcmsptwi_get_result(reason);
264 complete(&data->wait);
265
266 return IRQ_HANDLED;
267}
268
269/*
270 * Probe for and register the device and return 0 if there is one.
271 */
272static int pmcmsptwi_probe(struct platform_device *pldev)
273{
274 struct resource *res;
275 int rc = -ENODEV;
276
277 /* get the static platform resources */
278 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
279 if (!res) {
280 dev_err(&pldev->dev, "IOMEM resource not found\n");
281 goto ret_err;
282 }
283
284 /* reserve the memory region */
285 if (!request_mem_region(res->start, resource_size(res),
286 pldev->name)) {
287 dev_err(&pldev->dev,
288 "Unable to get memory/io address region 0x%08x\n",
289 res->start);
290 rc = -EBUSY;
291 goto ret_err;
292 }
293
294 /* remap the memory */
295 pmcmsptwi_data.iobase = ioremap_nocache(res->start,
296 resource_size(res));
297 if (!pmcmsptwi_data.iobase) {
298 dev_err(&pldev->dev,
299 "Unable to ioremap address 0x%08x\n", res->start);
300 rc = -EIO;
301 goto ret_unreserve;
302 }
303
304 /* request the irq */
305 pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
306 if (pmcmsptwi_data.irq) {
307 rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
308 IRQF_SHARED, pldev->name, &pmcmsptwi_data);
309 if (rc == 0) {
310 /*
311 * Enable 'DONE' interrupt only.
312 *
313 * If you enable all interrupts, you will get one on
314 * error and another when the operation completes.
315 * This way you only have to handle one interrupt,
316 * but you can still check all result flags.
317 */
318 pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
319 pmcmsptwi_data.iobase +
320 MSP_TWI_INT_MSK_REG_OFFSET);
321 } else {
322 dev_warn(&pldev->dev,
323 "Could not assign TWI IRQ handler "
324 "to irq %d (continuing with poll)\n",
325 pmcmsptwi_data.irq);
326 pmcmsptwi_data.irq = 0;
327 }
328 }
329
330 init_completion(&pmcmsptwi_data.wait);
331 mutex_init(&pmcmsptwi_data.lock);
332
333 pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
334 pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
335
336 printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
337
338 pmcmsptwi_adapter.dev.parent = &pldev->dev;
339 platform_set_drvdata(pldev, &pmcmsptwi_adapter);
340 i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
341
342 rc = i2c_add_adapter(&pmcmsptwi_adapter);
343 if (rc) {
344 dev_err(&pldev->dev, "Unable to register I2C adapter\n");
345 goto ret_unmap;
346 }
347
348 return 0;
349
350ret_unmap:
351 if (pmcmsptwi_data.irq) {
352 pmcmsptwi_writel(0,
353 pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
354 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
355 }
356
357 iounmap(pmcmsptwi_data.iobase);
358
359ret_unreserve:
360 release_mem_region(res->start, resource_size(res));
361
362ret_err:
363 return rc;
364}
365
366/*
367 * Release the device and return 0 if there is one.
368 */
369static int pmcmsptwi_remove(struct platform_device *pldev)
370{
371 struct resource *res;
372
373 i2c_del_adapter(&pmcmsptwi_adapter);
374
375 if (pmcmsptwi_data.irq) {
376 pmcmsptwi_writel(0,
377 pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
378 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
379 }
380
381 iounmap(pmcmsptwi_data.iobase);
382
383 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
384 release_mem_region(res->start, resource_size(res));
385
386 return 0;
387}
388
389/*
390 * Polls the 'busy' register until the command is complete.
391 * NOTE: Assumes data->lock is held.
392 */
393static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
394{
395 int i;
396
397 for (i = 0; i < MSP_MAX_POLL; i++) {
398 u32 val = pmcmsptwi_readl(data->iobase +
399 MSP_TWI_BUSY_REG_OFFSET);
400 if (val == 0) {
401 u32 reason = pmcmsptwi_readl(data->iobase +
402 MSP_TWI_INT_STS_REG_OFFSET);
403 pmcmsptwi_writel(reason, data->iobase +
404 MSP_TWI_INT_STS_REG_OFFSET);
405 data->last_result = pmcmsptwi_get_result(reason);
406 return;
407 }
408 udelay(MSP_POLL_DELAY);
409 }
410
411 dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
412 data->last_result = MSP_TWI_XFER_TIMEOUT;
413}
414
415/*
416 * Do the transfer (low level):
417 * May use interrupt-driven or polling, depending on if an IRQ is
418 * presently registered.
419 * NOTE: Assumes data->lock is held.
420 */
421static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
422 u32 reg, struct pmcmsptwi_data *data)
423{
424 dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
425 pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
426 if (data->irq) {
427 unsigned long timeleft = wait_for_completion_timeout(
428 &data->wait, MSP_IRQ_TIMEOUT);
429 if (timeleft == 0) {
430 dev_dbg(&pmcmsptwi_adapter.dev,
431 "Result: IRQ timeout\n");
432 complete(&data->wait);
433 data->last_result = MSP_TWI_XFER_TIMEOUT;
434 }
435 } else
436 pmcmsptwi_poll_complete(data);
437
438 return data->last_result;
439}
440
441/*
442 * Helper routine, converts 'pmctwi_cmd' struct to register format
443 */
444static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
445{
446 return ((cmd->type & 0x3) << 8) |
447 (((cmd->write_len - 1) & 0x7) << 4) |
448 ((cmd->read_len - 1) & 0x7);
449}
450
451/*
452 * Do the transfer (high level)
453 */
454static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
455 struct pmcmsptwi_cmd *cmd,
456 struct pmcmsptwi_data *data)
457{
458 enum pmcmsptwi_xfer_result retval;
459
460 if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
461 (cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
462 (cmd->type == MSP_TWI_CMD_WRITE_READ &&
463 (cmd->read_len == 0 || cmd->write_len == 0))) {
464 dev_err(&pmcmsptwi_adapter.dev,
465 "%s: Cannot transfer less than 1 byte\n",
466 __func__);
467 return -EINVAL;
468 }
469
470 if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
471 cmd->write_len > MSP_MAX_BYTES_PER_RW) {
472 dev_err(&pmcmsptwi_adapter.dev,
473 "%s: Cannot transfer more than %d bytes\n",
474 __func__, MSP_MAX_BYTES_PER_RW);
475 return -EINVAL;
476 }
477
478 mutex_lock(&data->lock);
479 dev_dbg(&pmcmsptwi_adapter.dev,
480 "Setting address to 0x%04x\n", cmd->addr);
481 pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
482
483 if (cmd->type == MSP_TWI_CMD_WRITE ||
484 cmd->type == MSP_TWI_CMD_WRITE_READ) {
485 u64 tmp = be64_to_cpup((__be64 *)cmd->write_data);
486 tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
487 dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
488 pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
489 data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
490 if (cmd->write_len > 4)
491 pmcmsptwi_writel(tmp >> 32,
492 data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
493 }
494
495 retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
496 if (retval != MSP_TWI_XFER_OK)
497 goto xfer_err;
498
499 if (cmd->type == MSP_TWI_CMD_READ ||
500 cmd->type == MSP_TWI_CMD_WRITE_READ) {
501 int i;
502 u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
503 u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
504 MSP_TWI_DAT_0_REG_OFFSET);
505 if (cmd->read_len > 4)
506 tmp |= (u64)pmcmsptwi_readl(data->iobase +
507 MSP_TWI_DAT_1_REG_OFFSET) << 32;
508 tmp &= rmsk;
509 dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
510
511 for (i = 0; i < cmd->read_len; i++)
512 cmd->read_data[i] = tmp >> i;
513 }
514
515xfer_err:
516 mutex_unlock(&data->lock);
517
518 return retval;
519}
520
521/* -- Algorithm functions -- */
522
523/*
524 * Sends an i2c command out on the adapter
525 */
526static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
527 struct i2c_msg *msg, int num)
528{
529 struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
530 struct pmcmsptwi_cmd cmd;
531 struct pmcmsptwi_cfg oldcfg, newcfg;
532 int ret;
533
534 if (num > 2) {
535 dev_dbg(&adap->dev, "%d messages unsupported\n", num);
536 return -EINVAL;
537 } else if (num == 2) {
538 /* Check for a dual write-then-read command */
539 struct i2c_msg *nextmsg = msg + 1;
540 if (!(msg->flags & I2C_M_RD) &&
541 (nextmsg->flags & I2C_M_RD) &&
542 msg->addr == nextmsg->addr) {
543 cmd.type = MSP_TWI_CMD_WRITE_READ;
544 cmd.write_len = msg->len;
545 cmd.write_data = msg->buf;
546 cmd.read_len = nextmsg->len;
547 cmd.read_data = nextmsg->buf;
548 } else {
549 dev_dbg(&adap->dev,
550 "Non write-read dual messages unsupported\n");
551 return -EINVAL;
552 }
553 } else if (msg->flags & I2C_M_RD) {
554 cmd.type = MSP_TWI_CMD_READ;
555 cmd.read_len = msg->len;
556 cmd.read_data = msg->buf;
557 cmd.write_len = 0;
558 cmd.write_data = NULL;
559 } else {
560 cmd.type = MSP_TWI_CMD_WRITE;
561 cmd.read_len = 0;
562 cmd.read_data = NULL;
563 cmd.write_len = msg->len;
564 cmd.write_data = msg->buf;
565 }
566
567 if (msg->len == 0) {
568 dev_err(&adap->dev, "Zero-byte messages unsupported\n");
569 return -EINVAL;
570 }
571
572 cmd.addr = msg->addr;
573
574 if (msg->flags & I2C_M_TEN) {
575 pmcmsptwi_get_twi_config(&newcfg, data);
576 memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
577
578 /* Set the special 10-bit address flag */
579 newcfg.add10 = 1;
580
581 pmcmsptwi_set_twi_config(&newcfg, data);
582 }
583
584 /* Execute the command */
585 ret = pmcmsptwi_xfer_cmd(&cmd, data);
586
587 if (msg->flags & I2C_M_TEN)
588 pmcmsptwi_set_twi_config(&oldcfg, data);
589
590 dev_dbg(&adap->dev, "I2C %s of %d bytes %s\n",
591 (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
592 (ret == MSP_TWI_XFER_OK) ? "succeeded" : "failed");
593
594 if (ret != MSP_TWI_XFER_OK) {
595 /*
596 * TODO: We could potentially loop and retry in the case
597 * of MSP_TWI_XFER_TIMEOUT.
598 */
599 return -1;
600 }
601
602 return 0;
603}
604
605static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
606{
607 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
608 I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
609 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
610}
611
612/* -- Initialization -- */
613
614static struct i2c_algorithm pmcmsptwi_algo = {
615 .master_xfer = pmcmsptwi_master_xfer,
616 .functionality = pmcmsptwi_i2c_func,
617};
618
619static struct i2c_adapter pmcmsptwi_adapter = {
620 .owner = THIS_MODULE,
621 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
622 .algo = &pmcmsptwi_algo,
623 .name = DRV_NAME,
624};
625
626static struct platform_driver pmcmsptwi_driver = {
627 .probe = pmcmsptwi_probe,
628 .remove = pmcmsptwi_remove,
629 .driver = {
630 .name = DRV_NAME,
631 .owner = THIS_MODULE,
632 },
633};
634
635module_platform_driver(pmcmsptwi_driver);
636
637MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
638MODULE_LICENSE("GPL");
639MODULE_ALIAS("platform:" DRV_NAME);