Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 * Author: Rob Clark <rob@ti.com>
5 */
6
7#include <linux/math64.h>
8
9#include <drm/drm_atomic.h>
10#include <drm/drm_atomic_helper.h>
11#include <drm/drm_crtc.h>
12#include <drm/drm_mode.h>
13#include <drm/drm_vblank.h>
14
15#include "omap_drv.h"
16
17#define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
18
19struct omap_crtc_state {
20 /* Must be first. */
21 struct drm_crtc_state base;
22 /* Shadow values for legacy userspace support. */
23 unsigned int rotation;
24 unsigned int zpos;
25 bool manually_updated;
26};
27
28#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
29
30struct omap_crtc {
31 struct drm_crtc base;
32
33 const char *name;
34 struct omap_drm_pipeline *pipe;
35 enum omap_channel channel;
36
37 struct videomode vm;
38
39 bool ignore_digit_sync_lost;
40
41 bool enabled;
42 bool pending;
43 wait_queue_head_t pending_wait;
44 struct drm_pending_vblank_event *event;
45 struct delayed_work update_work;
46
47 void (*framedone_handler)(void *);
48 void *framedone_handler_data;
49};
50
51/* -----------------------------------------------------------------------------
52 * Helper Functions
53 */
54
55struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
56{
57 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
58 return &omap_crtc->vm;
59}
60
61enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
62{
63 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
64 return omap_crtc->channel;
65}
66
67static bool omap_crtc_is_pending(struct drm_crtc *crtc)
68{
69 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
70 unsigned long flags;
71 bool pending;
72
73 spin_lock_irqsave(&crtc->dev->event_lock, flags);
74 pending = omap_crtc->pending;
75 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
76
77 return pending;
78}
79
80int omap_crtc_wait_pending(struct drm_crtc *crtc)
81{
82 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
83
84 /*
85 * Timeout is set to a "sufficiently" high value, which should cover
86 * a single frame refresh even on slower displays.
87 */
88 return wait_event_timeout(omap_crtc->pending_wait,
89 !omap_crtc_is_pending(crtc),
90 msecs_to_jiffies(250));
91}
92
93/* -----------------------------------------------------------------------------
94 * DSS Manager Functions
95 */
96
97/*
98 * Manager-ops, callbacks from output when they need to configure
99 * the upstream part of the video pipe.
100 */
101
102void omap_crtc_dss_start_update(struct omap_drm_private *priv,
103 enum omap_channel channel)
104{
105 dispc_mgr_enable(priv->dispc, channel, true);
106}
107
108/* Called only from the encoder enable/disable and suspend/resume handlers. */
109void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
110{
111 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
112 struct drm_device *dev = crtc->dev;
113 struct omap_drm_private *priv = dev->dev_private;
114 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
115 enum omap_channel channel = omap_crtc->channel;
116 struct omap_irq_wait *wait;
117 u32 framedone_irq, vsync_irq;
118 int ret;
119
120 if (WARN_ON(omap_crtc->enabled == enable))
121 return;
122
123 if (omap_state->manually_updated) {
124 omap_irq_enable_framedone(crtc, enable);
125 omap_crtc->enabled = enable;
126 return;
127 }
128
129 if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
130 dispc_mgr_enable(priv->dispc, channel, enable);
131 omap_crtc->enabled = enable;
132 return;
133 }
134
135 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
136 /*
137 * Digit output produces some sync lost interrupts during the
138 * first frame when enabling, so we need to ignore those.
139 */
140 omap_crtc->ignore_digit_sync_lost = true;
141 }
142
143 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc,
144 channel);
145 vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel);
146
147 if (enable) {
148 wait = omap_irq_wait_init(dev, vsync_irq, 1);
149 } else {
150 /*
151 * When we disable the digit output, we need to wait for
152 * FRAMEDONE to know that DISPC has finished with the output.
153 *
154 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
155 * that case we need to use vsync interrupt, and wait for both
156 * even and odd frames.
157 */
158
159 if (framedone_irq)
160 wait = omap_irq_wait_init(dev, framedone_irq, 1);
161 else
162 wait = omap_irq_wait_init(dev, vsync_irq, 2);
163 }
164
165 dispc_mgr_enable(priv->dispc, channel, enable);
166 omap_crtc->enabled = enable;
167
168 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
169 if (ret) {
170 dev_err(dev->dev, "%s: timeout waiting for %s\n",
171 omap_crtc->name, enable ? "enable" : "disable");
172 }
173
174 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
175 omap_crtc->ignore_digit_sync_lost = false;
176 /* make sure the irq handler sees the value above */
177 mb();
178 }
179}
180
181
182int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel)
183{
184 struct drm_crtc *crtc = priv->channels[channel]->crtc;
185 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
186
187 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel,
188 &omap_crtc->vm);
189 omap_crtc_set_enabled(&omap_crtc->base, true);
190
191 return 0;
192}
193
194void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel)
195{
196 struct drm_crtc *crtc = priv->channels[channel]->crtc;
197 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
198
199 omap_crtc_set_enabled(&omap_crtc->base, false);
200}
201
202void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
203 enum omap_channel channel,
204 const struct videomode *vm)
205{
206 struct drm_crtc *crtc = priv->channels[channel]->crtc;
207 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
208
209 DBG("%s", omap_crtc->name);
210 omap_crtc->vm = *vm;
211}
212
213void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
214 enum omap_channel channel,
215 const struct dss_lcd_mgr_config *config)
216{
217 struct drm_crtc *crtc = priv->channels[channel]->crtc;
218 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
219
220 DBG("%s", omap_crtc->name);
221 dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
222 config);
223}
224
225int omap_crtc_dss_register_framedone(
226 struct omap_drm_private *priv, enum omap_channel channel,
227 void (*handler)(void *), void *data)
228{
229 struct drm_crtc *crtc = priv->channels[channel]->crtc;
230 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
231 struct drm_device *dev = omap_crtc->base.dev;
232
233 if (omap_crtc->framedone_handler)
234 return -EBUSY;
235
236 dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
237
238 omap_crtc->framedone_handler = handler;
239 omap_crtc->framedone_handler_data = data;
240
241 return 0;
242}
243
244void omap_crtc_dss_unregister_framedone(
245 struct omap_drm_private *priv, enum omap_channel channel,
246 void (*handler)(void *), void *data)
247{
248 struct drm_crtc *crtc = priv->channels[channel]->crtc;
249 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
250 struct drm_device *dev = omap_crtc->base.dev;
251
252 dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
253
254 WARN_ON(omap_crtc->framedone_handler != handler);
255 WARN_ON(omap_crtc->framedone_handler_data != data);
256
257 omap_crtc->framedone_handler = NULL;
258 omap_crtc->framedone_handler_data = NULL;
259}
260
261/* -----------------------------------------------------------------------------
262 * Setup, Flush and Page Flip
263 */
264
265void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
266{
267 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
268
269 if (omap_crtc->ignore_digit_sync_lost) {
270 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
271 if (!irqstatus)
272 return;
273 }
274
275 DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
276}
277
278void omap_crtc_vblank_irq(struct drm_crtc *crtc)
279{
280 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
281 struct drm_device *dev = omap_crtc->base.dev;
282 struct omap_drm_private *priv = dev->dev_private;
283 bool pending;
284
285 spin_lock(&crtc->dev->event_lock);
286 /*
287 * If the dispc is busy we're racing the flush operation. Try again on
288 * the next vblank interrupt.
289 */
290 if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) {
291 spin_unlock(&crtc->dev->event_lock);
292 return;
293 }
294
295 /* Send the vblank event if one has been requested. */
296 if (omap_crtc->event) {
297 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
298 omap_crtc->event = NULL;
299 }
300
301 pending = omap_crtc->pending;
302 omap_crtc->pending = false;
303 spin_unlock(&crtc->dev->event_lock);
304
305 if (pending)
306 drm_crtc_vblank_put(crtc);
307
308 /* Wake up omap_atomic_complete. */
309 wake_up(&omap_crtc->pending_wait);
310
311 DBG("%s: apply done", omap_crtc->name);
312}
313
314void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
315{
316 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
317
318 if (!omap_crtc->framedone_handler)
319 return;
320
321 omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
322
323 spin_lock(&crtc->dev->event_lock);
324 /* Send the vblank event if one has been requested. */
325 if (omap_crtc->event) {
326 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
327 omap_crtc->event = NULL;
328 }
329 omap_crtc->pending = false;
330 spin_unlock(&crtc->dev->event_lock);
331
332 /* Wake up omap_atomic_complete. */
333 wake_up(&omap_crtc->pending_wait);
334}
335
336void omap_crtc_flush(struct drm_crtc *crtc)
337{
338 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
339 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
340
341 if (!omap_state->manually_updated)
342 return;
343
344 if (!delayed_work_pending(&omap_crtc->update_work))
345 schedule_delayed_work(&omap_crtc->update_work, 0);
346}
347
348static void omap_crtc_manual_display_update(struct work_struct *data)
349{
350 struct omap_crtc *omap_crtc =
351 container_of(data, struct omap_crtc, update_work.work);
352 struct omap_dss_device *dssdev = omap_crtc->pipe->output;
353 struct drm_device *dev = omap_crtc->base.dev;
354 int ret;
355
356 if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->update)
357 return;
358
359 ret = dssdev->dsi_ops->update(dssdev);
360 if (ret < 0) {
361 spin_lock_irq(&dev->event_lock);
362 omap_crtc->pending = false;
363 spin_unlock_irq(&dev->event_lock);
364 wake_up(&omap_crtc->pending_wait);
365 }
366}
367
368static s16 omap_crtc_s31_32_to_s2_8(s64 coef)
369{
370 u64 sign_bit = 1ULL << 63;
371 u64 cbits = (u64)coef;
372
373 s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1ff);
374
375 if (cbits & sign_bit)
376 ret = -ret;
377
378 return ret;
379}
380
381static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm,
382 struct omap_dss_cpr_coefs *cpr)
383{
384 cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]);
385 cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]);
386 cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]);
387 cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]);
388 cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]);
389 cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]);
390 cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]);
391 cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]);
392 cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]);
393}
394
395static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
396{
397 struct omap_drm_private *priv = crtc->dev->dev_private;
398 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
399 struct omap_overlay_manager_info info;
400
401 memset(&info, 0, sizeof(info));
402
403 info.default_color = 0x000000;
404 info.trans_enabled = false;
405 info.partial_alpha_enabled = false;
406
407 if (crtc->state->ctm) {
408 struct drm_color_ctm *ctm = crtc->state->ctm->data;
409
410 info.cpr_enable = true;
411 omap_crtc_cpr_coefs_from_ctm(ctm, &info.cpr_coefs);
412 } else {
413 info.cpr_enable = false;
414 }
415
416 dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info);
417}
418
419/* -----------------------------------------------------------------------------
420 * CRTC Functions
421 */
422
423static void omap_crtc_destroy(struct drm_crtc *crtc)
424{
425 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
426
427 DBG("%s", omap_crtc->name);
428
429 drm_crtc_cleanup(crtc);
430
431 kfree(omap_crtc);
432}
433
434static void omap_crtc_arm_event(struct drm_crtc *crtc)
435{
436 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
437
438 WARN_ON(omap_crtc->pending);
439 omap_crtc->pending = true;
440
441 if (crtc->state->event) {
442 omap_crtc->event = crtc->state->event;
443 crtc->state->event = NULL;
444 }
445}
446
447static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
448 struct drm_atomic_state *state)
449{
450 struct omap_drm_private *priv = crtc->dev->dev_private;
451 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
452 struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
453 int ret;
454
455 DBG("%s", omap_crtc->name);
456
457 dispc_runtime_get(priv->dispc);
458
459 /* manual updated display will not trigger vsync irq */
460 if (omap_state->manually_updated)
461 return;
462
463 drm_crtc_vblank_on(crtc);
464
465 ret = drm_crtc_vblank_get(crtc);
466 WARN_ON(ret != 0);
467
468 spin_lock_irq(&crtc->dev->event_lock);
469 omap_crtc_arm_event(crtc);
470 spin_unlock_irq(&crtc->dev->event_lock);
471}
472
473static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
474 struct drm_atomic_state *state)
475{
476 struct omap_drm_private *priv = crtc->dev->dev_private;
477 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
478 struct drm_device *dev = crtc->dev;
479
480 DBG("%s", omap_crtc->name);
481
482 spin_lock_irq(&crtc->dev->event_lock);
483 if (crtc->state->event) {
484 drm_crtc_send_vblank_event(crtc, crtc->state->event);
485 crtc->state->event = NULL;
486 }
487 spin_unlock_irq(&crtc->dev->event_lock);
488
489 cancel_delayed_work(&omap_crtc->update_work);
490
491 if (!omap_crtc_wait_pending(crtc))
492 dev_warn(dev->dev, "manual display update did not finish!");
493
494 drm_crtc_vblank_off(crtc);
495
496 dispc_runtime_put(priv->dispc);
497}
498
499static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
500 const struct drm_display_mode *mode)
501{
502 struct omap_drm_private *priv = crtc->dev->dev_private;
503 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
504 struct videomode vm = {0};
505 int r;
506
507 drm_display_mode_to_videomode(mode, &vm);
508
509 /*
510 * DSI might not call this, since the supplied mode is not a
511 * valid DISPC mode. DSI will calculate and configure the
512 * proper DISPC mode later.
513 */
514 if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) {
515 r = dispc_mgr_check_timings(priv->dispc,
516 omap_crtc->channel,
517 &vm);
518 if (r)
519 return r;
520 }
521
522 /* Check for bandwidth limit */
523 if (priv->max_bandwidth) {
524 /*
525 * Estimation for the bandwidth need of a given mode with one
526 * full screen plane:
527 * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
528 * ^^ Refresh rate ^^
529 *
530 * The interlaced mode is taken into account by using the
531 * pixelclock in the calculation.
532 *
533 * The equation is rearranged for 64bit arithmetic.
534 */
535 uint64_t bandwidth = mode->clock * 1000;
536 unsigned int bpp = 4;
537
538 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
539 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
540
541 /*
542 * Reject modes which would need more bandwidth if used with one
543 * full resolution plane (most common use case).
544 */
545 if (priv->max_bandwidth < bandwidth)
546 return MODE_BAD;
547 }
548
549 return MODE_OK;
550}
551
552static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
553{
554 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
555 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
556
557 DBG("%s: set mode: " DRM_MODE_FMT,
558 omap_crtc->name, DRM_MODE_ARG(mode));
559
560 drm_display_mode_to_videomode(mode, &omap_crtc->vm);
561}
562
563static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
564{
565 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
566 struct omap_dss_device *dssdev = omap_crtc->pipe->output;
567
568 if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->is_video_mode)
569 return false;
570
571 if (dssdev->dsi_ops->is_video_mode(dssdev))
572 return false;
573
574 DBG("detected manually updated display!");
575 return true;
576}
577
578static int omap_crtc_atomic_check(struct drm_crtc *crtc,
579 struct drm_atomic_state *state)
580{
581 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
582 crtc);
583 struct drm_plane_state *pri_state;
584
585 if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) {
586 unsigned int length = crtc_state->degamma_lut->length /
587 sizeof(struct drm_color_lut);
588
589 if (length < 2)
590 return -EINVAL;
591 }
592
593 pri_state = drm_atomic_get_new_plane_state(state,
594 crtc->primary);
595 if (pri_state) {
596 struct omap_crtc_state *omap_crtc_state =
597 to_omap_crtc_state(crtc_state);
598
599 /* Mirror new values for zpos and rotation in omap_crtc_state */
600 omap_crtc_state->zpos = pri_state->zpos;
601 omap_crtc_state->rotation = pri_state->rotation;
602
603 /* Check if this CRTC is for a manually updated display */
604 omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
605 }
606
607 return 0;
608}
609
610static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
611 struct drm_atomic_state *state)
612{
613}
614
615static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
616 struct drm_atomic_state *state)
617{
618 struct omap_drm_private *priv = crtc->dev->dev_private;
619 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
620 struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
621 int ret;
622
623 if (crtc->state->color_mgmt_changed) {
624 struct drm_color_lut *lut = NULL;
625 unsigned int length = 0;
626
627 if (crtc->state->degamma_lut) {
628 lut = (struct drm_color_lut *)
629 crtc->state->degamma_lut->data;
630 length = crtc->state->degamma_lut->length /
631 sizeof(*lut);
632 }
633 dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel,
634 lut, length);
635 }
636
637 omap_crtc_write_crtc_properties(crtc);
638
639 /* Only flush the CRTC if it is currently enabled. */
640 if (!omap_crtc->enabled)
641 return;
642
643 DBG("%s: GO", omap_crtc->name);
644
645 if (omap_crtc_state->manually_updated) {
646 /* send new image for page flips and modeset changes */
647 spin_lock_irq(&crtc->dev->event_lock);
648 omap_crtc_flush(crtc);
649 omap_crtc_arm_event(crtc);
650 spin_unlock_irq(&crtc->dev->event_lock);
651 return;
652 }
653
654 ret = drm_crtc_vblank_get(crtc);
655 WARN_ON(ret != 0);
656
657 spin_lock_irq(&crtc->dev->event_lock);
658 dispc_mgr_go(priv->dispc, omap_crtc->channel);
659 omap_crtc_arm_event(crtc);
660 spin_unlock_irq(&crtc->dev->event_lock);
661}
662
663static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
664 struct drm_crtc_state *state,
665 struct drm_property *property,
666 u64 val)
667{
668 struct omap_drm_private *priv = crtc->dev->dev_private;
669 struct drm_plane_state *plane_state;
670
671 /*
672 * Delegate property set to the primary plane. Get the plane state and
673 * set the property directly, the shadow copy will be assigned in the
674 * omap_crtc_atomic_check callback. This way updates to plane state will
675 * always be mirrored in the crtc state correctly.
676 */
677 plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
678 if (IS_ERR(plane_state))
679 return PTR_ERR(plane_state);
680
681 if (property == crtc->primary->rotation_property)
682 plane_state->rotation = val;
683 else if (property == priv->zorder_prop)
684 plane_state->zpos = val;
685 else
686 return -EINVAL;
687
688 return 0;
689}
690
691static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
692 const struct drm_crtc_state *state,
693 struct drm_property *property,
694 u64 *val)
695{
696 struct omap_drm_private *priv = crtc->dev->dev_private;
697 struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
698
699 if (property == crtc->primary->rotation_property)
700 *val = omap_state->rotation;
701 else if (property == priv->zorder_prop)
702 *val = omap_state->zpos;
703 else
704 return -EINVAL;
705
706 return 0;
707}
708
709static void omap_crtc_reset(struct drm_crtc *crtc)
710{
711 struct omap_crtc_state *state;
712
713 if (crtc->state)
714 __drm_atomic_helper_crtc_destroy_state(crtc->state);
715
716 kfree(crtc->state);
717
718 state = kzalloc(sizeof(*state), GFP_KERNEL);
719 if (state)
720 __drm_atomic_helper_crtc_reset(crtc, &state->base);
721}
722
723static struct drm_crtc_state *
724omap_crtc_duplicate_state(struct drm_crtc *crtc)
725{
726 struct omap_crtc_state *state, *current_state;
727
728 if (WARN_ON(!crtc->state))
729 return NULL;
730
731 current_state = to_omap_crtc_state(crtc->state);
732
733 state = kmalloc(sizeof(*state), GFP_KERNEL);
734 if (!state)
735 return NULL;
736
737 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
738
739 state->zpos = current_state->zpos;
740 state->rotation = current_state->rotation;
741 state->manually_updated = current_state->manually_updated;
742
743 return &state->base;
744}
745
746static const struct drm_crtc_funcs omap_crtc_funcs = {
747 .reset = omap_crtc_reset,
748 .set_config = drm_atomic_helper_set_config,
749 .destroy = omap_crtc_destroy,
750 .page_flip = drm_atomic_helper_page_flip,
751 .atomic_duplicate_state = omap_crtc_duplicate_state,
752 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
753 .atomic_set_property = omap_crtc_atomic_set_property,
754 .atomic_get_property = omap_crtc_atomic_get_property,
755 .enable_vblank = omap_irq_enable_vblank,
756 .disable_vblank = omap_irq_disable_vblank,
757};
758
759static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
760 .mode_set_nofb = omap_crtc_mode_set_nofb,
761 .atomic_check = omap_crtc_atomic_check,
762 .atomic_begin = omap_crtc_atomic_begin,
763 .atomic_flush = omap_crtc_atomic_flush,
764 .atomic_enable = omap_crtc_atomic_enable,
765 .atomic_disable = omap_crtc_atomic_disable,
766 .mode_valid = omap_crtc_mode_valid,
767};
768
769/* -----------------------------------------------------------------------------
770 * Init and Cleanup
771 */
772
773static const char *channel_names[] = {
774 [OMAP_DSS_CHANNEL_LCD] = "lcd",
775 [OMAP_DSS_CHANNEL_DIGIT] = "tv",
776 [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
777 [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
778};
779
780/* initialize crtc */
781struct drm_crtc *omap_crtc_init(struct drm_device *dev,
782 struct omap_drm_pipeline *pipe,
783 struct drm_plane *plane)
784{
785 struct omap_drm_private *priv = dev->dev_private;
786 struct drm_crtc *crtc = NULL;
787 struct omap_crtc *omap_crtc;
788 enum omap_channel channel;
789 int ret;
790
791 channel = pipe->output->dispc_channel;
792
793 DBG("%s", channel_names[channel]);
794
795 omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
796 if (!omap_crtc)
797 return ERR_PTR(-ENOMEM);
798
799 crtc = &omap_crtc->base;
800
801 init_waitqueue_head(&omap_crtc->pending_wait);
802
803 omap_crtc->pipe = pipe;
804 omap_crtc->channel = channel;
805 omap_crtc->name = channel_names[channel];
806
807 /*
808 * We want to refresh manually updated displays from dirty callback,
809 * which is called quite often (e.g. for each drawn line). This will
810 * be used to do the display update asynchronously to avoid blocking
811 * the rendering process and merges multiple dirty calls into one
812 * update if they arrive very fast. We also call this function for
813 * atomic display updates (e.g. for page flips), which means we do
814 * not need extra locking. Atomic updates should be synchronous, but
815 * need to wait for the framedone interrupt anyways.
816 */
817 INIT_DELAYED_WORK(&omap_crtc->update_work,
818 omap_crtc_manual_display_update);
819
820 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
821 &omap_crtc_funcs, NULL);
822 if (ret < 0) {
823 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
824 __func__, pipe->output->name);
825 kfree(omap_crtc);
826 return ERR_PTR(ret);
827 }
828
829 drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
830
831 /* The dispc API adapts to what ever size, but the HW supports
832 * 256 element gamma table for LCDs and 1024 element table for
833 * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
834 * tables so lets use that. Size of HW gamma table can be
835 * extracted with dispc_mgr_gamma_size(). If it returns 0
836 * gamma table is not supported.
837 */
838 if (dispc_mgr_gamma_size(priv->dispc, channel)) {
839 unsigned int gamma_lut_size = 256;
840
841 drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0);
842 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
843 }
844
845 omap_plane_install_properties(crtc->primary, &crtc->base);
846
847 return crtc;
848}
1/*
2 * drivers/gpu/drm/omapdrm/omap_crtc.c
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Rob Clark <rob@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "omap_drv.h"
21
22#include <drm/drm_mode.h>
23#include "drm_crtc.h"
24#include "drm_crtc_helper.h"
25
26#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
27
28struct omap_crtc {
29 struct drm_crtc base;
30 struct drm_plane *plane;
31
32 const char *name;
33 int pipe;
34 enum omap_channel channel;
35 struct omap_overlay_manager_info info;
36 struct drm_encoder *current_encoder;
37
38 /*
39 * Temporary: eventually this will go away, but it is needed
40 * for now to keep the output's happy. (They only need
41 * mgr->id.) Eventually this will be replaced w/ something
42 * more common-panel-framework-y
43 */
44 struct omap_overlay_manager *mgr;
45
46 struct omap_video_timings timings;
47 bool enabled;
48 bool full_update;
49
50 struct omap_drm_apply apply;
51
52 struct omap_drm_irq apply_irq;
53 struct omap_drm_irq error_irq;
54
55 /* list of in-progress apply's: */
56 struct list_head pending_applies;
57
58 /* list of queued apply's: */
59 struct list_head queued_applies;
60
61 /* for handling queued and in-progress applies: */
62 struct work_struct apply_work;
63
64 /* if there is a pending flip, these will be non-null: */
65 struct drm_pending_vblank_event *event;
66 struct drm_framebuffer *old_fb;
67
68 /* for handling page flips without caring about what
69 * the callback is called from. Possibly we should just
70 * make omap_gem always call the cb from the worker so
71 * we don't have to care about this..
72 *
73 * XXX maybe fold into apply_work??
74 */
75 struct work_struct page_flip_work;
76};
77
78uint32_t pipe2vbl(struct drm_crtc *crtc)
79{
80 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
81
82 return dispc_mgr_get_vsync_irq(omap_crtc->channel);
83}
84
85/*
86 * Manager-ops, callbacks from output when they need to configure
87 * the upstream part of the video pipe.
88 *
89 * Most of these we can ignore until we add support for command-mode
90 * panels.. for video-mode the crtc-helpers already do an adequate
91 * job of sequencing the setup of the video pipe in the proper order
92 */
93
94/* ovl-mgr-id -> crtc */
95static struct omap_crtc *omap_crtcs[8];
96
97/* we can probably ignore these until we support command-mode panels: */
98static int omap_crtc_connect(struct omap_overlay_manager *mgr,
99 struct omap_dss_device *dst)
100{
101 if (mgr->output)
102 return -EINVAL;
103
104 if ((mgr->supported_outputs & dst->id) == 0)
105 return -EINVAL;
106
107 dst->manager = mgr;
108 mgr->output = dst;
109
110 return 0;
111}
112
113static void omap_crtc_disconnect(struct omap_overlay_manager *mgr,
114 struct omap_dss_device *dst)
115{
116 mgr->output->manager = NULL;
117 mgr->output = NULL;
118}
119
120static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
121{
122}
123
124static void set_enabled(struct drm_crtc *crtc, bool enable);
125
126static int omap_crtc_enable(struct omap_overlay_manager *mgr)
127{
128 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
129
130 dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
131 dispc_mgr_set_timings(omap_crtc->channel,
132 &omap_crtc->timings);
133 set_enabled(&omap_crtc->base, true);
134
135 return 0;
136}
137
138static void omap_crtc_disable(struct omap_overlay_manager *mgr)
139{
140 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
141
142 set_enabled(&omap_crtc->base, false);
143}
144
145static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
146 const struct omap_video_timings *timings)
147{
148 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
149 DBG("%s", omap_crtc->name);
150 omap_crtc->timings = *timings;
151 omap_crtc->full_update = true;
152}
153
154static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
155 const struct dss_lcd_mgr_config *config)
156{
157 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
158 DBG("%s", omap_crtc->name);
159 dispc_mgr_set_lcd_config(omap_crtc->channel, config);
160}
161
162static int omap_crtc_register_framedone_handler(
163 struct omap_overlay_manager *mgr,
164 void (*handler)(void *), void *data)
165{
166 return 0;
167}
168
169static void omap_crtc_unregister_framedone_handler(
170 struct omap_overlay_manager *mgr,
171 void (*handler)(void *), void *data)
172{
173}
174
175static const struct dss_mgr_ops mgr_ops = {
176 .connect = omap_crtc_connect,
177 .disconnect = omap_crtc_disconnect,
178 .start_update = omap_crtc_start_update,
179 .enable = omap_crtc_enable,
180 .disable = omap_crtc_disable,
181 .set_timings = omap_crtc_set_timings,
182 .set_lcd_config = omap_crtc_set_lcd_config,
183 .register_framedone_handler = omap_crtc_register_framedone_handler,
184 .unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
185};
186
187/*
188 * CRTC funcs:
189 */
190
191static void omap_crtc_destroy(struct drm_crtc *crtc)
192{
193 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
194
195 DBG("%s", omap_crtc->name);
196
197 WARN_ON(omap_crtc->apply_irq.registered);
198 omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
199
200 drm_crtc_cleanup(crtc);
201
202 kfree(omap_crtc);
203}
204
205static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
206{
207 struct omap_drm_private *priv = crtc->dev->dev_private;
208 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
209 bool enabled = (mode == DRM_MODE_DPMS_ON);
210 int i;
211
212 DBG("%s: %d", omap_crtc->name, mode);
213
214 if (enabled != omap_crtc->enabled) {
215 omap_crtc->enabled = enabled;
216 omap_crtc->full_update = true;
217 omap_crtc_apply(crtc, &omap_crtc->apply);
218
219 /* also enable our private plane: */
220 WARN_ON(omap_plane_dpms(omap_crtc->plane, mode));
221
222 /* and any attached overlay planes: */
223 for (i = 0; i < priv->num_planes; i++) {
224 struct drm_plane *plane = priv->planes[i];
225 if (plane->crtc == crtc)
226 WARN_ON(omap_plane_dpms(plane, mode));
227 }
228 }
229}
230
231static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
232 const struct drm_display_mode *mode,
233 struct drm_display_mode *adjusted_mode)
234{
235 return true;
236}
237
238static int omap_crtc_mode_set(struct drm_crtc *crtc,
239 struct drm_display_mode *mode,
240 struct drm_display_mode *adjusted_mode,
241 int x, int y,
242 struct drm_framebuffer *old_fb)
243{
244 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
245
246 mode = adjusted_mode;
247
248 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
249 omap_crtc->name, mode->base.id, mode->name,
250 mode->vrefresh, mode->clock,
251 mode->hdisplay, mode->hsync_start,
252 mode->hsync_end, mode->htotal,
253 mode->vdisplay, mode->vsync_start,
254 mode->vsync_end, mode->vtotal,
255 mode->type, mode->flags);
256
257 copy_timings_drm_to_omap(&omap_crtc->timings, mode);
258 omap_crtc->full_update = true;
259
260 return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb,
261 0, 0, mode->hdisplay, mode->vdisplay,
262 x << 16, y << 16,
263 mode->hdisplay << 16, mode->vdisplay << 16,
264 NULL, NULL);
265}
266
267static void omap_crtc_prepare(struct drm_crtc *crtc)
268{
269 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
270 DBG("%s", omap_crtc->name);
271 omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
272}
273
274static void omap_crtc_commit(struct drm_crtc *crtc)
275{
276 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
277 DBG("%s", omap_crtc->name);
278 omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
279}
280
281static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
282 struct drm_framebuffer *old_fb)
283{
284 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
285 struct drm_plane *plane = omap_crtc->plane;
286 struct drm_display_mode *mode = &crtc->mode;
287
288 return omap_plane_mode_set(plane, crtc, crtc->primary->fb,
289 0, 0, mode->hdisplay, mode->vdisplay,
290 x << 16, y << 16,
291 mode->hdisplay << 16, mode->vdisplay << 16,
292 NULL, NULL);
293}
294
295static void vblank_cb(void *arg)
296{
297 struct drm_crtc *crtc = arg;
298 struct drm_device *dev = crtc->dev;
299 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
300 unsigned long flags;
301
302 spin_lock_irqsave(&dev->event_lock, flags);
303
304 /* wakeup userspace */
305 if (omap_crtc->event)
306 drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);
307
308 omap_crtc->event = NULL;
309 omap_crtc->old_fb = NULL;
310
311 spin_unlock_irqrestore(&dev->event_lock, flags);
312}
313
314static void page_flip_worker(struct work_struct *work)
315{
316 struct omap_crtc *omap_crtc =
317 container_of(work, struct omap_crtc, page_flip_work);
318 struct drm_crtc *crtc = &omap_crtc->base;
319 struct drm_display_mode *mode = &crtc->mode;
320 struct drm_gem_object *bo;
321
322 mutex_lock(&crtc->mutex);
323 omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb,
324 0, 0, mode->hdisplay, mode->vdisplay,
325 crtc->x << 16, crtc->y << 16,
326 mode->hdisplay << 16, mode->vdisplay << 16,
327 vblank_cb, crtc);
328 mutex_unlock(&crtc->mutex);
329
330 bo = omap_framebuffer_bo(crtc->primary->fb, 0);
331 drm_gem_object_unreference_unlocked(bo);
332}
333
334static void page_flip_cb(void *arg)
335{
336 struct drm_crtc *crtc = arg;
337 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
338 struct omap_drm_private *priv = crtc->dev->dev_private;
339
340 /* avoid assumptions about what ctxt we are called from: */
341 queue_work(priv->wq, &omap_crtc->page_flip_work);
342}
343
344static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
345 struct drm_framebuffer *fb,
346 struct drm_pending_vblank_event *event,
347 uint32_t page_flip_flags)
348{
349 struct drm_device *dev = crtc->dev;
350 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
351 struct drm_plane *primary = crtc->primary;
352 struct drm_gem_object *bo;
353 unsigned long flags;
354
355 DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1,
356 fb->base.id, event);
357
358 spin_lock_irqsave(&dev->event_lock, flags);
359
360 if (omap_crtc->old_fb) {
361 spin_unlock_irqrestore(&dev->event_lock, flags);
362 dev_err(dev->dev, "already a pending flip\n");
363 return -EINVAL;
364 }
365
366 omap_crtc->event = event;
367 omap_crtc->old_fb = primary->fb = fb;
368
369 spin_unlock_irqrestore(&dev->event_lock, flags);
370
371 /*
372 * Hold a reference temporarily until the crtc is updated
373 * and takes the reference to the bo. This avoids it
374 * getting freed from under us:
375 */
376 bo = omap_framebuffer_bo(fb, 0);
377 drm_gem_object_reference(bo);
378
379 omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);
380
381 return 0;
382}
383
384static int omap_crtc_set_property(struct drm_crtc *crtc,
385 struct drm_property *property, uint64_t val)
386{
387 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
388 struct omap_drm_private *priv = crtc->dev->dev_private;
389
390 if (property == priv->rotation_prop) {
391 crtc->invert_dimensions =
392 !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270)));
393 }
394
395 return omap_plane_set_property(omap_crtc->plane, property, val);
396}
397
398static const struct drm_crtc_funcs omap_crtc_funcs = {
399 .set_config = drm_crtc_helper_set_config,
400 .destroy = omap_crtc_destroy,
401 .page_flip = omap_crtc_page_flip_locked,
402 .set_property = omap_crtc_set_property,
403};
404
405static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
406 .dpms = omap_crtc_dpms,
407 .mode_fixup = omap_crtc_mode_fixup,
408 .mode_set = omap_crtc_mode_set,
409 .prepare = omap_crtc_prepare,
410 .commit = omap_crtc_commit,
411 .mode_set_base = omap_crtc_mode_set_base,
412};
413
414const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
415{
416 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
417 return &omap_crtc->timings;
418}
419
420enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
421{
422 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
423 return omap_crtc->channel;
424}
425
426static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
427{
428 struct omap_crtc *omap_crtc =
429 container_of(irq, struct omap_crtc, error_irq);
430 struct drm_crtc *crtc = &omap_crtc->base;
431 DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
432 /* avoid getting in a flood, unregister the irq until next vblank */
433 __omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
434}
435
436static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
437{
438 struct omap_crtc *omap_crtc =
439 container_of(irq, struct omap_crtc, apply_irq);
440 struct drm_crtc *crtc = &omap_crtc->base;
441
442 if (!omap_crtc->error_irq.registered)
443 __omap_irq_register(crtc->dev, &omap_crtc->error_irq);
444
445 if (!dispc_mgr_go_busy(omap_crtc->channel)) {
446 struct omap_drm_private *priv =
447 crtc->dev->dev_private;
448 DBG("%s: apply done", omap_crtc->name);
449 __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
450 queue_work(priv->wq, &omap_crtc->apply_work);
451 }
452}
453
454static void apply_worker(struct work_struct *work)
455{
456 struct omap_crtc *omap_crtc =
457 container_of(work, struct omap_crtc, apply_work);
458 struct drm_crtc *crtc = &omap_crtc->base;
459 struct drm_device *dev = crtc->dev;
460 struct omap_drm_apply *apply, *n;
461 bool need_apply;
462
463 /*
464 * Synchronize everything on mode_config.mutex, to keep
465 * the callbacks and list modification all serialized
466 * with respect to modesetting ioctls from userspace.
467 */
468 mutex_lock(&crtc->mutex);
469 dispc_runtime_get();
470
471 /*
472 * If we are still pending a previous update, wait.. when the
473 * pending update completes, we get kicked again.
474 */
475 if (omap_crtc->apply_irq.registered)
476 goto out;
477
478 /* finish up previous apply's: */
479 list_for_each_entry_safe(apply, n,
480 &omap_crtc->pending_applies, pending_node) {
481 apply->post_apply(apply);
482 list_del(&apply->pending_node);
483 }
484
485 need_apply = !list_empty(&omap_crtc->queued_applies);
486
487 /* then handle the next round of of queued apply's: */
488 list_for_each_entry_safe(apply, n,
489 &omap_crtc->queued_applies, queued_node) {
490 apply->pre_apply(apply);
491 list_del(&apply->queued_node);
492 apply->queued = false;
493 list_add_tail(&apply->pending_node,
494 &omap_crtc->pending_applies);
495 }
496
497 if (need_apply) {
498 enum omap_channel channel = omap_crtc->channel;
499
500 DBG("%s: GO", omap_crtc->name);
501
502 if (dispc_mgr_is_enabled(channel)) {
503 omap_irq_register(dev, &omap_crtc->apply_irq);
504 dispc_mgr_go(channel);
505 } else {
506 struct omap_drm_private *priv = dev->dev_private;
507 queue_work(priv->wq, &omap_crtc->apply_work);
508 }
509 }
510
511out:
512 dispc_runtime_put();
513 mutex_unlock(&crtc->mutex);
514}
515
516int omap_crtc_apply(struct drm_crtc *crtc,
517 struct omap_drm_apply *apply)
518{
519 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
520
521 WARN_ON(!mutex_is_locked(&crtc->mutex));
522
523 /* no need to queue it again if it is already queued: */
524 if (apply->queued)
525 return 0;
526
527 apply->queued = true;
528 list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);
529
530 /*
531 * If there are no currently pending updates, then go ahead and
532 * kick the worker immediately, otherwise it will run again when
533 * the current update finishes.
534 */
535 if (list_empty(&omap_crtc->pending_applies)) {
536 struct omap_drm_private *priv = crtc->dev->dev_private;
537 queue_work(priv->wq, &omap_crtc->apply_work);
538 }
539
540 return 0;
541}
542
543/* called only from apply */
544static void set_enabled(struct drm_crtc *crtc, bool enable)
545{
546 struct drm_device *dev = crtc->dev;
547 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
548 enum omap_channel channel = omap_crtc->channel;
549 struct omap_irq_wait *wait;
550 u32 framedone_irq, vsync_irq;
551 int ret;
552
553 if (dispc_mgr_is_enabled(channel) == enable)
554 return;
555
556 /*
557 * Digit output produces some sync lost interrupts during the first
558 * frame when enabling, so we need to ignore those.
559 */
560 omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
561
562 framedone_irq = dispc_mgr_get_framedone_irq(channel);
563 vsync_irq = dispc_mgr_get_vsync_irq(channel);
564
565 if (enable) {
566 wait = omap_irq_wait_init(dev, vsync_irq, 1);
567 } else {
568 /*
569 * When we disable the digit output, we need to wait for
570 * FRAMEDONE to know that DISPC has finished with the output.
571 *
572 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
573 * that case we need to use vsync interrupt, and wait for both
574 * even and odd frames.
575 */
576
577 if (framedone_irq)
578 wait = omap_irq_wait_init(dev, framedone_irq, 1);
579 else
580 wait = omap_irq_wait_init(dev, vsync_irq, 2);
581 }
582
583 dispc_mgr_enable(channel, enable);
584
585 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
586 if (ret) {
587 dev_err(dev->dev, "%s: timeout waiting for %s\n",
588 omap_crtc->name, enable ? "enable" : "disable");
589 }
590
591 omap_irq_register(crtc->dev, &omap_crtc->error_irq);
592}
593
594static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
595{
596 struct omap_crtc *omap_crtc =
597 container_of(apply, struct omap_crtc, apply);
598 struct drm_crtc *crtc = &omap_crtc->base;
599 struct drm_encoder *encoder = NULL;
600
601 DBG("%s: enabled=%d, full=%d", omap_crtc->name,
602 omap_crtc->enabled, omap_crtc->full_update);
603
604 if (omap_crtc->full_update) {
605 struct omap_drm_private *priv = crtc->dev->dev_private;
606 int i;
607 for (i = 0; i < priv->num_encoders; i++) {
608 if (priv->encoders[i]->crtc == crtc) {
609 encoder = priv->encoders[i];
610 break;
611 }
612 }
613 }
614
615 if (omap_crtc->current_encoder && encoder != omap_crtc->current_encoder)
616 omap_encoder_set_enabled(omap_crtc->current_encoder, false);
617
618 omap_crtc->current_encoder = encoder;
619
620 if (!omap_crtc->enabled) {
621 if (encoder)
622 omap_encoder_set_enabled(encoder, false);
623 } else {
624 if (encoder) {
625 omap_encoder_set_enabled(encoder, false);
626 omap_encoder_update(encoder, omap_crtc->mgr,
627 &omap_crtc->timings);
628 omap_encoder_set_enabled(encoder, true);
629 }
630 }
631
632 omap_crtc->full_update = false;
633}
634
635static void omap_crtc_post_apply(struct omap_drm_apply *apply)
636{
637 /* nothing needed for post-apply */
638}
639
640void omap_crtc_flush(struct drm_crtc *crtc)
641{
642 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
643 int loops = 0;
644
645 while (!list_empty(&omap_crtc->pending_applies) ||
646 !list_empty(&omap_crtc->queued_applies) ||
647 omap_crtc->event || omap_crtc->old_fb) {
648
649 if (++loops > 10) {
650 dev_err(crtc->dev->dev,
651 "omap_crtc_flush() timeout\n");
652 break;
653 }
654
655 schedule_timeout_uninterruptible(msecs_to_jiffies(20));
656 }
657}
658
659static const char *channel_names[] = {
660 [OMAP_DSS_CHANNEL_LCD] = "lcd",
661 [OMAP_DSS_CHANNEL_DIGIT] = "tv",
662 [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
663 [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
664};
665
666void omap_crtc_pre_init(void)
667{
668 dss_install_mgr_ops(&mgr_ops);
669}
670
671void omap_crtc_pre_uninit(void)
672{
673 dss_uninstall_mgr_ops();
674}
675
676/* initialize crtc */
677struct drm_crtc *omap_crtc_init(struct drm_device *dev,
678 struct drm_plane *plane, enum omap_channel channel, int id)
679{
680 struct drm_crtc *crtc = NULL;
681 struct omap_crtc *omap_crtc;
682 struct omap_overlay_manager_info *info;
683
684 DBG("%s", channel_names[channel]);
685
686 omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
687 if (!omap_crtc)
688 goto fail;
689
690 crtc = &omap_crtc->base;
691
692 INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
693 INIT_WORK(&omap_crtc->apply_work, apply_worker);
694
695 INIT_LIST_HEAD(&omap_crtc->pending_applies);
696 INIT_LIST_HEAD(&omap_crtc->queued_applies);
697
698 omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
699 omap_crtc->apply.post_apply = omap_crtc_post_apply;
700
701 omap_crtc->channel = channel;
702 omap_crtc->plane = plane;
703 omap_crtc->plane->crtc = crtc;
704 omap_crtc->name = channel_names[channel];
705 omap_crtc->pipe = id;
706
707 omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
708 omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
709
710 omap_crtc->error_irq.irqmask =
711 dispc_mgr_get_sync_lost_irq(channel);
712 omap_crtc->error_irq.irq = omap_crtc_error_irq;
713 omap_irq_register(dev, &omap_crtc->error_irq);
714
715 /* temporary: */
716 omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
717
718 /* TODO: fix hard-coded setup.. add properties! */
719 info = &omap_crtc->info;
720 info->default_color = 0x00000000;
721 info->trans_key = 0x00000000;
722 info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
723 info->trans_enabled = false;
724
725 drm_crtc_init(dev, crtc, &omap_crtc_funcs);
726 drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
727
728 omap_plane_install_properties(omap_crtc->plane, &crtc->base);
729
730 omap_crtcs[channel] = omap_crtc;
731
732 return crtc;
733
734fail:
735 if (crtc)
736 omap_crtc_destroy(crtc);
737
738 return NULL;
739}