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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 *
5 * This driver is heavily based upon:
6 *
7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 *
9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
10 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
11 * Portions Copyright (C) 2003 Red Hat Inc
12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
13 *
14 * TODO
15 * Look into engine reset on timeout errors. Should not be required.
16 */
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <scsi/scsi_host.h>
23#include <linux/libata.h>
24
25#define DRV_NAME "pata_hpt37x"
26#define DRV_VERSION "0.6.30"
27
28struct hpt_clock {
29 u8 xfer_speed;
30 u32 timing;
31};
32
33struct hpt_chip {
34 const char *name;
35 unsigned int base;
36 struct hpt_clock const *clocks[4];
37};
38
39/* key for bus clock timings
40 * bit
41 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
42 * cycles = value + 1
43 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
44 * cycles = value + 1
45 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
46 * register access.
47 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
48 * register access.
49 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
50 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
51 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
52 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
53 * register access.
54 * 28 UDMA enable.
55 * 29 DMA enable.
56 * 30 PIO_MST enable. If set, the chip is in bus master mode during
57 * PIO xfer.
58 * 31 FIFO enable. Only for PIO.
59 */
60
61static struct hpt_clock hpt37x_timings_33[] = {
62 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
63 { XFER_UDMA_5, 0x12446231 },
64 { XFER_UDMA_4, 0x12446231 },
65 { XFER_UDMA_3, 0x126c6231 },
66 { XFER_UDMA_2, 0x12486231 },
67 { XFER_UDMA_1, 0x124c6233 },
68 { XFER_UDMA_0, 0x12506297 },
69
70 { XFER_MW_DMA_2, 0x22406c31 },
71 { XFER_MW_DMA_1, 0x22406c33 },
72 { XFER_MW_DMA_0, 0x22406c97 },
73
74 { XFER_PIO_4, 0x06414e31 },
75 { XFER_PIO_3, 0x06414e42 },
76 { XFER_PIO_2, 0x06414e53 },
77 { XFER_PIO_1, 0x06814e93 },
78 { XFER_PIO_0, 0x06814ea7 }
79};
80
81static struct hpt_clock hpt37x_timings_50[] = {
82 { XFER_UDMA_6, 0x12848242 },
83 { XFER_UDMA_5, 0x12848242 },
84 { XFER_UDMA_4, 0x12ac8242 },
85 { XFER_UDMA_3, 0x128c8242 },
86 { XFER_UDMA_2, 0x120c8242 },
87 { XFER_UDMA_1, 0x12148254 },
88 { XFER_UDMA_0, 0x121882ea },
89
90 { XFER_MW_DMA_2, 0x22808242 },
91 { XFER_MW_DMA_1, 0x22808254 },
92 { XFER_MW_DMA_0, 0x228082ea },
93
94 { XFER_PIO_4, 0x0a81f442 },
95 { XFER_PIO_3, 0x0a81f443 },
96 { XFER_PIO_2, 0x0a81f454 },
97 { XFER_PIO_1, 0x0ac1f465 },
98 { XFER_PIO_0, 0x0ac1f48a }
99};
100
101static struct hpt_clock hpt37x_timings_66[] = {
102 { XFER_UDMA_6, 0x1c869c62 },
103 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
104 { XFER_UDMA_4, 0x1c8a9c62 },
105 { XFER_UDMA_3, 0x1c8e9c62 },
106 { XFER_UDMA_2, 0x1c929c62 },
107 { XFER_UDMA_1, 0x1c9a9c62 },
108 { XFER_UDMA_0, 0x1c829c62 },
109
110 { XFER_MW_DMA_2, 0x2c829c62 },
111 { XFER_MW_DMA_1, 0x2c829c66 },
112 { XFER_MW_DMA_0, 0x2c829d2e },
113
114 { XFER_PIO_4, 0x0c829c62 },
115 { XFER_PIO_3, 0x0c829c84 },
116 { XFER_PIO_2, 0x0c829ca6 },
117 { XFER_PIO_1, 0x0d029d26 },
118 { XFER_PIO_0, 0x0d029d5e }
119};
120
121
122static const struct hpt_chip hpt370 = {
123 "HPT370",
124 48,
125 {
126 hpt37x_timings_33,
127 NULL,
128 NULL,
129 NULL
130 }
131};
132
133static const struct hpt_chip hpt370a = {
134 "HPT370A",
135 48,
136 {
137 hpt37x_timings_33,
138 NULL,
139 hpt37x_timings_50,
140 NULL
141 }
142};
143
144static const struct hpt_chip hpt372 = {
145 "HPT372",
146 55,
147 {
148 hpt37x_timings_33,
149 NULL,
150 hpt37x_timings_50,
151 hpt37x_timings_66
152 }
153};
154
155static const struct hpt_chip hpt302 = {
156 "HPT302",
157 66,
158 {
159 hpt37x_timings_33,
160 NULL,
161 hpt37x_timings_50,
162 hpt37x_timings_66
163 }
164};
165
166static const struct hpt_chip hpt371 = {
167 "HPT371",
168 66,
169 {
170 hpt37x_timings_33,
171 NULL,
172 hpt37x_timings_50,
173 hpt37x_timings_66
174 }
175};
176
177static const struct hpt_chip hpt372a = {
178 "HPT372A",
179 66,
180 {
181 hpt37x_timings_33,
182 NULL,
183 hpt37x_timings_50,
184 hpt37x_timings_66
185 }
186};
187
188static const struct hpt_chip hpt374 = {
189 "HPT374",
190 48,
191 {
192 hpt37x_timings_33,
193 NULL,
194 NULL,
195 NULL
196 }
197};
198
199/**
200 * hpt37x_find_mode - reset the hpt37x bus
201 * @ap: ATA port
202 * @speed: transfer mode
203 *
204 * Return the 32bit register programming information for this channel
205 * that matches the speed provided.
206 */
207
208static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
209{
210 struct hpt_clock *clocks = ap->host->private_data;
211
212 while (clocks->xfer_speed) {
213 if (clocks->xfer_speed == speed)
214 return clocks->timing;
215 clocks++;
216 }
217 BUG();
218 return 0xffffffffU; /* silence compiler warning */
219}
220
221static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
222 const char * const list[])
223{
224 unsigned char model_num[ATA_ID_PROD_LEN + 1];
225 int i;
226
227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
228
229 i = match_string(list, -1, model_num);
230 if (i >= 0) {
231 ata_dev_warn(dev, "%s is not supported for %s\n",
232 modestr, list[i]);
233 return 1;
234 }
235 return 0;
236}
237
238static const char * const bad_ata33[] = {
239 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
240 "Maxtor 90845U3", "Maxtor 90650U2",
241 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
242 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
244 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
248 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
249 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
250 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
251 NULL
252};
253
254static const char * const bad_ata100_5[] = {
255 "IBM-DTLA-307075",
256 "IBM-DTLA-307060",
257 "IBM-DTLA-307045",
258 "IBM-DTLA-307030",
259 "IBM-DTLA-307020",
260 "IBM-DTLA-307015",
261 "IBM-DTLA-305040",
262 "IBM-DTLA-305030",
263 "IBM-DTLA-305020",
264 "IC35L010AVER07-0",
265 "IC35L020AVER07-0",
266 "IC35L030AVER07-0",
267 "IC35L040AVER07-0",
268 "IC35L060AVER07-0",
269 "WDC AC310200R",
270 NULL
271};
272
273/**
274 * hpt370_filter - mode selection filter
275 * @adev: ATA device
276 * @mask: mode mask
277 *
278 * Block UDMA on devices that cause trouble with this controller.
279 */
280
281static unsigned int hpt370_filter(struct ata_device *adev, unsigned int mask)
282{
283 if (adev->class == ATA_DEV_ATA) {
284 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
285 mask &= ~ATA_MASK_UDMA;
286 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
287 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
288 }
289 return mask;
290}
291
292/**
293 * hpt370a_filter - mode selection filter
294 * @adev: ATA device
295 * @mask: mode mask
296 *
297 * Block UDMA on devices that cause trouble with this controller.
298 */
299
300static unsigned int hpt370a_filter(struct ata_device *adev, unsigned int mask)
301{
302 if (adev->class == ATA_DEV_ATA) {
303 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
304 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
305 }
306 return mask;
307}
308
309/**
310 * hpt372_filter - mode selection filter
311 * @adev: ATA device
312 * @mask: mode mask
313 *
314 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
315 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
316 */
317static unsigned int hpt372_filter(struct ata_device *adev, unsigned int mask)
318{
319 if (ata_id_is_sata(adev->id))
320 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
321
322 return mask;
323}
324
325/**
326 * hpt37x_cable_detect - Detect the cable type
327 * @ap: ATA port to detect on
328 *
329 * Return the cable type attached to this port
330 */
331
332static int hpt37x_cable_detect(struct ata_port *ap)
333{
334 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
335 u8 scr2, ata66;
336
337 pci_read_config_byte(pdev, 0x5B, &scr2);
338 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
339
340 udelay(10); /* debounce */
341
342 /* Cable register now active */
343 pci_read_config_byte(pdev, 0x5A, &ata66);
344 /* Restore state */
345 pci_write_config_byte(pdev, 0x5B, scr2);
346
347 if (ata66 & (2 >> ap->port_no))
348 return ATA_CBL_PATA40;
349 else
350 return ATA_CBL_PATA80;
351}
352
353/**
354 * hpt374_fn1_cable_detect - Detect the cable type
355 * @ap: ATA port to detect on
356 *
357 * Return the cable type attached to this port
358 */
359
360static int hpt374_fn1_cable_detect(struct ata_port *ap)
361{
362 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
363 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
364 u16 mcr3;
365 u8 ata66;
366
367 /* Do the extra channel work */
368 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
369 /* Set bit 15 of 0x52 to enable TCBLID as input */
370 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
371 pci_read_config_byte(pdev, 0x5A, &ata66);
372 /* Reset TCBLID/FCBLID to output */
373 pci_write_config_word(pdev, mcrbase + 2, mcr3);
374
375 if (ata66 & (2 >> ap->port_no))
376 return ATA_CBL_PATA40;
377 else
378 return ATA_CBL_PATA80;
379}
380
381/**
382 * hpt37x_pre_reset - reset the hpt37x bus
383 * @link: ATA link to reset
384 * @deadline: deadline jiffies for the operation
385 *
386 * Perform the initial reset handling for the HPT37x.
387 */
388
389static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
390{
391 struct ata_port *ap = link->ap;
392 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
393 static const struct pci_bits hpt37x_enable_bits[] = {
394 { 0x50, 1, 0x04, 0x04 },
395 { 0x54, 1, 0x04, 0x04 }
396 };
397 u8 mcr2;
398
399 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
400 return -ENOENT;
401
402 /* Reset the state machine */
403 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
404 udelay(100);
405
406 /*
407 * Disable the "fast interrupt" prediction. Don't hold off
408 * on interrupts. (== 0x01 despite what the docs say)
409 */
410 pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
411 /* Is it HPT370/A? */
412 if (pdev->device == PCI_DEVICE_ID_TTI_HPT366 && pdev->revision < 5) {
413 mcr2 &= ~0x02;
414 mcr2 |= 0x01;
415 } else {
416 mcr2 &= ~0x07;
417 }
418 pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
419
420 return ata_sff_prereset(link, deadline);
421}
422
423static void hpt37x_set_mode(struct ata_port *ap, struct ata_device *adev,
424 u8 mode)
425{
426 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
427 int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
428 u32 reg, timing, mask;
429
430 /* Determine timing mask and find matching mode entry */
431 if (mode < XFER_MW_DMA_0)
432 mask = 0xcfc3ffff;
433 else if (mode < XFER_UDMA_0)
434 mask = 0x31c001ff;
435 else
436 mask = 0x303c0000;
437
438 timing = hpt37x_find_mode(ap, mode);
439
440 pci_read_config_dword(pdev, addr, ®);
441 reg = (reg & ~mask) | (timing & mask);
442 pci_write_config_dword(pdev, addr, reg);
443}
444/**
445 * hpt37x_set_piomode - PIO setup
446 * @ap: ATA interface
447 * @adev: device on the interface
448 *
449 * Perform PIO mode setup.
450 */
451
452static void hpt37x_set_piomode(struct ata_port *ap, struct ata_device *adev)
453{
454 hpt37x_set_mode(ap, adev, adev->pio_mode);
455}
456
457/**
458 * hpt37x_set_dmamode - DMA timing setup
459 * @ap: ATA interface
460 * @adev: Device being configured
461 *
462 * Set up the channel for MWDMA or UDMA modes.
463 */
464
465static void hpt37x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
466{
467 hpt37x_set_mode(ap, adev, adev->dma_mode);
468}
469
470/**
471 * hpt370_bmdma_stop - DMA engine stop
472 * @qc: ATA command
473 *
474 * Work around the HPT370 DMA engine.
475 */
476
477static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
478{
479 struct ata_port *ap = qc->ap;
480 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
481 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
482 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
483 u8 dma_cmd;
484
485 if (dma_stat & ATA_DMA_ACTIVE) {
486 udelay(20);
487 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
488 }
489 if (dma_stat & ATA_DMA_ACTIVE) {
490 /* Clear the engine */
491 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
492 udelay(10);
493 /* Stop DMA */
494 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
495 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
496 /* Clear Error */
497 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
498 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
499 bmdma + ATA_DMA_STATUS);
500 /* Clear the engine */
501 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
502 udelay(10);
503 }
504 ata_bmdma_stop(qc);
505}
506
507/**
508 * hpt37x_bmdma_stop - DMA engine stop
509 * @qc: ATA command
510 *
511 * Clean up after the HPT372 and later DMA engine
512 */
513
514static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
515{
516 struct ata_port *ap = qc->ap;
517 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
518 int mscreg = 0x50 + 4 * ap->port_no;
519 u8 bwsr_stat, msc_stat;
520
521 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
522 pci_read_config_byte(pdev, mscreg, &msc_stat);
523 if (bwsr_stat & (1 << ap->port_no))
524 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
525 ata_bmdma_stop(qc);
526}
527
528
529static const struct scsi_host_template hpt37x_sht = {
530 ATA_BMDMA_SHT(DRV_NAME),
531};
532
533/*
534 * Configuration for HPT370
535 */
536
537static struct ata_port_operations hpt370_port_ops = {
538 .inherits = &ata_bmdma_port_ops,
539
540 .bmdma_stop = hpt370_bmdma_stop,
541
542 .mode_filter = hpt370_filter,
543 .cable_detect = hpt37x_cable_detect,
544 .set_piomode = hpt37x_set_piomode,
545 .set_dmamode = hpt37x_set_dmamode,
546 .prereset = hpt37x_pre_reset,
547};
548
549/*
550 * Configuration for HPT370A. Close to 370 but less filters
551 */
552
553static struct ata_port_operations hpt370a_port_ops = {
554 .inherits = &hpt370_port_ops,
555 .mode_filter = hpt370a_filter,
556};
557
558/*
559 * Configuration for HPT371 and HPT302.
560 */
561
562static struct ata_port_operations hpt302_port_ops = {
563 .inherits = &ata_bmdma_port_ops,
564
565 .bmdma_stop = hpt37x_bmdma_stop,
566
567 .cable_detect = hpt37x_cable_detect,
568 .set_piomode = hpt37x_set_piomode,
569 .set_dmamode = hpt37x_set_dmamode,
570 .prereset = hpt37x_pre_reset,
571};
572
573/*
574 * Configuration for HPT372. Mode setting works like 371 and 302
575 * but we have a mode filter.
576 */
577
578static struct ata_port_operations hpt372_port_ops = {
579 .inherits = &hpt302_port_ops,
580 .mode_filter = hpt372_filter,
581};
582
583/*
584 * Configuration for HPT374. Mode setting and filtering works like 372
585 * but we have a different cable detection procedure for function 1.
586 */
587
588static struct ata_port_operations hpt374_fn1_port_ops = {
589 .inherits = &hpt372_port_ops,
590 .cable_detect = hpt374_fn1_cable_detect,
591};
592
593/**
594 * hpt37x_clock_slot - Turn timing to PC clock entry
595 * @freq: Reported frequency in MHz
596 *
597 * Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
598 * and 3 for 66Mhz)
599 */
600
601static int hpt37x_clock_slot(unsigned int freq)
602{
603 if (freq < 40)
604 return 0; /* 33Mhz slot */
605 if (freq < 45)
606 return 1; /* 40Mhz slot */
607 if (freq < 55)
608 return 2; /* 50Mhz slot */
609 return 3; /* 60Mhz slot */
610}
611
612/**
613 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
614 * @dev: PCI device
615 *
616 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
617 * succeeds
618 */
619
620static int hpt37x_calibrate_dpll(struct pci_dev *dev)
621{
622 u8 reg5b;
623 u32 reg5c;
624 int tries;
625
626 for (tries = 0; tries < 0x5000; tries++) {
627 udelay(50);
628 pci_read_config_byte(dev, 0x5b, ®5b);
629 if (reg5b & 0x80) {
630 /* See if it stays set */
631 for (tries = 0; tries < 0x1000; tries++) {
632 pci_read_config_byte(dev, 0x5b, ®5b);
633 /* Failed ? */
634 if ((reg5b & 0x80) == 0)
635 return 0;
636 }
637 /* Turn off tuning, we have the DPLL set */
638 pci_read_config_dword(dev, 0x5c, ®5c);
639 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
640 return 1;
641 }
642 }
643 /* Never went stable */
644 return 0;
645}
646
647static int hpt37x_pci_clock(struct pci_dev *pdev, unsigned int base)
648{
649 unsigned int freq;
650 u32 fcnt;
651
652 /*
653 * Some devices do not let this value be accessed via PCI space
654 * according to the old driver. In addition we must use the value
655 * from FN 0 on the HPT374.
656 */
657 if (pdev->device == PCI_DEVICE_ID_TTI_HPT374 &&
658 (PCI_FUNC(pdev->devfn) & 1)) {
659 struct pci_dev *pdev_fn0;
660
661 pdev_fn0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
662 /* Someone hot plugged the controller on us? */
663 if (!pdev_fn0)
664 return 0;
665 fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90);
666 pci_dev_put(pdev_fn0);
667 } else {
668 fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
669 }
670
671 if ((fcnt >> 12) != 0xABCDE) {
672 u32 total = 0;
673 int i;
674 u16 sr;
675
676 dev_warn(&pdev->dev, "BIOS clock data not set\n");
677
678 /* This is the process the HPT371 BIOS is reported to use */
679 for (i = 0; i < 128; i++) {
680 pci_read_config_word(pdev, 0x78, &sr);
681 total += sr & 0x1FF;
682 udelay(15);
683 }
684 fcnt = total / 128;
685 }
686 fcnt &= 0x1FF;
687
688 freq = (fcnt * base) / 192; /* in MHz */
689
690 /* Clamp to bands */
691 if (freq < 40)
692 return 33;
693 if (freq < 45)
694 return 40;
695 if (freq < 55)
696 return 50;
697 return 66;
698}
699
700/**
701 * hpt37x_init_one - Initialise an HPT37X/302
702 * @dev: PCI device
703 * @id: Entry in match table
704 *
705 * Initialise an HPT37x device. There are some interesting complications
706 * here. Firstly the chip may report 366 and be one of several variants.
707 * Secondly all the timings depend on the clock for the chip which we must
708 * detect and look up
709 *
710 * This is the known chip mappings. It may be missing a couple of later
711 * releases.
712 *
713 * Chip version PCI Rev Notes
714 * HPT366 4 (HPT366) 0 Other driver
715 * HPT366 4 (HPT366) 1 Other driver
716 * HPT368 4 (HPT366) 2 Other driver
717 * HPT370 4 (HPT366) 3 UDMA100
718 * HPT370A 4 (HPT366) 4 UDMA100
719 * HPT372 4 (HPT366) 5 UDMA133 (1)
720 * HPT372N 4 (HPT366) 6 Other driver
721 * HPT372A 5 (HPT372) 1 UDMA133 (1)
722 * HPT372N 5 (HPT372) 2 Other driver
723 * HPT302 6 (HPT302) 1 UDMA133
724 * HPT302N 6 (HPT302) 2 Other driver
725 * HPT371 7 (HPT371) * UDMA133
726 * HPT374 8 (HPT374) * UDMA133 4 channel
727 * HPT372N 9 (HPT372N) * Other driver
728 *
729 * (1) UDMA133 support depends on the bus clock
730 */
731
732static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
733{
734 /* HPT370 - UDMA100 */
735 static const struct ata_port_info info_hpt370 = {
736 .flags = ATA_FLAG_SLAVE_POSS,
737 .pio_mask = ATA_PIO4,
738 .mwdma_mask = ATA_MWDMA2,
739 .udma_mask = ATA_UDMA5,
740 .port_ops = &hpt370_port_ops
741 };
742 /* HPT370A - UDMA100 */
743 static const struct ata_port_info info_hpt370a = {
744 .flags = ATA_FLAG_SLAVE_POSS,
745 .pio_mask = ATA_PIO4,
746 .mwdma_mask = ATA_MWDMA2,
747 .udma_mask = ATA_UDMA5,
748 .port_ops = &hpt370a_port_ops
749 };
750 /* HPT370 - UDMA66 */
751 static const struct ata_port_info info_hpt370_33 = {
752 .flags = ATA_FLAG_SLAVE_POSS,
753 .pio_mask = ATA_PIO4,
754 .mwdma_mask = ATA_MWDMA2,
755 .udma_mask = ATA_UDMA4,
756 .port_ops = &hpt370_port_ops
757 };
758 /* HPT370A - UDMA66 */
759 static const struct ata_port_info info_hpt370a_33 = {
760 .flags = ATA_FLAG_SLAVE_POSS,
761 .pio_mask = ATA_PIO4,
762 .mwdma_mask = ATA_MWDMA2,
763 .udma_mask = ATA_UDMA4,
764 .port_ops = &hpt370a_port_ops
765 };
766 /* HPT372 - UDMA133 */
767 static const struct ata_port_info info_hpt372 = {
768 .flags = ATA_FLAG_SLAVE_POSS,
769 .pio_mask = ATA_PIO4,
770 .mwdma_mask = ATA_MWDMA2,
771 .udma_mask = ATA_UDMA6,
772 .port_ops = &hpt372_port_ops
773 };
774 /* HPT371, 302 - UDMA133 */
775 static const struct ata_port_info info_hpt302 = {
776 .flags = ATA_FLAG_SLAVE_POSS,
777 .pio_mask = ATA_PIO4,
778 .mwdma_mask = ATA_MWDMA2,
779 .udma_mask = ATA_UDMA6,
780 .port_ops = &hpt302_port_ops
781 };
782 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
783 static const struct ata_port_info info_hpt374_fn0 = {
784 .flags = ATA_FLAG_SLAVE_POSS,
785 .pio_mask = ATA_PIO4,
786 .mwdma_mask = ATA_MWDMA2,
787 .udma_mask = ATA_UDMA5,
788 .port_ops = &hpt372_port_ops
789 };
790 static const struct ata_port_info info_hpt374_fn1 = {
791 .flags = ATA_FLAG_SLAVE_POSS,
792 .pio_mask = ATA_PIO4,
793 .mwdma_mask = ATA_MWDMA2,
794 .udma_mask = ATA_UDMA5,
795 .port_ops = &hpt374_fn1_port_ops
796 };
797
798 static const int MHz[4] = { 33, 40, 50, 66 };
799 void *private_data = NULL;
800 const struct ata_port_info *ppi[] = { NULL, NULL };
801 u8 rev = dev->revision;
802 u8 irqmask;
803 u8 mcr1;
804 unsigned int freq; /* MHz */
805 int prefer_dpll = 1;
806
807 unsigned long iobase = pci_resource_start(dev, 4);
808
809 const struct hpt_chip *chip_table;
810 int clock_slot;
811 int rc;
812
813 rc = pcim_enable_device(dev);
814 if (rc)
815 return rc;
816
817 switch (dev->device) {
818 case PCI_DEVICE_ID_TTI_HPT366:
819 /* May be a later chip in disguise. Check */
820 /* Older chips are in the HPT366 driver. Ignore them */
821 if (rev < 3)
822 return -ENODEV;
823 /* N series chips have their own driver. Ignore */
824 if (rev == 6)
825 return -ENODEV;
826
827 switch (rev) {
828 case 3:
829 ppi[0] = &info_hpt370;
830 chip_table = &hpt370;
831 prefer_dpll = 0;
832 break;
833 case 4:
834 ppi[0] = &info_hpt370a;
835 chip_table = &hpt370a;
836 prefer_dpll = 0;
837 break;
838 case 5:
839 ppi[0] = &info_hpt372;
840 chip_table = &hpt372;
841 break;
842 default:
843 dev_err(&dev->dev,
844 "Unknown HPT366 subtype, please report (%d)\n",
845 rev);
846 return -ENODEV;
847 }
848 break;
849 case PCI_DEVICE_ID_TTI_HPT372:
850 /* 372N if rev >= 2 */
851 if (rev >= 2)
852 return -ENODEV;
853 ppi[0] = &info_hpt372;
854 chip_table = &hpt372a;
855 break;
856 case PCI_DEVICE_ID_TTI_HPT302:
857 /* 302N if rev > 1 */
858 if (rev > 1)
859 return -ENODEV;
860 ppi[0] = &info_hpt302;
861 /* Check this */
862 chip_table = &hpt302;
863 break;
864 case PCI_DEVICE_ID_TTI_HPT371:
865 if (rev > 1)
866 return -ENODEV;
867 ppi[0] = &info_hpt302;
868 chip_table = &hpt371;
869 /*
870 * Single channel device, master is not present but the BIOS
871 * (or us for non x86) must mark it absent
872 */
873 pci_read_config_byte(dev, 0x50, &mcr1);
874 mcr1 &= ~0x04;
875 pci_write_config_byte(dev, 0x50, mcr1);
876 break;
877 case PCI_DEVICE_ID_TTI_HPT374:
878 chip_table = &hpt374;
879 if (!(PCI_FUNC(dev->devfn) & 1))
880 *ppi = &info_hpt374_fn0;
881 else
882 *ppi = &info_hpt374_fn1;
883 break;
884 default:
885 dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n",
886 dev->device);
887 return -ENODEV;
888 }
889 /* Ok so this is a chip we support */
890
891 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
892 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
893 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
894 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
895
896 pci_read_config_byte(dev, 0x5A, &irqmask);
897 irqmask &= ~0x10;
898 pci_write_config_byte(dev, 0x5a, irqmask);
899
900 /*
901 * HPT371 chips physically have only one channel, the secondary one,
902 * but the primary channel registers do exist! Go figure...
903 * So, we manually disable the non-existing channel here
904 * (if the BIOS hasn't done this already).
905 */
906 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
907 u8 mcr1;
908
909 pci_read_config_byte(dev, 0x50, &mcr1);
910 mcr1 &= ~0x04;
911 pci_write_config_byte(dev, 0x50, mcr1);
912 }
913
914 /*
915 * default to pci clock. make sure MA15/16 are set to output
916 * to prevent drives having problems with 40-pin cables. Needed
917 * for some drives such as IBM-DTLA which will not enter ready
918 * state on reset when PDIAG is a input.
919 */
920
921 pci_write_config_byte(dev, 0x5b, 0x23);
922
923 /*
924 * HighPoint does this for HPT372A.
925 * NOTE: This register is only writeable via I/O space.
926 */
927 if (chip_table == &hpt372a)
928 outb(0x0e, iobase + 0x9c);
929
930 freq = hpt37x_pci_clock(dev, chip_table->base);
931 if (!freq)
932 return -ENODEV;
933
934 /*
935 * Turn the frequency check into a band and then find a timing
936 * table to match it.
937 */
938
939 clock_slot = hpt37x_clock_slot(freq);
940 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
941 /*
942 * We need to try PLL mode instead
943 *
944 * For non UDMA133 capable devices we should
945 * use a 50MHz DPLL by choice
946 */
947 unsigned int f_low, f_high;
948 int dpll, adjust;
949
950 /* Compute DPLL */
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
952
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
954 f_high = f_low + 2;
955 if (clock_slot > 1)
956 f_high += 2;
957
958 /* Select the DPLL clock. */
959 pci_write_config_byte(dev, 0x5b, 0x21);
960 pci_write_config_dword(dev, 0x5C,
961 (f_high << 16) | f_low | 0x100);
962
963 for (adjust = 0; adjust < 8; adjust++) {
964 if (hpt37x_calibrate_dpll(dev))
965 break;
966 /*
967 * See if it'll settle at a fractionally
968 * different clock
969 */
970 if (adjust & 1)
971 f_low -= adjust >> 1;
972 else
973 f_high += adjust >> 1;
974 pci_write_config_dword(dev, 0x5C,
975 (f_high << 16) | f_low | 0x100);
976 }
977 if (adjust == 8) {
978 dev_err(&dev->dev, "DPLL did not stabilize!\n");
979 return -ENODEV;
980 }
981 if (dpll == 3)
982 private_data = (void *)hpt37x_timings_66;
983 else
984 private_data = (void *)hpt37x_timings_50;
985
986 dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n",
987 MHz[clock_slot], MHz[dpll]);
988 } else {
989 private_data = (void *)chip_table->clocks[clock_slot];
990 /*
991 * Perform a final fixup. Note that we will have used the
992 * DPLL on the HPT372 which means we don't have to worry
993 * about lack of UDMA133 support on lower clocks
994 */
995
996 if (clock_slot < 2 && ppi[0] == &info_hpt370)
997 ppi[0] = &info_hpt370_33;
998 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
999 ppi[0] = &info_hpt370a_33;
1000
1001 dev_info(&dev->dev, "%s using %dMHz bus clock\n",
1002 chip_table->name, MHz[clock_slot]);
1003 }
1004
1005 /* Now kick off ATA set up */
1006 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1007}
1008
1009static const struct pci_device_id hpt37x[] = {
1010 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1011 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1012 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1013 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1014 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1015
1016 { },
1017};
1018
1019static struct pci_driver hpt37x_pci_driver = {
1020 .name = DRV_NAME,
1021 .id_table = hpt37x,
1022 .probe = hpt37x_init_one,
1023 .remove = ata_pci_remove_one
1024};
1025
1026module_pci_driver(hpt37x_pci_driver);
1027
1028MODULE_AUTHOR("Alan Cox");
1029MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1030MODULE_LICENSE("GPL");
1031MODULE_DEVICE_TABLE(pci, hpt37x);
1032MODULE_VERSION(DRV_VERSION);
1/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
12 *
13 * TODO
14 * Look into engine reset on timeout errors. Should not be required.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt37x"
28#define DRV_VERSION "0.6.23"
29
30struct hpt_clock {
31 u8 xfer_speed;
32 u32 timing;
33};
34
35struct hpt_chip {
36 const char *name;
37 unsigned int base;
38 struct hpt_clock const *clocks[4];
39};
40
41/* key for bus clock timings
42 * bit
43 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
44 * cycles = value + 1
45 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
46 * cycles = value + 1
47 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
48 * register access.
49 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
50 * register access.
51 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
52 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
53 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
54 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
55 * register access.
56 * 28 UDMA enable.
57 * 29 DMA enable.
58 * 30 PIO_MST enable. If set, the chip is in bus master mode during
59 * PIO xfer.
60 * 31 FIFO enable. Only for PIO.
61 */
62
63static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
71
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
75
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
81};
82
83static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
91
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
95
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
101};
102
103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
111
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
115
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
121};
122
123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
128 hpt37x_timings_33,
129 NULL,
130 NULL,
131 NULL
132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
139 hpt37x_timings_33,
140 NULL,
141 hpt37x_timings_50,
142 NULL
143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
150 hpt37x_timings_33,
151 NULL,
152 hpt37x_timings_50,
153 hpt37x_timings_66
154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
161 hpt37x_timings_33,
162 NULL,
163 hpt37x_timings_50,
164 hpt37x_timings_66
165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
172 hpt37x_timings_33,
173 NULL,
174 hpt37x_timings_50,
175 hpt37x_timings_66
176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
183 hpt37x_timings_33,
184 NULL,
185 hpt37x_timings_50,
186 hpt37x_timings_66
187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
194 hpt37x_timings_33,
195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201/**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
209
210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while (clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
224 const char * const list[])
225{
226 unsigned char model_num[ATA_ID_PROD_LEN + 1];
227 int i = 0;
228
229 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
230
231 while (list[i] != NULL) {
232 if (!strcmp(list[i], model_num)) {
233 pr_warn("%s is not supported for %s\n",
234 modestr, list[i]);
235 return 1;
236 }
237 i++;
238 }
239 return 0;
240}
241
242static const char * const bad_ata33[] = {
243 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
244 "Maxtor 90845U3", "Maxtor 90650U2",
245 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
246 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
247 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
248 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
249 "Maxtor 90510D4",
250 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
251 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
252 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
253 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
254 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
255 NULL
256};
257
258static const char * const bad_ata100_5[] = {
259 "IBM-DTLA-307075",
260 "IBM-DTLA-307060",
261 "IBM-DTLA-307045",
262 "IBM-DTLA-307030",
263 "IBM-DTLA-307020",
264 "IBM-DTLA-307015",
265 "IBM-DTLA-305040",
266 "IBM-DTLA-305030",
267 "IBM-DTLA-305020",
268 "IC35L010AVER07-0",
269 "IC35L020AVER07-0",
270 "IC35L030AVER07-0",
271 "IC35L040AVER07-0",
272 "IC35L060AVER07-0",
273 "WDC AC310200R",
274 NULL
275};
276
277/**
278 * hpt370_filter - mode selection filter
279 * @adev: ATA device
280 *
281 * Block UDMA on devices that cause trouble with this controller.
282 */
283
284static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
285{
286 if (adev->class == ATA_DEV_ATA) {
287 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
288 mask &= ~ATA_MASK_UDMA;
289 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
290 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
291 }
292 return mask;
293}
294
295/**
296 * hpt370a_filter - mode selection filter
297 * @adev: ATA device
298 *
299 * Block UDMA on devices that cause trouble with this controller.
300 */
301
302static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
303{
304 if (adev->class == ATA_DEV_ATA) {
305 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
306 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
307 }
308 return mask;
309}
310
311/**
312 * hpt372_filter - mode selection filter
313 * @adev: ATA device
314 * @mask: mode mask
315 *
316 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
317 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
318 */
319static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
320{
321 if (ata_id_is_sata(adev->id))
322 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
323
324 return mask;
325}
326
327/**
328 * hpt37x_cable_detect - Detect the cable type
329 * @ap: ATA port to detect on
330 *
331 * Return the cable type attached to this port
332 */
333
334static int hpt37x_cable_detect(struct ata_port *ap)
335{
336 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
337 u8 scr2, ata66;
338
339 pci_read_config_byte(pdev, 0x5B, &scr2);
340 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
341
342 udelay(10); /* debounce */
343
344 /* Cable register now active */
345 pci_read_config_byte(pdev, 0x5A, &ata66);
346 /* Restore state */
347 pci_write_config_byte(pdev, 0x5B, scr2);
348
349 if (ata66 & (2 >> ap->port_no))
350 return ATA_CBL_PATA40;
351 else
352 return ATA_CBL_PATA80;
353}
354
355/**
356 * hpt374_fn1_cable_detect - Detect the cable type
357 * @ap: ATA port to detect on
358 *
359 * Return the cable type attached to this port
360 */
361
362static int hpt374_fn1_cable_detect(struct ata_port *ap)
363{
364 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
365 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
366 u16 mcr3;
367 u8 ata66;
368
369 /* Do the extra channel work */
370 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
371 /* Set bit 15 of 0x52 to enable TCBLID as input */
372 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
373 pci_read_config_byte(pdev, 0x5A, &ata66);
374 /* Reset TCBLID/FCBLID to output */
375 pci_write_config_word(pdev, mcrbase + 2, mcr3);
376
377 if (ata66 & (2 >> ap->port_no))
378 return ATA_CBL_PATA40;
379 else
380 return ATA_CBL_PATA80;
381}
382
383/**
384 * hpt37x_pre_reset - reset the hpt37x bus
385 * @link: ATA link to reset
386 * @deadline: deadline jiffies for the operation
387 *
388 * Perform the initial reset handling for the HPT37x.
389 */
390
391static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
392{
393 struct ata_port *ap = link->ap;
394 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
395 static const struct pci_bits hpt37x_enable_bits[] = {
396 { 0x50, 1, 0x04, 0x04 },
397 { 0x54, 1, 0x04, 0x04 }
398 };
399
400 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
401 return -ENOENT;
402
403 /* Reset the state machine */
404 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
405 udelay(100);
406
407 return ata_sff_prereset(link, deadline);
408}
409
410static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
411 u8 mode)
412{
413 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
414 u32 addr1, addr2;
415 u32 reg, timing, mask;
416 u8 fast;
417
418 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
419 addr2 = 0x51 + 4 * ap->port_no;
420
421 /* Fast interrupt prediction disable, hold off interrupt disable */
422 pci_read_config_byte(pdev, addr2, &fast);
423 fast &= ~0x02;
424 fast |= 0x01;
425 pci_write_config_byte(pdev, addr2, fast);
426
427 /* Determine timing mask and find matching mode entry */
428 if (mode < XFER_MW_DMA_0)
429 mask = 0xcfc3ffff;
430 else if (mode < XFER_UDMA_0)
431 mask = 0x31c001ff;
432 else
433 mask = 0x303c0000;
434
435 timing = hpt37x_find_mode(ap, mode);
436
437 pci_read_config_dword(pdev, addr1, ®);
438 reg = (reg & ~mask) | (timing & mask);
439 pci_write_config_dword(pdev, addr1, reg);
440}
441/**
442 * hpt370_set_piomode - PIO setup
443 * @ap: ATA interface
444 * @adev: device on the interface
445 *
446 * Perform PIO mode setup.
447 */
448
449static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
450{
451 hpt370_set_mode(ap, adev, adev->pio_mode);
452}
453
454/**
455 * hpt370_set_dmamode - DMA timing setup
456 * @ap: ATA interface
457 * @adev: Device being configured
458 *
459 * Set up the channel for MWDMA or UDMA modes.
460 */
461
462static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
463{
464 hpt370_set_mode(ap, adev, adev->dma_mode);
465}
466
467/**
468 * hpt370_bmdma_end - DMA engine stop
469 * @qc: ATA command
470 *
471 * Work around the HPT370 DMA engine.
472 */
473
474static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
475{
476 struct ata_port *ap = qc->ap;
477 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
478 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
479 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
480 u8 dma_cmd;
481
482 if (dma_stat & ATA_DMA_ACTIVE) {
483 udelay(20);
484 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
485 }
486 if (dma_stat & ATA_DMA_ACTIVE) {
487 /* Clear the engine */
488 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
489 udelay(10);
490 /* Stop DMA */
491 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
492 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
493 /* Clear Error */
494 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
495 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
496 bmdma + ATA_DMA_STATUS);
497 /* Clear the engine */
498 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
499 udelay(10);
500 }
501 ata_bmdma_stop(qc);
502}
503
504static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
505 u8 mode)
506{
507 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
508 u32 addr1, addr2;
509 u32 reg, timing, mask;
510 u8 fast;
511
512 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
513 addr2 = 0x51 + 4 * ap->port_no;
514
515 /* Fast interrupt prediction disable, hold off interrupt disable */
516 pci_read_config_byte(pdev, addr2, &fast);
517 fast &= ~0x07;
518 pci_write_config_byte(pdev, addr2, fast);
519
520 /* Determine timing mask and find matching mode entry */
521 if (mode < XFER_MW_DMA_0)
522 mask = 0xcfc3ffff;
523 else if (mode < XFER_UDMA_0)
524 mask = 0x31c001ff;
525 else
526 mask = 0x303c0000;
527
528 timing = hpt37x_find_mode(ap, mode);
529
530 pci_read_config_dword(pdev, addr1, ®);
531 reg = (reg & ~mask) | (timing & mask);
532 pci_write_config_dword(pdev, addr1, reg);
533}
534
535/**
536 * hpt372_set_piomode - PIO setup
537 * @ap: ATA interface
538 * @adev: device on the interface
539 *
540 * Perform PIO mode setup.
541 */
542
543static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
544{
545 hpt372_set_mode(ap, adev, adev->pio_mode);
546}
547
548/**
549 * hpt372_set_dmamode - DMA timing setup
550 * @ap: ATA interface
551 * @adev: Device being configured
552 *
553 * Set up the channel for MWDMA or UDMA modes.
554 */
555
556static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
557{
558 hpt372_set_mode(ap, adev, adev->dma_mode);
559}
560
561/**
562 * hpt37x_bmdma_end - DMA engine stop
563 * @qc: ATA command
564 *
565 * Clean up after the HPT372 and later DMA engine
566 */
567
568static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
569{
570 struct ata_port *ap = qc->ap;
571 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
572 int mscreg = 0x50 + 4 * ap->port_no;
573 u8 bwsr_stat, msc_stat;
574
575 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
576 pci_read_config_byte(pdev, mscreg, &msc_stat);
577 if (bwsr_stat & (1 << ap->port_no))
578 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
579 ata_bmdma_stop(qc);
580}
581
582
583static struct scsi_host_template hpt37x_sht = {
584 ATA_BMDMA_SHT(DRV_NAME),
585};
586
587/*
588 * Configuration for HPT370
589 */
590
591static struct ata_port_operations hpt370_port_ops = {
592 .inherits = &ata_bmdma_port_ops,
593
594 .bmdma_stop = hpt370_bmdma_stop,
595
596 .mode_filter = hpt370_filter,
597 .cable_detect = hpt37x_cable_detect,
598 .set_piomode = hpt370_set_piomode,
599 .set_dmamode = hpt370_set_dmamode,
600 .prereset = hpt37x_pre_reset,
601};
602
603/*
604 * Configuration for HPT370A. Close to 370 but less filters
605 */
606
607static struct ata_port_operations hpt370a_port_ops = {
608 .inherits = &hpt370_port_ops,
609 .mode_filter = hpt370a_filter,
610};
611
612/*
613 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
614 * mode setting functionality.
615 */
616
617static struct ata_port_operations hpt302_port_ops = {
618 .inherits = &ata_bmdma_port_ops,
619
620 .bmdma_stop = hpt37x_bmdma_stop,
621
622 .cable_detect = hpt37x_cable_detect,
623 .set_piomode = hpt372_set_piomode,
624 .set_dmamode = hpt372_set_dmamode,
625 .prereset = hpt37x_pre_reset,
626};
627
628/*
629 * Configuration for HPT372. Mode setting works like 371 and 302
630 * but we have a mode filter.
631 */
632
633static struct ata_port_operations hpt372_port_ops = {
634 .inherits = &hpt302_port_ops,
635 .mode_filter = hpt372_filter,
636};
637
638/*
639 * Configuration for HPT374. Mode setting and filtering works like 372
640 * but we have a different cable detection procedure for function 1.
641 */
642
643static struct ata_port_operations hpt374_fn1_port_ops = {
644 .inherits = &hpt372_port_ops,
645 .cable_detect = hpt374_fn1_cable_detect,
646};
647
648/**
649 * hpt37x_clock_slot - Turn timing to PC clock entry
650 * @freq: Reported frequency timing
651 * @base: Base timing
652 *
653 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
654 * and 3 for 66Mhz)
655 */
656
657static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
658{
659 unsigned int f = (base * freq) / 192; /* Mhz */
660 if (f < 40)
661 return 0; /* 33Mhz slot */
662 if (f < 45)
663 return 1; /* 40Mhz slot */
664 if (f < 55)
665 return 2; /* 50Mhz slot */
666 return 3; /* 60Mhz slot */
667}
668
669/**
670 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
671 * @dev: PCI device
672 *
673 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
674 * succeeds
675 */
676
677static int hpt37x_calibrate_dpll(struct pci_dev *dev)
678{
679 u8 reg5b;
680 u32 reg5c;
681 int tries;
682
683 for (tries = 0; tries < 0x5000; tries++) {
684 udelay(50);
685 pci_read_config_byte(dev, 0x5b, ®5b);
686 if (reg5b & 0x80) {
687 /* See if it stays set */
688 for (tries = 0; tries < 0x1000; tries++) {
689 pci_read_config_byte(dev, 0x5b, ®5b);
690 /* Failed ? */
691 if ((reg5b & 0x80) == 0)
692 return 0;
693 }
694 /* Turn off tuning, we have the DPLL set */
695 pci_read_config_dword(dev, 0x5c, ®5c);
696 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
697 return 1;
698 }
699 }
700 /* Never went stable */
701 return 0;
702}
703
704static u32 hpt374_read_freq(struct pci_dev *pdev)
705{
706 u32 freq;
707 unsigned long io_base = pci_resource_start(pdev, 4);
708
709 if (PCI_FUNC(pdev->devfn) & 1) {
710 struct pci_dev *pdev_0;
711
712 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
713 /* Someone hot plugged the controller on us ? */
714 if (pdev_0 == NULL)
715 return 0;
716 io_base = pci_resource_start(pdev_0, 4);
717 freq = inl(io_base + 0x90);
718 pci_dev_put(pdev_0);
719 } else
720 freq = inl(io_base + 0x90);
721 return freq;
722}
723
724/**
725 * hpt37x_init_one - Initialise an HPT37X/302
726 * @dev: PCI device
727 * @id: Entry in match table
728 *
729 * Initialise an HPT37x device. There are some interesting complications
730 * here. Firstly the chip may report 366 and be one of several variants.
731 * Secondly all the timings depend on the clock for the chip which we must
732 * detect and look up
733 *
734 * This is the known chip mappings. It may be missing a couple of later
735 * releases.
736 *
737 * Chip version PCI Rev Notes
738 * HPT366 4 (HPT366) 0 Other driver
739 * HPT366 4 (HPT366) 1 Other driver
740 * HPT368 4 (HPT366) 2 Other driver
741 * HPT370 4 (HPT366) 3 UDMA100
742 * HPT370A 4 (HPT366) 4 UDMA100
743 * HPT372 4 (HPT366) 5 UDMA133 (1)
744 * HPT372N 4 (HPT366) 6 Other driver
745 * HPT372A 5 (HPT372) 1 UDMA133 (1)
746 * HPT372N 5 (HPT372) 2 Other driver
747 * HPT302 6 (HPT302) 1 UDMA133
748 * HPT302N 6 (HPT302) 2 Other driver
749 * HPT371 7 (HPT371) * UDMA133
750 * HPT374 8 (HPT374) * UDMA133 4 channel
751 * HPT372N 9 (HPT372N) * Other driver
752 *
753 * (1) UDMA133 support depends on the bus clock
754 */
755
756static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
757{
758 /* HPT370 - UDMA100 */
759 static const struct ata_port_info info_hpt370 = {
760 .flags = ATA_FLAG_SLAVE_POSS,
761 .pio_mask = ATA_PIO4,
762 .mwdma_mask = ATA_MWDMA2,
763 .udma_mask = ATA_UDMA5,
764 .port_ops = &hpt370_port_ops
765 };
766 /* HPT370A - UDMA100 */
767 static const struct ata_port_info info_hpt370a = {
768 .flags = ATA_FLAG_SLAVE_POSS,
769 .pio_mask = ATA_PIO4,
770 .mwdma_mask = ATA_MWDMA2,
771 .udma_mask = ATA_UDMA5,
772 .port_ops = &hpt370a_port_ops
773 };
774 /* HPT370 - UDMA66 */
775 static const struct ata_port_info info_hpt370_33 = {
776 .flags = ATA_FLAG_SLAVE_POSS,
777 .pio_mask = ATA_PIO4,
778 .mwdma_mask = ATA_MWDMA2,
779 .udma_mask = ATA_UDMA4,
780 .port_ops = &hpt370_port_ops
781 };
782 /* HPT370A - UDMA66 */
783 static const struct ata_port_info info_hpt370a_33 = {
784 .flags = ATA_FLAG_SLAVE_POSS,
785 .pio_mask = ATA_PIO4,
786 .mwdma_mask = ATA_MWDMA2,
787 .udma_mask = ATA_UDMA4,
788 .port_ops = &hpt370a_port_ops
789 };
790 /* HPT372 - UDMA133 */
791 static const struct ata_port_info info_hpt372 = {
792 .flags = ATA_FLAG_SLAVE_POSS,
793 .pio_mask = ATA_PIO4,
794 .mwdma_mask = ATA_MWDMA2,
795 .udma_mask = ATA_UDMA6,
796 .port_ops = &hpt372_port_ops
797 };
798 /* HPT371, 302 - UDMA133 */
799 static const struct ata_port_info info_hpt302 = {
800 .flags = ATA_FLAG_SLAVE_POSS,
801 .pio_mask = ATA_PIO4,
802 .mwdma_mask = ATA_MWDMA2,
803 .udma_mask = ATA_UDMA6,
804 .port_ops = &hpt302_port_ops
805 };
806 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
807 static const struct ata_port_info info_hpt374_fn0 = {
808 .flags = ATA_FLAG_SLAVE_POSS,
809 .pio_mask = ATA_PIO4,
810 .mwdma_mask = ATA_MWDMA2,
811 .udma_mask = ATA_UDMA5,
812 .port_ops = &hpt372_port_ops
813 };
814 static const struct ata_port_info info_hpt374_fn1 = {
815 .flags = ATA_FLAG_SLAVE_POSS,
816 .pio_mask = ATA_PIO4,
817 .mwdma_mask = ATA_MWDMA2,
818 .udma_mask = ATA_UDMA5,
819 .port_ops = &hpt374_fn1_port_ops
820 };
821
822 static const int MHz[4] = { 33, 40, 50, 66 };
823 void *private_data = NULL;
824 const struct ata_port_info *ppi[] = { NULL, NULL };
825 u8 rev = dev->revision;
826 u8 irqmask;
827 u8 mcr1;
828 u32 freq;
829 int prefer_dpll = 1;
830
831 unsigned long iobase = pci_resource_start(dev, 4);
832
833 const struct hpt_chip *chip_table;
834 int clock_slot;
835 int rc;
836
837 rc = pcim_enable_device(dev);
838 if (rc)
839 return rc;
840
841 switch (dev->device) {
842 case PCI_DEVICE_ID_TTI_HPT366:
843 /* May be a later chip in disguise. Check */
844 /* Older chips are in the HPT366 driver. Ignore them */
845 if (rev < 3)
846 return -ENODEV;
847 /* N series chips have their own driver. Ignore */
848 if (rev == 6)
849 return -ENODEV;
850
851 switch (rev) {
852 case 3:
853 ppi[0] = &info_hpt370;
854 chip_table = &hpt370;
855 prefer_dpll = 0;
856 break;
857 case 4:
858 ppi[0] = &info_hpt370a;
859 chip_table = &hpt370a;
860 prefer_dpll = 0;
861 break;
862 case 5:
863 ppi[0] = &info_hpt372;
864 chip_table = &hpt372;
865 break;
866 default:
867 pr_err("Unknown HPT366 subtype, please report (%d)\n",
868 rev);
869 return -ENODEV;
870 }
871 break;
872 case PCI_DEVICE_ID_TTI_HPT372:
873 /* 372N if rev >= 2 */
874 if (rev >= 2)
875 return -ENODEV;
876 ppi[0] = &info_hpt372;
877 chip_table = &hpt372a;
878 break;
879 case PCI_DEVICE_ID_TTI_HPT302:
880 /* 302N if rev > 1 */
881 if (rev > 1)
882 return -ENODEV;
883 ppi[0] = &info_hpt302;
884 /* Check this */
885 chip_table = &hpt302;
886 break;
887 case PCI_DEVICE_ID_TTI_HPT371:
888 if (rev > 1)
889 return -ENODEV;
890 ppi[0] = &info_hpt302;
891 chip_table = &hpt371;
892 /*
893 * Single channel device, master is not present but the BIOS
894 * (or us for non x86) must mark it absent
895 */
896 pci_read_config_byte(dev, 0x50, &mcr1);
897 mcr1 &= ~0x04;
898 pci_write_config_byte(dev, 0x50, mcr1);
899 break;
900 case PCI_DEVICE_ID_TTI_HPT374:
901 chip_table = &hpt374;
902 if (!(PCI_FUNC(dev->devfn) & 1))
903 *ppi = &info_hpt374_fn0;
904 else
905 *ppi = &info_hpt374_fn1;
906 break;
907 default:
908 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
909 return -ENODEV;
910 }
911 /* Ok so this is a chip we support */
912
913 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
914 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
915 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
916 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
917
918 pci_read_config_byte(dev, 0x5A, &irqmask);
919 irqmask &= ~0x10;
920 pci_write_config_byte(dev, 0x5a, irqmask);
921
922 /*
923 * default to pci clock. make sure MA15/16 are set to output
924 * to prevent drives having problems with 40-pin cables. Needed
925 * for some drives such as IBM-DTLA which will not enter ready
926 * state on reset when PDIAG is a input.
927 */
928
929 pci_write_config_byte(dev, 0x5b, 0x23);
930
931 /*
932 * HighPoint does this for HPT372A.
933 * NOTE: This register is only writeable via I/O space.
934 */
935 if (chip_table == &hpt372a)
936 outb(0x0e, iobase + 0x9c);
937
938 /*
939 * Some devices do not let this value be accessed via PCI space
940 * according to the old driver. In addition we must use the value
941 * from FN 0 on the HPT374.
942 */
943
944 if (chip_table == &hpt374) {
945 freq = hpt374_read_freq(dev);
946 if (freq == 0)
947 return -ENODEV;
948 } else
949 freq = inl(iobase + 0x90);
950
951 if ((freq >> 12) != 0xABCDE) {
952 int i;
953 u8 sr;
954 u32 total = 0;
955
956 pr_warn("BIOS has not set timing clocks\n");
957
958 /* This is the process the HPT371 BIOS is reported to use */
959 for (i = 0; i < 128; i++) {
960 pci_read_config_byte(dev, 0x78, &sr);
961 total += sr & 0x1FF;
962 udelay(15);
963 }
964 freq = total / 128;
965 }
966 freq &= 0x1FF;
967
968 /*
969 * Turn the frequency check into a band and then find a timing
970 * table to match it.
971 */
972
973 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
974 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
975 /*
976 * We need to try PLL mode instead
977 *
978 * For non UDMA133 capable devices we should
979 * use a 50MHz DPLL by choice
980 */
981 unsigned int f_low, f_high;
982 int dpll, adjust;
983
984 /* Compute DPLL */
985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
986
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
988 f_high = f_low + 2;
989 if (clock_slot > 1)
990 f_high += 2;
991
992 /* Select the DPLL clock. */
993 pci_write_config_byte(dev, 0x5b, 0x21);
994 pci_write_config_dword(dev, 0x5C,
995 (f_high << 16) | f_low | 0x100);
996
997 for (adjust = 0; adjust < 8; adjust++) {
998 if (hpt37x_calibrate_dpll(dev))
999 break;
1000 /*
1001 * See if it'll settle at a fractionally
1002 * different clock
1003 */
1004 if (adjust & 1)
1005 f_low -= adjust >> 1;
1006 else
1007 f_high += adjust >> 1;
1008 pci_write_config_dword(dev, 0x5C,
1009 (f_high << 16) | f_low | 0x100);
1010 }
1011 if (adjust == 8) {
1012 pr_err("DPLL did not stabilize!\n");
1013 return -ENODEV;
1014 }
1015 if (dpll == 3)
1016 private_data = (void *)hpt37x_timings_66;
1017 else
1018 private_data = (void *)hpt37x_timings_50;
1019
1020 pr_info("bus clock %dMHz, using %dMHz DPLL\n",
1021 MHz[clock_slot], MHz[dpll]);
1022 } else {
1023 private_data = (void *)chip_table->clocks[clock_slot];
1024 /*
1025 * Perform a final fixup. Note that we will have used the
1026 * DPLL on the HPT372 which means we don't have to worry
1027 * about lack of UDMA133 support on lower clocks
1028 */
1029
1030 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1031 ppi[0] = &info_hpt370_33;
1032 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1033 ppi[0] = &info_hpt370a_33;
1034
1035 pr_info("%s using %dMHz bus clock\n",
1036 chip_table->name, MHz[clock_slot]);
1037 }
1038
1039 /* Now kick off ATA set up */
1040 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1041}
1042
1043static const struct pci_device_id hpt37x[] = {
1044 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1047 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1048 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1049
1050 { },
1051};
1052
1053static struct pci_driver hpt37x_pci_driver = {
1054 .name = DRV_NAME,
1055 .id_table = hpt37x,
1056 .probe = hpt37x_init_one,
1057 .remove = ata_pci_remove_one
1058};
1059
1060module_pci_driver(hpt37x_pci_driver);
1061
1062MODULE_AUTHOR("Alan Cox");
1063MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1064MODULE_LICENSE("GPL");
1065MODULE_DEVICE_TABLE(pci, hpt37x);
1066MODULE_VERSION(DRV_VERSION);