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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Aic94xx SAS/SATA driver sequencer interface.
4 *
5 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
6 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7 *
8 * Parts of this code adapted from David Chaw's adp94xx_seq.c.
9 */
10
11#include <linux/delay.h>
12#include <linux/gfp.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/firmware.h>
16#include "aic94xx_reg.h"
17#include "aic94xx_hwi.h"
18
19#include "aic94xx_seq.h"
20#include "aic94xx_dump.h"
21
22/* It takes no more than 0.05 us for an instruction
23 * to complete. So waiting for 1 us should be more than
24 * plenty.
25 */
26#define PAUSE_DELAY 1
27#define PAUSE_TRIES 1000
28
29static const struct firmware *sequencer_fw;
30static u16 cseq_vecs[CSEQ_NUM_VECS], lseq_vecs[LSEQ_NUM_VECS], mode2_task,
31 cseq_idle_loop, lseq_idle_loop;
32static const u8 *cseq_code, *lseq_code;
33static u32 cseq_code_size, lseq_code_size;
34
35static u16 first_scb_site_no = 0xFFFF;
36static u16 last_scb_site_no;
37
38/* ---------- Pause/Unpause CSEQ/LSEQ ---------- */
39
40/**
41 * asd_pause_cseq - pause the central sequencer
42 * @asd_ha: pointer to host adapter structure
43 *
44 * Return 0 on success, negative on failure.
45 */
46static int asd_pause_cseq(struct asd_ha_struct *asd_ha)
47{
48 int count = PAUSE_TRIES;
49 u32 arp2ctl;
50
51 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
52 if (arp2ctl & PAUSED)
53 return 0;
54
55 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl | EPAUSE);
56 do {
57 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
58 if (arp2ctl & PAUSED)
59 return 0;
60 udelay(PAUSE_DELAY);
61 } while (--count > 0);
62
63 ASD_DPRINTK("couldn't pause CSEQ\n");
64 return -1;
65}
66
67/**
68 * asd_unpause_cseq - unpause the central sequencer.
69 * @asd_ha: pointer to host adapter structure.
70 *
71 * Return 0 on success, negative on error.
72 */
73static int asd_unpause_cseq(struct asd_ha_struct *asd_ha)
74{
75 u32 arp2ctl;
76 int count = PAUSE_TRIES;
77
78 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
79 if (!(arp2ctl & PAUSED))
80 return 0;
81
82 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl & ~EPAUSE);
83 do {
84 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
85 if (!(arp2ctl & PAUSED))
86 return 0;
87 udelay(PAUSE_DELAY);
88 } while (--count > 0);
89
90 ASD_DPRINTK("couldn't unpause the CSEQ\n");
91 return -1;
92}
93
94/**
95 * asd_seq_pause_lseq - pause a link sequencer
96 * @asd_ha: pointer to a host adapter structure
97 * @lseq: link sequencer of interest
98 *
99 * Return 0 on success, negative on error.
100 */
101static int asd_seq_pause_lseq(struct asd_ha_struct *asd_ha, int lseq)
102{
103 u32 arp2ctl;
104 int count = PAUSE_TRIES;
105
106 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
107 if (arp2ctl & PAUSED)
108 return 0;
109
110 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl | EPAUSE);
111 do {
112 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
113 if (arp2ctl & PAUSED)
114 return 0;
115 udelay(PAUSE_DELAY);
116 } while (--count > 0);
117
118 ASD_DPRINTK("couldn't pause LSEQ %d\n", lseq);
119 return -1;
120}
121
122/**
123 * asd_pause_lseq - pause the link sequencer(s)
124 * @asd_ha: pointer to host adapter structure
125 * @lseq_mask: mask of link sequencers of interest
126 *
127 * Return 0 on success, negative on failure.
128 */
129static int asd_pause_lseq(struct asd_ha_struct *asd_ha, u8 lseq_mask)
130{
131 int lseq;
132 int err = 0;
133
134 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
135 err = asd_seq_pause_lseq(asd_ha, lseq);
136 if (err)
137 return err;
138 }
139
140 return err;
141}
142
143/**
144 * asd_seq_unpause_lseq - unpause a link sequencer
145 * @asd_ha: pointer to host adapter structure
146 * @lseq: link sequencer of interest
147 *
148 * Return 0 on success, negative on error.
149 */
150static int asd_seq_unpause_lseq(struct asd_ha_struct *asd_ha, int lseq)
151{
152 u32 arp2ctl;
153 int count = PAUSE_TRIES;
154
155 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
156 if (!(arp2ctl & PAUSED))
157 return 0;
158
159 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl & ~EPAUSE);
160 do {
161 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
162 if (!(arp2ctl & PAUSED))
163 return 0;
164 udelay(PAUSE_DELAY);
165 } while (--count > 0);
166
167 ASD_DPRINTK("couldn't unpause LSEQ %d\n", lseq);
168 return 0;
169}
170
171
172/* ---------- Downloading CSEQ/LSEQ microcode ---------- */
173
174static int asd_verify_cseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
175 u32 size)
176{
177 u32 addr = CSEQ_RAM_REG_BASE_ADR;
178 const u32 *prog = (u32 *) _prog;
179 u32 i;
180
181 for (i = 0; i < size; i += 4, prog++, addr += 4) {
182 u32 val = asd_read_reg_dword(asd_ha, addr);
183
184 if (le32_to_cpu(*prog) != val) {
185 asd_printk("%s: cseq verify failed at %u "
186 "read:0x%x, wanted:0x%x\n",
187 pci_name(asd_ha->pcidev),
188 i, val, le32_to_cpu(*prog));
189 return -1;
190 }
191 }
192 ASD_DPRINTK("verified %d bytes, passed\n", size);
193 return 0;
194}
195
196/**
197 * asd_verify_lseq - verify the microcode of a link sequencer
198 * @asd_ha: pointer to host adapter structure
199 * @_prog: pointer to the microcode
200 * @size: size of the microcode in bytes
201 * @lseq: link sequencer of interest
202 *
203 * The link sequencer code is accessed in 4 KB pages, which are selected
204 * by setting LmRAMPAGE (bits 8 and 9) of the LmBISTCTL1 register.
205 * The 10 KB LSEQm instruction code is mapped, page at a time, at
206 * LmSEQRAM address.
207 */
208static int asd_verify_lseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
209 u32 size, int lseq)
210{
211#define LSEQ_CODEPAGE_SIZE 4096
212 int pages = (size + LSEQ_CODEPAGE_SIZE - 1) / LSEQ_CODEPAGE_SIZE;
213 u32 page;
214 const u32 *prog = (u32 *) _prog;
215
216 for (page = 0; page < pages; page++) {
217 u32 i;
218
219 asd_write_reg_dword(asd_ha, LmBISTCTL1(lseq),
220 page << LmRAMPAGE_LSHIFT);
221 for (i = 0; size > 0 && i < LSEQ_CODEPAGE_SIZE;
222 i += 4, prog++, size-=4) {
223
224 u32 val = asd_read_reg_dword(asd_ha, LmSEQRAM(lseq)+i);
225
226 if (le32_to_cpu(*prog) != val) {
227 asd_printk("%s: LSEQ%d verify failed "
228 "page:%d, offs:%d\n",
229 pci_name(asd_ha->pcidev),
230 lseq, page, i);
231 return -1;
232 }
233 }
234 }
235 ASD_DPRINTK("LSEQ%d verified %d bytes, passed\n", lseq,
236 (int)((u8 *)prog-_prog));
237 return 0;
238}
239
240/**
241 * asd_verify_seq -- verify CSEQ/LSEQ microcode
242 * @asd_ha: pointer to host adapter structure
243 * @prog: pointer to microcode
244 * @size: size of the microcode
245 * @lseq_mask: if 0, verify CSEQ microcode, else mask of LSEQs of interest
246 *
247 * Return 0 if microcode is correct, negative on mismatch.
248 */
249static int asd_verify_seq(struct asd_ha_struct *asd_ha, const u8 *prog,
250 u32 size, u8 lseq_mask)
251{
252 if (lseq_mask == 0)
253 return asd_verify_cseq(asd_ha, prog, size);
254 else {
255 int lseq, err;
256
257 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
258 err = asd_verify_lseq(asd_ha, prog, size, lseq);
259 if (err)
260 return err;
261 }
262 }
263
264 return 0;
265}
266#define ASD_DMA_MODE_DOWNLOAD
267#ifdef ASD_DMA_MODE_DOWNLOAD
268/* This is the size of the CSEQ Mapped instruction page */
269#define MAX_DMA_OVLY_COUNT ((1U << 14)-1)
270static int asd_download_seq(struct asd_ha_struct *asd_ha,
271 const u8 * const prog, u32 size, u8 lseq_mask)
272{
273 u32 comstaten;
274 u32 reg;
275 int page;
276 const int pages = (size + MAX_DMA_OVLY_COUNT - 1) / MAX_DMA_OVLY_COUNT;
277 struct asd_dma_tok *token;
278 int err = 0;
279
280 if (size % 4) {
281 asd_printk("sequencer program not multiple of 4\n");
282 return -1;
283 }
284
285 asd_pause_cseq(asd_ha);
286 asd_pause_lseq(asd_ha, 0xFF);
287
288 /* save, disable and clear interrupts */
289 comstaten = asd_read_reg_dword(asd_ha, COMSTATEN);
290 asd_write_reg_dword(asd_ha, COMSTATEN, 0);
291 asd_write_reg_dword(asd_ha, COMSTAT, COMSTAT_MASK);
292
293 asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
294 asd_write_reg_dword(asd_ha, CHIMINT, CHIMINT_MASK);
295
296 token = asd_alloc_coherent(asd_ha, MAX_DMA_OVLY_COUNT, GFP_KERNEL);
297 if (!token) {
298 asd_printk("out of memory for dma SEQ download\n");
299 err = -ENOMEM;
300 goto out;
301 }
302 ASD_DPRINTK("dma-ing %d bytes\n", size);
303
304 for (page = 0; page < pages; page++) {
305 int i;
306 u32 left = min(size-page*MAX_DMA_OVLY_COUNT,
307 (u32)MAX_DMA_OVLY_COUNT);
308
309 memcpy(token->vaddr, prog + page*MAX_DMA_OVLY_COUNT, left);
310 asd_write_reg_addr(asd_ha, OVLYDMAADR, token->dma_handle);
311 asd_write_reg_dword(asd_ha, OVLYDMACNT, left);
312 reg = !page ? RESETOVLYDMA : 0;
313 reg |= (STARTOVLYDMA | OVLYHALTERR);
314 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
315 /* Start DMA. */
316 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
317
318 for (i = PAUSE_TRIES*100; i > 0; i--) {
319 u32 dmadone = asd_read_reg_dword(asd_ha, OVLYDMACTL);
320 if (!(dmadone & OVLYDMAACT))
321 break;
322 udelay(PAUSE_DELAY);
323 }
324 }
325
326 reg = asd_read_reg_dword(asd_ha, COMSTAT);
327 if (!(reg & OVLYDMADONE) || (reg & OVLYERR)
328 || (asd_read_reg_dword(asd_ha, CHIMINT) & DEVEXCEPT_MASK)){
329 asd_printk("%s: error DMA-ing sequencer code\n",
330 pci_name(asd_ha->pcidev));
331 err = -ENODEV;
332 }
333
334 asd_free_coherent(asd_ha, token);
335 out:
336 asd_write_reg_dword(asd_ha, COMSTATEN, comstaten);
337
338 return err ? : asd_verify_seq(asd_ha, prog, size, lseq_mask);
339}
340#else /* ASD_DMA_MODE_DOWNLOAD */
341static int asd_download_seq(struct asd_ha_struct *asd_ha, const u8 *_prog,
342 u32 size, u8 lseq_mask)
343{
344 int i;
345 u32 reg = 0;
346 const u32 *prog = (u32 *) _prog;
347
348 if (size % 4) {
349 asd_printk("sequencer program not multiple of 4\n");
350 return -1;
351 }
352
353 asd_pause_cseq(asd_ha);
354 asd_pause_lseq(asd_ha, 0xFF);
355
356 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
357 reg |= PIOCMODE;
358
359 asd_write_reg_dword(asd_ha, OVLYDMACNT, size);
360 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
361
362 ASD_DPRINTK("downloading %s sequencer%s in PIO mode...\n",
363 lseq_mask ? "LSEQ" : "CSEQ", lseq_mask ? "s" : "");
364
365 for (i = 0; i < size; i += 4, prog++)
366 asd_write_reg_dword(asd_ha, SPIODATA, *prog);
367
368 reg = (reg & ~PIOCMODE) | OVLYHALTERR;
369 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
370
371 return asd_verify_seq(asd_ha, _prog, size, lseq_mask);
372}
373#endif /* ASD_DMA_MODE_DOWNLOAD */
374
375/**
376 * asd_seq_download_seqs - download the sequencer microcode
377 * @asd_ha: pointer to host adapter structure
378 *
379 * Download the central and link sequencer microcode.
380 */
381static int asd_seq_download_seqs(struct asd_ha_struct *asd_ha)
382{
383 int err;
384
385 if (!asd_ha->hw_prof.enabled_phys) {
386 asd_printk("%s: no enabled phys!\n", pci_name(asd_ha->pcidev));
387 return -ENODEV;
388 }
389
390 /* Download the CSEQ */
391 ASD_DPRINTK("downloading CSEQ...\n");
392 err = asd_download_seq(asd_ha, cseq_code, cseq_code_size, 0);
393 if (err) {
394 asd_printk("CSEQ download failed:%d\n", err);
395 return err;
396 }
397
398 /* Download the Link Sequencers code. All of the Link Sequencers
399 * microcode can be downloaded at the same time.
400 */
401 ASD_DPRINTK("downloading LSEQs...\n");
402 err = asd_download_seq(asd_ha, lseq_code, lseq_code_size,
403 asd_ha->hw_prof.enabled_phys);
404 if (err) {
405 /* Try it one at a time */
406 u8 lseq;
407 u8 lseq_mask = asd_ha->hw_prof.enabled_phys;
408
409 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
410 err = asd_download_seq(asd_ha, lseq_code,
411 lseq_code_size, 1<<lseq);
412 if (err)
413 break;
414 }
415 }
416 if (err)
417 asd_printk("LSEQs download failed:%d\n", err);
418
419 return err;
420}
421
422/* ---------- Initializing the chip, chip memory, etc. ---------- */
423
424/**
425 * asd_init_cseq_mip - initialize CSEQ mode independent pages 4-7
426 * @asd_ha: pointer to host adapter structure
427 */
428static void asd_init_cseq_mip(struct asd_ha_struct *asd_ha)
429{
430 /* CSEQ Mode Independent, page 4 setup. */
431 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_HEAD, 0xFFFF);
432 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_TAIL, 0xFFFF);
433 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_HEAD, 0xFFFF);
434 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_TAIL, 0xFFFF);
435 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_HEAD, 0xFFFF);
436 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_TAIL, 0xFFFF);
437 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_HEAD, 0xFFFF);
438 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_TAIL, 0xFFFF);
439 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_HEAD, 0xFFFF);
440 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_TAIL, 0xFFFF);
441 asd_write_reg_word(asd_ha, CSEQ_REG0, 0);
442 asd_write_reg_word(asd_ha, CSEQ_REG1, 0);
443 asd_write_reg_dword(asd_ha, CSEQ_REG2, 0);
444 asd_write_reg_byte(asd_ha, CSEQ_LINK_CTL_Q_MAP, 0);
445 {
446 u8 con = asd_read_reg_byte(asd_ha, CCONEXIST);
447 u8 val = hweight8(con);
448 asd_write_reg_byte(asd_ha, CSEQ_MAX_CSEQ_MODE, (val<<4)|val);
449 }
450 asd_write_reg_word(asd_ha, CSEQ_FREE_LIST_HACK_COUNT, 0);
451
452 /* CSEQ Mode independent, page 5 setup. */
453 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE, 0);
454 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE+4, 0);
455 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT, 0);
456 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT+4, 0);
457 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_HEAD, 0xFFFF);
458 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_TAIL, 0xFFFF);
459 asd_write_reg_word(asd_ha, CSEQ_NEED_EST_NEXUS_SCB, 0);
460 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_HEAD, 0);
461 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_TAIL, 0);
462 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_SCB_OFFSET, 0);
463
464 /* CSEQ Mode independent, page 6 setup. */
465 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR0, 0);
466 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR1, 0);
467 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_SCBPTR, 0);
468 asd_write_reg_byte(asd_ha, CSEQ_INT_ROUT_MODE, 0);
469 asd_write_reg_byte(asd_ha, CSEQ_ISR_SCRATCH_FLAGS, 0);
470 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_SINDEX, 0);
471 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_DINDEX, 0);
472 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_HEAD, 0xFFFF);
473 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_TAIL, 0xFFFF);
474 /* Calculate the free scb mask. */
475 {
476 u16 cmdctx = asd_get_cmdctx_size(asd_ha);
477 cmdctx = (~((cmdctx/128)-1)) >> 8;
478 asd_write_reg_byte(asd_ha, CSEQ_FREE_SCB_MASK, (u8)cmdctx);
479 }
480 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_HEAD,
481 first_scb_site_no);
482 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_TAIL,
483 last_scb_site_no);
484 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_HEAD, 0xFFFF);
485 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_TAIL, 0xFFFF);
486
487 /* CSEQ Mode independent, page 7 setup. */
488 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE, 0);
489 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE+4, 0);
490 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT, 0);
491 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT+4, 0);
492 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_HEAD, 0xFFFF);
493 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_TAIL, 0xFFFF);
494 asd_write_reg_word(asd_ha, CSEQ_NEED_EMPTY_SCB, 0);
495 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_HEAD, 0);
496 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_TAIL, 0);
497 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_SCB_OFFSET, 0);
498 asd_write_reg_word(asd_ha, CSEQ_PRIMITIVE_DATA, 0);
499 asd_write_reg_dword(asd_ha, CSEQ_TIMEOUT_CONST, 0);
500}
501
502/**
503 * asd_init_cseq_mdp - initialize CSEQ Mode dependent pages
504 * @asd_ha: pointer to host adapter structure
505 */
506static void asd_init_cseq_mdp(struct asd_ha_struct *asd_ha)
507{
508 int i;
509 int moffs;
510
511 moffs = CSEQ_PAGE_SIZE * 2;
512
513 /* CSEQ Mode dependent, modes 0-7, page 0 setup. */
514 for (i = 0; i < 8; i++) {
515 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SINDEX, 0);
516 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCBPTR, 0);
517 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_HEAD, 0xFFFF);
518 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_TAIL, 0xFFFF);
519 asd_write_reg_byte(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCRPAGE, 0);
520 }
521
522 /* CSEQ Mode dependent, mode 0-7, page 1 and 2 shall be ignored. */
523
524 /* CSEQ Mode dependent, mode 8, page 0 setup. */
525 asd_write_reg_word(asd_ha, CSEQ_RET_ADDR, 0xFFFF);
526 asd_write_reg_word(asd_ha, CSEQ_RET_SCBPTR, 0);
527 asd_write_reg_word(asd_ha, CSEQ_SAVE_SCBPTR, 0);
528 asd_write_reg_word(asd_ha, CSEQ_EMPTY_TRANS_CTX, 0);
529 asd_write_reg_word(asd_ha, CSEQ_RESP_LEN, 0);
530 asd_write_reg_word(asd_ha, CSEQ_TMF_SCBPTR, 0);
531 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_PREV_SCB, 0);
532 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_HEAD, 0);
533 asd_write_reg_word(asd_ha, CSEQ_CLEAR_LU_HEAD, 0);
534 asd_write_reg_byte(asd_ha, CSEQ_TMF_OPCODE, 0);
535 asd_write_reg_byte(asd_ha, CSEQ_SCRATCH_FLAGS, 0);
536 asd_write_reg_word(asd_ha, CSEQ_HSB_SITE, 0);
537 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_SCB_SITE,
538 (u16)last_scb_site_no+1);
539 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_DDB_SITE,
540 (u16)asd_ha->hw_prof.max_ddbs);
541
542 /* CSEQ Mode dependent, mode 8, page 1 setup. */
543 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR, 0);
544 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR + 4, 0);
545 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK, 0);
546 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK + 4, 0);
547
548 /* CSEQ Mode dependent, mode 8, page 2 setup. */
549 /* Tell the sequencer the bus address of the first SCB. */
550 asd_write_reg_addr(asd_ha, CSEQ_HQ_NEW_POINTER,
551 asd_ha->seq.next_scb.dma_handle);
552 ASD_DPRINTK("First SCB dma_handle: 0x%llx\n",
553 (unsigned long long)asd_ha->seq.next_scb.dma_handle);
554
555 /* Tell the sequencer the first Done List entry address. */
556 asd_write_reg_addr(asd_ha, CSEQ_HQ_DONE_BASE,
557 asd_ha->seq.actual_dl->dma_handle);
558
559 /* Initialize the Q_DONE_POINTER with the least significant
560 * 4 bytes of the first Done List address. */
561 asd_write_reg_dword(asd_ha, CSEQ_HQ_DONE_POINTER,
562 ASD_BUSADDR_LO(asd_ha->seq.actual_dl->dma_handle));
563
564 asd_write_reg_byte(asd_ha, CSEQ_HQ_DONE_PASS, ASD_DEF_DL_TOGGLE);
565
566 /* CSEQ Mode dependent, mode 8, page 3 shall be ignored. */
567}
568
569/**
570 * asd_init_cseq_scratch -- setup and init CSEQ
571 * @asd_ha: pointer to host adapter structure
572 *
573 * Setup and initialize Central sequencers. Initialize the mode
574 * independent and dependent scratch page to the default settings.
575 */
576static void asd_init_cseq_scratch(struct asd_ha_struct *asd_ha)
577{
578 asd_init_cseq_mip(asd_ha);
579 asd_init_cseq_mdp(asd_ha);
580}
581
582/**
583 * asd_init_lseq_mip -- initialize LSEQ Mode independent pages 0-3
584 * @asd_ha: pointer to host adapter structure
585 * @lseq: link sequencer
586 */
587static void asd_init_lseq_mip(struct asd_ha_struct *asd_ha, u8 lseq)
588{
589 int i;
590
591 /* LSEQ Mode independent page 0 setup. */
592 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_HEAD(lseq), 0xFFFF);
593 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_TAIL(lseq), 0xFFFF);
594 asd_write_reg_byte(asd_ha, LmSEQ_LINK_NUMBER(lseq), lseq);
595 asd_write_reg_byte(asd_ha, LmSEQ_SCRATCH_FLAGS(lseq),
596 ASD_NOTIFY_ENABLE_SPINUP);
597 asd_write_reg_dword(asd_ha, LmSEQ_CONNECTION_STATE(lseq),0x08000000);
598 asd_write_reg_word(asd_ha, LmSEQ_CONCTL(lseq), 0);
599 asd_write_reg_byte(asd_ha, LmSEQ_CONSTAT(lseq), 0);
600 asd_write_reg_byte(asd_ha, LmSEQ_CONNECTION_MODES(lseq), 0);
601 asd_write_reg_word(asd_ha, LmSEQ_REG1_ISR(lseq), 0);
602 asd_write_reg_word(asd_ha, LmSEQ_REG2_ISR(lseq), 0);
603 asd_write_reg_word(asd_ha, LmSEQ_REG3_ISR(lseq), 0);
604 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq), 0);
605 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq)+4, 0);
606
607 /* LSEQ Mode independent page 1 setup. */
608 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR0(lseq), 0xFFFF);
609 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR1(lseq), 0xFFFF);
610 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR2(lseq), 0xFFFF);
611 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR3(lseq), 0xFFFF);
612 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE0(lseq), 0);
613 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE1(lseq), 0);
614 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE2(lseq), 0);
615 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE3(lseq), 0);
616 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_HEAD(lseq), 0);
617 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_TAIL(lseq), 0);
618 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_BUF_AVAIL(lseq), 0);
619 asd_write_reg_dword(asd_ha, LmSEQ_TIMEOUT_CONST(lseq), 0);
620 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_SINDEX(lseq), 0);
621 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_DINDEX(lseq), 0);
622
623 /* LSEQ Mode Independent page 2 setup. */
624 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR0(lseq), 0xFFFF);
625 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR1(lseq), 0xFFFF);
626 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR2(lseq), 0xFFFF);
627 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR3(lseq), 0xFFFF);
628 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD0(lseq), 0);
629 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD1(lseq), 0);
630 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD2(lseq), 0);
631 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD3(lseq), 0);
632 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_HEAD(lseq), 0);
633 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_TAIL(lseq), 0);
634 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_BUFS_AVAIL(lseq), 0);
635 for (i = 0; i < 12; i += 4)
636 asd_write_reg_dword(asd_ha, LmSEQ_ATA_SCR_REGS(lseq) + i, 0);
637
638 /* LSEQ Mode Independent page 3 setup. */
639
640 /* Device present timer timeout */
641 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TMR_TOUT_CONST(lseq),
642 ASD_DEV_PRESENT_TIMEOUT);
643
644 /* SATA interlock timer disabled */
645 asd_write_reg_dword(asd_ha, LmSEQ_SATA_INTERLOCK_TIMEOUT(lseq),
646 ASD_SATA_INTERLOCK_TIMEOUT);
647
648 /* STP shutdown timer timeout constant, IGNORED by the sequencer,
649 * always 0. */
650 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMEOUT(lseq),
651 ASD_STP_SHUTDOWN_TIMEOUT);
652
653 asd_write_reg_dword(asd_ha, LmSEQ_SRST_ASSERT_TIMEOUT(lseq),
654 ASD_SRST_ASSERT_TIMEOUT);
655
656 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMEOUT(lseq),
657 ASD_RCV_FIS_TIMEOUT);
658
659 asd_write_reg_dword(asd_ha, LmSEQ_ONE_MILLISEC_TIMEOUT(lseq),
660 ASD_ONE_MILLISEC_TIMEOUT);
661
662 /* COM_INIT timer */
663 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(lseq),
664 ASD_TEN_MILLISEC_TIMEOUT);
665
666 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMEOUT(lseq),
667 ASD_SMP_RCV_TIMEOUT);
668}
669
670/**
671 * asd_init_lseq_mdp -- initialize LSEQ mode dependent pages.
672 * @asd_ha: pointer to host adapter structure
673 * @lseq: link sequencer
674 */
675static void asd_init_lseq_mdp(struct asd_ha_struct *asd_ha, int lseq)
676{
677 int i;
678 u32 moffs;
679 u16 ret_addr[] = {
680 0xFFFF, /* mode 0 */
681 0xFFFF, /* mode 1 */
682 mode2_task, /* mode 2 */
683 0,
684 0xFFFF, /* mode 4/5 */
685 0xFFFF, /* mode 4/5 */
686 };
687
688 /*
689 * Mode 0,1,2 and 4/5 have common field on page 0 for the first
690 * 14 bytes.
691 */
692 for (i = 0; i < 3; i++) {
693 moffs = i * LSEQ_MODE_SCRATCH_SIZE;
694 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR(lseq)+moffs,
695 ret_addr[i]);
696 asd_write_reg_word(asd_ha, LmSEQ_REG0_MODE(lseq)+moffs, 0);
697 asd_write_reg_word(asd_ha, LmSEQ_MODE_FLAGS(lseq)+moffs, 0);
698 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR2(lseq)+moffs,0xFFFF);
699 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR1(lseq)+moffs,0xFFFF);
700 asd_write_reg_byte(asd_ha, LmSEQ_OPCODE_TO_CSEQ(lseq)+moffs,0);
701 asd_write_reg_word(asd_ha, LmSEQ_DATA_TO_CSEQ(lseq)+moffs,0);
702 }
703 /*
704 * Mode 5 page 0 overlaps the same scratch page with Mode 0 page 3.
705 */
706 asd_write_reg_word(asd_ha,
707 LmSEQ_RET_ADDR(lseq)+LSEQ_MODE5_PAGE0_OFFSET,
708 ret_addr[5]);
709 asd_write_reg_word(asd_ha,
710 LmSEQ_REG0_MODE(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
711 asd_write_reg_word(asd_ha,
712 LmSEQ_MODE_FLAGS(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
713 asd_write_reg_word(asd_ha,
714 LmSEQ_RET_ADDR2(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
715 asd_write_reg_word(asd_ha,
716 LmSEQ_RET_ADDR1(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
717 asd_write_reg_byte(asd_ha,
718 LmSEQ_OPCODE_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
719 asd_write_reg_word(asd_ha,
720 LmSEQ_DATA_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
721
722 /* LSEQ Mode dependent 0, page 0 setup. */
723 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_DDB_SITE(lseq),
724 (u16)asd_ha->hw_prof.max_ddbs);
725 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_TRANS_CTX(lseq), 0);
726 asd_write_reg_word(asd_ha, LmSEQ_RESP_LEN(lseq), 0);
727 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_SCB_SITE(lseq),
728 (u16)last_scb_site_no+1);
729 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq),
730 (u16) ((LmM0INTEN_MASK & 0xFFFF0000) >> 16));
731 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq) + 2,
732 (u16) LmM0INTEN_MASK & 0xFFFF);
733 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_FRM_LEN(lseq), 0);
734 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_PROTOCOL(lseq), 0);
735 asd_write_reg_byte(asd_ha, LmSEQ_RESP_STATUS(lseq), 0);
736 asd_write_reg_byte(asd_ha, LmSEQ_LAST_LOADED_SGE(lseq), 0);
737 asd_write_reg_word(asd_ha, LmSEQ_SAVE_SCBPTR(lseq), 0);
738
739 /* LSEQ mode dependent, mode 1, page 0 setup. */
740 asd_write_reg_word(asd_ha, LmSEQ_Q_XMIT_HEAD(lseq), 0xFFFF);
741 asd_write_reg_word(asd_ha, LmSEQ_M1_EMPTY_TRANS_CTX(lseq), 0);
742 asd_write_reg_word(asd_ha, LmSEQ_INI_CONN_TAG(lseq), 0);
743 asd_write_reg_byte(asd_ha, LmSEQ_FAILED_OPEN_STATUS(lseq), 0);
744 asd_write_reg_byte(asd_ha, LmSEQ_XMIT_REQUEST_TYPE(lseq), 0);
745 asd_write_reg_byte(asd_ha, LmSEQ_M1_RESP_STATUS(lseq), 0);
746 asd_write_reg_byte(asd_ha, LmSEQ_M1_LAST_LOADED_SGE(lseq), 0);
747 asd_write_reg_word(asd_ha, LmSEQ_M1_SAVE_SCBPTR(lseq), 0);
748
749 /* LSEQ Mode dependent mode 2, page 0 setup */
750 asd_write_reg_word(asd_ha, LmSEQ_PORT_COUNTER(lseq), 0);
751 asd_write_reg_word(asd_ha, LmSEQ_PM_TABLE_PTR(lseq), 0);
752 asd_write_reg_word(asd_ha, LmSEQ_SATA_INTERLOCK_TMR_SAVE(lseq), 0);
753 asd_write_reg_word(asd_ha, LmSEQ_IP_BITL(lseq), 0);
754 asd_write_reg_word(asd_ha, LmSEQ_COPY_SMP_CONN_TAG(lseq), 0);
755 asd_write_reg_byte(asd_ha, LmSEQ_P0M2_OFFS1AH(lseq), 0);
756
757 /* LSEQ Mode dependent, mode 4/5, page 0 setup. */
758 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_STATUS(lseq), 0);
759 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_MODE(lseq), 0);
760 asd_write_reg_word(asd_ha, LmSEQ_Q_LINK_HEAD(lseq), 0xFFFF);
761 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_ERR(lseq), 0);
762 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_SIGNALS(lseq), 0);
763 asd_write_reg_byte(asd_ha, LmSEQ_SAS_RESET_MODE(lseq), 0);
764 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RESET_RETRY_COUNT(lseq), 0);
765 asd_write_reg_byte(asd_ha, LmSEQ_NUM_LINK_RESET_RETRIES(lseq), 0);
766 asd_write_reg_word(asd_ha, LmSEQ_OOB_INT_ENABLES(lseq), 0);
767 /*
768 * Set the desired interval between transmissions of the NOTIFY
769 * (ENABLE SPINUP) primitive. Must be initialized to val - 1.
770 */
771 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_TIMEOUT(lseq),
772 ASD_NOTIFY_TIMEOUT - 1);
773 /* No delay for the first NOTIFY to be sent to the attached target. */
774 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_DOWN_COUNT(lseq),
775 ASD_NOTIFY_DOWN_COUNT);
776 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(lseq),
777 ASD_NOTIFY_DOWN_COUNT);
778
779 /* LSEQ Mode dependent, mode 0 and 1, page 1 setup. */
780 for (i = 0; i < 2; i++) {
781 int j;
782 /* Start from Page 1 of Mode 0 and 1. */
783 moffs = LSEQ_PAGE_SIZE + i*LSEQ_MODE_SCRATCH_SIZE;
784 /* All the fields of page 1 can be initialized to 0. */
785 for (j = 0; j < LSEQ_PAGE_SIZE; j += 4)
786 asd_write_reg_dword(asd_ha, LmSCRATCH(lseq)+moffs+j,0);
787 }
788
789 /* LSEQ Mode dependent, mode 2, page 1 setup. */
790 asd_write_reg_dword(asd_ha, LmSEQ_INVALID_DWORD_COUNT(lseq), 0);
791 asd_write_reg_dword(asd_ha, LmSEQ_DISPARITY_ERROR_COUNT(lseq), 0);
792 asd_write_reg_dword(asd_ha, LmSEQ_LOSS_OF_SYNC_COUNT(lseq), 0);
793
794 /* LSEQ Mode dependent, mode 4/5, page 1. */
795 for (i = 0; i < LSEQ_PAGE_SIZE; i+=4)
796 asd_write_reg_dword(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq)+i, 0);
797 asd_write_reg_byte(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq), 0xFF);
798 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq), 0xFF);
799 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+1,0xFF);
800 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+2,0xFF);
801 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq), 0xFF);
802 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+1, 0xFF);
803 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+2, 0xFF);
804 asd_write_reg_dword(asd_ha, LmSEQ_DATA_OFFSET(lseq), 0xFFFFFFFF);
805
806 /* LSEQ Mode dependent, mode 0, page 2 setup. */
807 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMER_TERM_TS(lseq), 0);
808 asd_write_reg_byte(asd_ha, LmSEQ_DEVICE_BITS(lseq), 0);
809 asd_write_reg_word(asd_ha, LmSEQ_SDB_DDB(lseq), 0);
810 asd_write_reg_byte(asd_ha, LmSEQ_SDB_NUM_TAGS(lseq), 0);
811 asd_write_reg_byte(asd_ha, LmSEQ_SDB_CURR_TAG(lseq), 0);
812
813 /* LSEQ Mode Dependent 1, page 2 setup. */
814 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq), 0);
815 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq)+4, 0);
816 asd_write_reg_dword(asd_ha, LmSEQ_OPEN_TIMER_TERM_TS(lseq), 0);
817 asd_write_reg_dword(asd_ha, LmSEQ_SRST_AS_TIMER_TERM_TS(lseq), 0);
818 asd_write_reg_dword(asd_ha, LmSEQ_LAST_LOADED_SG_EL(lseq), 0);
819
820 /* LSEQ Mode Dependent 2, page 2 setup. */
821 /* The LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS is IGNORED by the sequencer,
822 * i.e. always 0. */
823 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(lseq),0);
824 asd_write_reg_dword(asd_ha, LmSEQ_CLOSE_TIMER_TERM_TS(lseq), 0);
825 asd_write_reg_dword(asd_ha, LmSEQ_BREAK_TIMER_TERM_TS(lseq), 0);
826 asd_write_reg_dword(asd_ha, LmSEQ_DWS_RESET_TIMER_TERM_TS(lseq), 0);
827 asd_write_reg_dword(asd_ha,LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(lseq),0);
828 asd_write_reg_dword(asd_ha, LmSEQ_MCTL_TIMER_TERM_TS(lseq), 0);
829
830 /* LSEQ Mode Dependent 4/5, page 2 setup. */
831 asd_write_reg_dword(asd_ha, LmSEQ_COMINIT_TIMER_TERM_TS(lseq), 0);
832 asd_write_reg_dword(asd_ha, LmSEQ_RCV_ID_TIMER_TERM_TS(lseq), 0);
833 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMER_TERM_TS(lseq), 0);
834 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TIMER_TERM_TS(lseq), 0);
835}
836
837/**
838 * asd_init_lseq_scratch -- setup and init link sequencers
839 * @asd_ha: pointer to host adapter struct
840 */
841static void asd_init_lseq_scratch(struct asd_ha_struct *asd_ha)
842{
843 u8 lseq;
844 u8 lseq_mask;
845
846 lseq_mask = asd_ha->hw_prof.enabled_phys;
847 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
848 asd_init_lseq_mip(asd_ha, lseq);
849 asd_init_lseq_mdp(asd_ha, lseq);
850 }
851}
852
853/**
854 * asd_init_scb_sites -- initialize sequencer SCB sites (memory).
855 * @asd_ha: pointer to host adapter structure
856 *
857 * This should be done before initializing common CSEQ and LSEQ
858 * scratch since those areas depend on some computed values here,
859 * last_scb_site_no, etc.
860 */
861static void asd_init_scb_sites(struct asd_ha_struct *asd_ha)
862{
863 u16 site_no;
864 u16 max_scbs = 0;
865
866 for (site_no = asd_ha->hw_prof.max_scbs-1;
867 site_no != (u16) -1;
868 site_no--) {
869 u16 i;
870
871 /* Initialize all fields in the SCB site to 0. */
872 for (i = 0; i < ASD_SCB_SIZE; i += 4)
873 asd_scbsite_write_dword(asd_ha, site_no, i, 0);
874
875 /* Initialize SCB Site Opcode field to invalid. */
876 asd_scbsite_write_byte(asd_ha, site_no,
877 offsetof(struct scb_header, opcode),
878 0xFF);
879
880 /* Initialize SCB Site Flags field to mean a response
881 * frame has been received. This means inadvertent
882 * frames received to be dropped. */
883 asd_scbsite_write_byte(asd_ha, site_no, 0x49, 0x01);
884
885 /* Workaround needed by SEQ to fix a SATA issue is to exclude
886 * certain SCB sites from the free list. */
887 if (!SCB_SITE_VALID(site_no))
888 continue;
889
890 if (last_scb_site_no == 0)
891 last_scb_site_no = site_no;
892
893 /* For every SCB site, we need to initialize the
894 * following fields: Q_NEXT, SCB_OPCODE, SCB_FLAGS,
895 * and SG Element Flag. */
896
897 /* Q_NEXT field of the last SCB is invalidated. */
898 asd_scbsite_write_word(asd_ha, site_no, 0, first_scb_site_no);
899
900 first_scb_site_no = site_no;
901 max_scbs++;
902 }
903 asd_ha->hw_prof.max_scbs = max_scbs;
904 ASD_DPRINTK("max_scbs:%d\n", asd_ha->hw_prof.max_scbs);
905 ASD_DPRINTK("first_scb_site_no:0x%x\n", first_scb_site_no);
906 ASD_DPRINTK("last_scb_site_no:0x%x\n", last_scb_site_no);
907}
908
909/**
910 * asd_init_cseq_cio - initialize CSEQ CIO registers
911 * @asd_ha: pointer to host adapter structure
912 */
913static void asd_init_cseq_cio(struct asd_ha_struct *asd_ha)
914{
915 int i;
916
917 asd_write_reg_byte(asd_ha, CSEQCOMINTEN, 0);
918 asd_write_reg_byte(asd_ha, CSEQDLCTL, ASD_DL_SIZE_BITS);
919 asd_write_reg_byte(asd_ha, CSEQDLOFFS, 0);
920 asd_write_reg_byte(asd_ha, CSEQDLOFFS+1, 0);
921 asd_ha->seq.scbpro = 0;
922 asd_write_reg_dword(asd_ha, SCBPRO, 0);
923 asd_write_reg_dword(asd_ha, CSEQCON, 0);
924
925 /* Initialize CSEQ Mode 11 Interrupt Vectors.
926 * The addresses are 16 bit wide and in dword units.
927 * The values of their macros are in byte units.
928 * Thus we have to divide by 4. */
929 asd_write_reg_word(asd_ha, CM11INTVEC0, cseq_vecs[0]);
930 asd_write_reg_word(asd_ha, CM11INTVEC1, cseq_vecs[1]);
931 asd_write_reg_word(asd_ha, CM11INTVEC2, cseq_vecs[2]);
932
933 /* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
934 asd_write_reg_byte(asd_ha, CARP2INTEN, EN_ARP2HALTC);
935
936 /* Initialize CSEQ Scratch Page to 0x04. */
937 asd_write_reg_byte(asd_ha, CSCRATCHPAGE, 0x04);
938
939 /* Initialize CSEQ Mode[0-8] Dependent registers. */
940 /* Initialize Scratch Page to 0. */
941 for (i = 0; i < 9; i++)
942 asd_write_reg_byte(asd_ha, CMnSCRATCHPAGE(i), 0);
943
944 /* Reset the ARP2 Program Count. */
945 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
946
947 for (i = 0; i < 8; i++) {
948 /* Initialize Mode n Link m Interrupt Enable. */
949 asd_write_reg_dword(asd_ha, CMnINTEN(i), EN_CMnRSPMBXF);
950 /* Initialize Mode n Request Mailbox. */
951 asd_write_reg_dword(asd_ha, CMnREQMBX(i), 0);
952 }
953}
954
955/**
956 * asd_init_lseq_cio -- initialize LmSEQ CIO registers
957 * @asd_ha: pointer to host adapter structure
958 * @lseq: link sequencer
959 */
960static void asd_init_lseq_cio(struct asd_ha_struct *asd_ha, int lseq)
961{
962 u8 *sas_addr;
963 int i;
964
965 /* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
966 asd_write_reg_dword(asd_ha, LmARP2INTEN(lseq), EN_ARP2HALTC);
967
968 asd_write_reg_byte(asd_ha, LmSCRATCHPAGE(lseq), 0);
969
970 /* Initialize Mode 0,1, and 2 SCRATCHPAGE to 0. */
971 for (i = 0; i < 3; i++)
972 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, i), 0);
973
974 /* Initialize Mode 5 SCRATCHPAGE to 0. */
975 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, 5), 0);
976
977 asd_write_reg_dword(asd_ha, LmRSPMBX(lseq), 0);
978 /* Initialize Mode 0,1,2 and 5 Interrupt Enable and
979 * Interrupt registers. */
980 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 0), LmM0INTEN_MASK);
981 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 0), 0xFFFFFFFF);
982 /* Mode 1 */
983 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 1), LmM1INTEN_MASK);
984 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 1), 0xFFFFFFFF);
985 /* Mode 2 */
986 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 2), LmM2INTEN_MASK);
987 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 2), 0xFFFFFFFF);
988 /* Mode 5 */
989 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 5), LmM5INTEN_MASK);
990 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 5), 0xFFFFFFFF);
991
992 /* Enable HW Timer status. */
993 asd_write_reg_byte(asd_ha, LmHWTSTATEN(lseq), LmHWTSTATEN_MASK);
994
995 /* Enable Primitive Status 0 and 1. */
996 asd_write_reg_dword(asd_ha, LmPRIMSTAT0EN(lseq), LmPRIMSTAT0EN_MASK);
997 asd_write_reg_dword(asd_ha, LmPRIMSTAT1EN(lseq), LmPRIMSTAT1EN_MASK);
998
999 /* Enable Frame Error. */
1000 asd_write_reg_dword(asd_ha, LmFRMERREN(lseq), LmFRMERREN_MASK);
1001 asd_write_reg_byte(asd_ha, LmMnHOLDLVL(lseq, 0), 0x50);
1002
1003 /* Initialize Mode 0 Transfer Level to 512. */
1004 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 0), LmMnXFRLVL_512);
1005 /* Initialize Mode 1 Transfer Level to 256. */
1006 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 1), LmMnXFRLVL_256);
1007
1008 /* Initialize Program Count. */
1009 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1010
1011 /* Enable Blind SG Move. */
1012 asd_write_reg_dword(asd_ha, LmMODECTL(lseq), LmBLIND48);
1013 asd_write_reg_word(asd_ha, LmM3SATATIMER(lseq),
1014 ASD_SATA_INTERLOCK_TIMEOUT);
1015
1016 (void) asd_read_reg_dword(asd_ha, LmREQMBX(lseq));
1017
1018 /* Clear Primitive Status 0 and 1. */
1019 asd_write_reg_dword(asd_ha, LmPRMSTAT0(lseq), 0xFFFFFFFF);
1020 asd_write_reg_dword(asd_ha, LmPRMSTAT1(lseq), 0xFFFFFFFF);
1021
1022 /* Clear HW Timer status. */
1023 asd_write_reg_byte(asd_ha, LmHWTSTAT(lseq), 0xFF);
1024
1025 /* Clear DMA Errors for Mode 0 and 1. */
1026 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 0), 0xFF);
1027 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 1), 0xFF);
1028
1029 /* Clear SG DMA Errors for Mode 0 and 1. */
1030 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 0), 0xFF);
1031 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 1), 0xFF);
1032
1033 /* Clear Mode 0 Buffer Parity Error. */
1034 asd_write_reg_byte(asd_ha, LmMnBUFSTAT(lseq, 0), LmMnBUFPERR);
1035
1036 /* Clear Mode 0 Frame Error register. */
1037 asd_write_reg_dword(asd_ha, LmMnFRMERR(lseq, 0), 0xFFFFFFFF);
1038
1039 /* Reset LSEQ external interrupt arbiter. */
1040 asd_write_reg_byte(asd_ha, LmARP2INTCTL(lseq), RSTINTCTL);
1041
1042 /* Set the Phy SAS for the LmSEQ WWN. */
1043 sas_addr = asd_ha->phys[lseq].phy_desc->sas_addr;
1044 for (i = 0; i < SAS_ADDR_SIZE; i++)
1045 asd_write_reg_byte(asd_ha, LmWWN(lseq) + i, sas_addr[i]);
1046
1047 /* Set the Transmit Size to 1024 bytes, 0 = 256 Dwords. */
1048 asd_write_reg_byte(asd_ha, LmMnXMTSIZE(lseq, 1), 0);
1049
1050 /* Set the Bus Inactivity Time Limit Timer. */
1051 asd_write_reg_word(asd_ha, LmBITL_TIMER(lseq), 9);
1052
1053 /* Enable SATA Port Multiplier. */
1054 asd_write_reg_byte(asd_ha, LmMnSATAFS(lseq, 1), 0x80);
1055
1056 /* Initialize Interrupt Vector[0-10] address in Mode 3.
1057 * See the comment on CSEQ_INT_* */
1058 asd_write_reg_word(asd_ha, LmM3INTVEC0(lseq), lseq_vecs[0]);
1059 asd_write_reg_word(asd_ha, LmM3INTVEC1(lseq), lseq_vecs[1]);
1060 asd_write_reg_word(asd_ha, LmM3INTVEC2(lseq), lseq_vecs[2]);
1061 asd_write_reg_word(asd_ha, LmM3INTVEC3(lseq), lseq_vecs[3]);
1062 asd_write_reg_word(asd_ha, LmM3INTVEC4(lseq), lseq_vecs[4]);
1063 asd_write_reg_word(asd_ha, LmM3INTVEC5(lseq), lseq_vecs[5]);
1064 asd_write_reg_word(asd_ha, LmM3INTVEC6(lseq), lseq_vecs[6]);
1065 asd_write_reg_word(asd_ha, LmM3INTVEC7(lseq), lseq_vecs[7]);
1066 asd_write_reg_word(asd_ha, LmM3INTVEC8(lseq), lseq_vecs[8]);
1067 asd_write_reg_word(asd_ha, LmM3INTVEC9(lseq), lseq_vecs[9]);
1068 asd_write_reg_word(asd_ha, LmM3INTVEC10(lseq), lseq_vecs[10]);
1069 /*
1070 * Program the Link LED control, applicable only for
1071 * Chip Rev. B or later.
1072 */
1073 asd_write_reg_dword(asd_ha, LmCONTROL(lseq),
1074 (LEDTIMER | LEDMODE_TXRX | LEDTIMERS_100ms));
1075
1076 /* Set the Align Rate for SAS and STP mode. */
1077 asd_write_reg_byte(asd_ha, LmM1SASALIGN(lseq), SAS_ALIGN_DEFAULT);
1078 asd_write_reg_byte(asd_ha, LmM1STPALIGN(lseq), STP_ALIGN_DEFAULT);
1079}
1080
1081
1082/**
1083 * asd_post_init_cseq -- clear CSEQ Mode n Int. status and Response mailbox
1084 * @asd_ha: pointer to host adapter struct
1085 */
1086static void asd_post_init_cseq(struct asd_ha_struct *asd_ha)
1087{
1088 int i;
1089
1090 for (i = 0; i < 8; i++)
1091 asd_write_reg_dword(asd_ha, CMnINT(i), 0xFFFFFFFF);
1092 for (i = 0; i < 8; i++)
1093 asd_read_reg_dword(asd_ha, CMnRSPMBX(i));
1094 /* Reset the external interrupt arbiter. */
1095 asd_write_reg_byte(asd_ha, CARP2INTCTL, RSTINTCTL);
1096}
1097
1098/**
1099 * asd_init_ddb_0 -- initialize DDB 0
1100 * @asd_ha: pointer to host adapter structure
1101 *
1102 * Initialize DDB site 0 which is used internally by the sequencer.
1103 */
1104static void asd_init_ddb_0(struct asd_ha_struct *asd_ha)
1105{
1106 int i;
1107
1108 /* Zero out the DDB explicitly */
1109 for (i = 0; i < sizeof(struct asd_ddb_seq_shared); i+=4)
1110 asd_ddbsite_write_dword(asd_ha, 0, i, 0);
1111
1112 asd_ddbsite_write_word(asd_ha, 0,
1113 offsetof(struct asd_ddb_seq_shared, q_free_ddb_head), 0);
1114 asd_ddbsite_write_word(asd_ha, 0,
1115 offsetof(struct asd_ddb_seq_shared, q_free_ddb_tail),
1116 asd_ha->hw_prof.max_ddbs-1);
1117 asd_ddbsite_write_word(asd_ha, 0,
1118 offsetof(struct asd_ddb_seq_shared, q_free_ddb_cnt), 0);
1119 asd_ddbsite_write_word(asd_ha, 0,
1120 offsetof(struct asd_ddb_seq_shared, q_used_ddb_head), 0xFFFF);
1121 asd_ddbsite_write_word(asd_ha, 0,
1122 offsetof(struct asd_ddb_seq_shared, q_used_ddb_tail), 0xFFFF);
1123 asd_ddbsite_write_word(asd_ha, 0,
1124 offsetof(struct asd_ddb_seq_shared, shared_mem_lock), 0);
1125 asd_ddbsite_write_word(asd_ha, 0,
1126 offsetof(struct asd_ddb_seq_shared, smp_conn_tag), 0);
1127 asd_ddbsite_write_word(asd_ha, 0,
1128 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_cnt), 0);
1129 asd_ddbsite_write_word(asd_ha, 0,
1130 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_thresh),
1131 asd_ha->hw_prof.num_phys * 2);
1132 asd_ddbsite_write_byte(asd_ha, 0,
1133 offsetof(struct asd_ddb_seq_shared, settable_max_contexts),0);
1134 asd_ddbsite_write_byte(asd_ha, 0,
1135 offsetof(struct asd_ddb_seq_shared, conn_not_active), 0xFF);
1136 asd_ddbsite_write_byte(asd_ha, 0,
1137 offsetof(struct asd_ddb_seq_shared, phy_is_up), 0x00);
1138 /* DDB 0 is reserved */
1139 set_bit(0, asd_ha->hw_prof.ddb_bitmap);
1140}
1141
1142static void asd_seq_init_ddb_sites(struct asd_ha_struct *asd_ha)
1143{
1144 unsigned int i;
1145 unsigned int ddb_site;
1146
1147 for (ddb_site = 0 ; ddb_site < ASD_MAX_DDBS; ddb_site++)
1148 for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4)
1149 asd_ddbsite_write_dword(asd_ha, ddb_site, i, 0);
1150}
1151
1152/**
1153 * asd_seq_setup_seqs -- setup and initialize central and link sequencers
1154 * @asd_ha: pointer to host adapter structure
1155 */
1156static void asd_seq_setup_seqs(struct asd_ha_struct *asd_ha)
1157{
1158 int lseq;
1159 u8 lseq_mask;
1160
1161 /* Initialize DDB sites */
1162 asd_seq_init_ddb_sites(asd_ha);
1163
1164 /* Initialize SCB sites. Done first to compute some values which
1165 * the rest of the init code depends on. */
1166 asd_init_scb_sites(asd_ha);
1167
1168 /* Initialize CSEQ Scratch RAM registers. */
1169 asd_init_cseq_scratch(asd_ha);
1170
1171 /* Initialize LmSEQ Scratch RAM registers. */
1172 asd_init_lseq_scratch(asd_ha);
1173
1174 /* Initialize CSEQ CIO registers. */
1175 asd_init_cseq_cio(asd_ha);
1176
1177 asd_init_ddb_0(asd_ha);
1178
1179 /* Initialize LmSEQ CIO registers. */
1180 lseq_mask = asd_ha->hw_prof.enabled_phys;
1181 for_each_sequencer(lseq_mask, lseq_mask, lseq)
1182 asd_init_lseq_cio(asd_ha, lseq);
1183 asd_post_init_cseq(asd_ha);
1184}
1185
1186
1187/**
1188 * asd_seq_start_cseq -- start the central sequencer, CSEQ
1189 * @asd_ha: pointer to host adapter structure
1190 */
1191static int asd_seq_start_cseq(struct asd_ha_struct *asd_ha)
1192{
1193 /* Reset the ARP2 instruction to location zero. */
1194 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
1195
1196 /* Unpause the CSEQ */
1197 return asd_unpause_cseq(asd_ha);
1198}
1199
1200/**
1201 * asd_seq_start_lseq -- start a link sequencer
1202 * @asd_ha: pointer to host adapter structure
1203 * @lseq: the link sequencer of interest
1204 */
1205static int asd_seq_start_lseq(struct asd_ha_struct *asd_ha, int lseq)
1206{
1207 /* Reset the ARP2 instruction to location zero. */
1208 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1209
1210 /* Unpause the LmSEQ */
1211 return asd_seq_unpause_lseq(asd_ha, lseq);
1212}
1213
1214int asd_release_firmware(void)
1215{
1216 release_firmware(sequencer_fw);
1217 return 0;
1218}
1219
1220static int asd_request_firmware(struct asd_ha_struct *asd_ha)
1221{
1222 int err, i;
1223 struct sequencer_file_header header;
1224 const struct sequencer_file_header *hdr_ptr;
1225 u32 csum = 0;
1226 u16 *ptr_cseq_vecs, *ptr_lseq_vecs;
1227
1228 if (sequencer_fw)
1229 /* already loaded */
1230 return 0;
1231
1232 err = request_firmware(&sequencer_fw,
1233 SAS_RAZOR_SEQUENCER_FW_FILE,
1234 &asd_ha->pcidev->dev);
1235 if (err)
1236 return err;
1237
1238 hdr_ptr = (const struct sequencer_file_header *)sequencer_fw->data;
1239
1240 header.csum = le32_to_cpu(hdr_ptr->csum);
1241 header.major = le32_to_cpu(hdr_ptr->major);
1242 header.minor = le32_to_cpu(hdr_ptr->minor);
1243 header.cseq_table_offset = le32_to_cpu(hdr_ptr->cseq_table_offset);
1244 header.cseq_table_size = le32_to_cpu(hdr_ptr->cseq_table_size);
1245 header.lseq_table_offset = le32_to_cpu(hdr_ptr->lseq_table_offset);
1246 header.lseq_table_size = le32_to_cpu(hdr_ptr->lseq_table_size);
1247 header.cseq_code_offset = le32_to_cpu(hdr_ptr->cseq_code_offset);
1248 header.cseq_code_size = le32_to_cpu(hdr_ptr->cseq_code_size);
1249 header.lseq_code_offset = le32_to_cpu(hdr_ptr->lseq_code_offset);
1250 header.lseq_code_size = le32_to_cpu(hdr_ptr->lseq_code_size);
1251 header.mode2_task = le16_to_cpu(hdr_ptr->mode2_task);
1252 header.cseq_idle_loop = le16_to_cpu(hdr_ptr->cseq_idle_loop);
1253 header.lseq_idle_loop = le16_to_cpu(hdr_ptr->lseq_idle_loop);
1254
1255 for (i = sizeof(header.csum); i < sequencer_fw->size; i++)
1256 csum += sequencer_fw->data[i];
1257
1258 if (csum != header.csum) {
1259 asd_printk("Firmware file checksum mismatch\n");
1260 return -EINVAL;
1261 }
1262
1263 if (header.cseq_table_size != CSEQ_NUM_VECS ||
1264 header.lseq_table_size != LSEQ_NUM_VECS) {
1265 asd_printk("Firmware file table size mismatch\n");
1266 return -EINVAL;
1267 }
1268
1269 asd_printk("Found sequencer Firmware version %d.%d (%s)\n",
1270 header.major, header.minor, hdr_ptr->version);
1271
1272 if (header.major != SAS_RAZOR_SEQUENCER_FW_MAJOR) {
1273 asd_printk("Firmware Major Version Mismatch;"
1274 "driver requires version %d.X",
1275 SAS_RAZOR_SEQUENCER_FW_MAJOR);
1276 return -EINVAL;
1277 }
1278
1279 ptr_cseq_vecs = (u16 *)&sequencer_fw->data[header.cseq_table_offset];
1280 ptr_lseq_vecs = (u16 *)&sequencer_fw->data[header.lseq_table_offset];
1281 mode2_task = header.mode2_task;
1282 cseq_idle_loop = header.cseq_idle_loop;
1283 lseq_idle_loop = header.lseq_idle_loop;
1284
1285 for (i = 0; i < CSEQ_NUM_VECS; i++)
1286 cseq_vecs[i] = le16_to_cpu(ptr_cseq_vecs[i]);
1287
1288 for (i = 0; i < LSEQ_NUM_VECS; i++)
1289 lseq_vecs[i] = le16_to_cpu(ptr_lseq_vecs[i]);
1290
1291 cseq_code = &sequencer_fw->data[header.cseq_code_offset];
1292 cseq_code_size = header.cseq_code_size;
1293 lseq_code = &sequencer_fw->data[header.lseq_code_offset];
1294 lseq_code_size = header.lseq_code_size;
1295
1296 return 0;
1297}
1298
1299int asd_init_seqs(struct asd_ha_struct *asd_ha)
1300{
1301 int err;
1302
1303 err = asd_request_firmware(asd_ha);
1304
1305 if (err) {
1306 asd_printk("Failed to load sequencer firmware file %s, error %d\n",
1307 SAS_RAZOR_SEQUENCER_FW_FILE, err);
1308 return err;
1309 }
1310
1311 err = asd_seq_download_seqs(asd_ha);
1312 if (err) {
1313 asd_printk("couldn't download sequencers for %s\n",
1314 pci_name(asd_ha->pcidev));
1315 return err;
1316 }
1317
1318 asd_seq_setup_seqs(asd_ha);
1319
1320 return 0;
1321}
1322
1323int asd_start_seqs(struct asd_ha_struct *asd_ha)
1324{
1325 int err;
1326 u8 lseq_mask;
1327 int lseq;
1328
1329 err = asd_seq_start_cseq(asd_ha);
1330 if (err) {
1331 asd_printk("couldn't start CSEQ for %s\n",
1332 pci_name(asd_ha->pcidev));
1333 return err;
1334 }
1335
1336 lseq_mask = asd_ha->hw_prof.enabled_phys;
1337 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
1338 err = asd_seq_start_lseq(asd_ha, lseq);
1339 if (err) {
1340 asd_printk("couldn't start LSEQ %d for %s\n", lseq,
1341 pci_name(asd_ha->pcidev));
1342 return err;
1343 }
1344 }
1345
1346 return 0;
1347}
1348
1349/**
1350 * asd_update_port_links -- update port_map_by_links and phy_is_up
1351 * @asd_ha: pointer to host adapter structure
1352 * @phy: pointer to the phy which has been added to a port
1353 *
1354 * 1) When a link reset has completed and we got BYTES DMAED with a
1355 * valid frame we call this function for that phy, to indicate that
1356 * the phy is up, i.e. we update the phy_is_up in DDB 0. The
1357 * sequencer checks phy_is_up when pending SCBs are to be sent, and
1358 * when an open address frame has been received.
1359 *
1360 * 2) When we know of ports, we call this function to update the map
1361 * of phys participaing in that port, i.e. we update the
1362 * port_map_by_links in DDB 0. When a HARD_RESET primitive has been
1363 * received, the sequencer disables all phys in that port.
1364 * port_map_by_links is also used as the conn_mask byte in the
1365 * initiator/target port DDB.
1366 */
1367void asd_update_port_links(struct asd_ha_struct *asd_ha, struct asd_phy *phy)
1368{
1369 const u8 phy_mask = (u8) phy->asd_port->phy_mask;
1370 u8 phy_is_up;
1371 u8 mask;
1372 int i, err;
1373 unsigned long flags;
1374
1375 spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
1376 for_each_phy(phy_mask, mask, i)
1377 asd_ddbsite_write_byte(asd_ha, 0,
1378 offsetof(struct asd_ddb_seq_shared,
1379 port_map_by_links)+i,phy_mask);
1380
1381 for (i = 0; i < 12; i++) {
1382 phy_is_up = asd_ddbsite_read_byte(asd_ha, 0,
1383 offsetof(struct asd_ddb_seq_shared, phy_is_up));
1384 err = asd_ddbsite_update_byte(asd_ha, 0,
1385 offsetof(struct asd_ddb_seq_shared, phy_is_up),
1386 phy_is_up,
1387 phy_is_up | phy_mask);
1388 if (!err)
1389 break;
1390 else if (err == -EFAULT) {
1391 asd_printk("phy_is_up: parity error in DDB 0\n");
1392 break;
1393 }
1394 }
1395 spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
1396
1397 if (err)
1398 asd_printk("couldn't update DDB 0:error:%d\n", err);
1399}
1400
1401MODULE_FIRMWARE(SAS_RAZOR_SEQUENCER_FW_FILE);
1/*
2 * Aic94xx SAS/SATA driver sequencer interface.
3 *
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
6 *
7 * Parts of this code adapted from David Chaw's adp94xx_seq.c.
8 *
9 * This file is licensed under GPLv2.
10 *
11 * This file is part of the aic94xx driver.
12 *
13 * The aic94xx driver is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; version 2 of the
16 * License.
17 *
18 * The aic94xx driver is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with the aic94xx driver; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 *
27 */
28
29#include <linux/delay.h>
30#include <linux/gfp.h>
31#include <linux/pci.h>
32#include <linux/module.h>
33#include <linux/firmware.h>
34#include "aic94xx_reg.h"
35#include "aic94xx_hwi.h"
36
37#include "aic94xx_seq.h"
38#include "aic94xx_dump.h"
39
40/* It takes no more than 0.05 us for an instruction
41 * to complete. So waiting for 1 us should be more than
42 * plenty.
43 */
44#define PAUSE_DELAY 1
45#define PAUSE_TRIES 1000
46
47static const struct firmware *sequencer_fw;
48static u16 cseq_vecs[CSEQ_NUM_VECS], lseq_vecs[LSEQ_NUM_VECS], mode2_task,
49 cseq_idle_loop, lseq_idle_loop;
50static const u8 *cseq_code, *lseq_code;
51static u32 cseq_code_size, lseq_code_size;
52
53static u16 first_scb_site_no = 0xFFFF;
54static u16 last_scb_site_no;
55
56/* ---------- Pause/Unpause CSEQ/LSEQ ---------- */
57
58/**
59 * asd_pause_cseq - pause the central sequencer
60 * @asd_ha: pointer to host adapter structure
61 *
62 * Return 0 on success, negative on failure.
63 */
64static int asd_pause_cseq(struct asd_ha_struct *asd_ha)
65{
66 int count = PAUSE_TRIES;
67 u32 arp2ctl;
68
69 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
70 if (arp2ctl & PAUSED)
71 return 0;
72
73 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl | EPAUSE);
74 do {
75 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
76 if (arp2ctl & PAUSED)
77 return 0;
78 udelay(PAUSE_DELAY);
79 } while (--count > 0);
80
81 ASD_DPRINTK("couldn't pause CSEQ\n");
82 return -1;
83}
84
85/**
86 * asd_unpause_cseq - unpause the central sequencer.
87 * @asd_ha: pointer to host adapter structure.
88 *
89 * Return 0 on success, negative on error.
90 */
91static int asd_unpause_cseq(struct asd_ha_struct *asd_ha)
92{
93 u32 arp2ctl;
94 int count = PAUSE_TRIES;
95
96 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
97 if (!(arp2ctl & PAUSED))
98 return 0;
99
100 asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl & ~EPAUSE);
101 do {
102 arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
103 if (!(arp2ctl & PAUSED))
104 return 0;
105 udelay(PAUSE_DELAY);
106 } while (--count > 0);
107
108 ASD_DPRINTK("couldn't unpause the CSEQ\n");
109 return -1;
110}
111
112/**
113 * asd_seq_pause_lseq - pause a link sequencer
114 * @asd_ha: pointer to a host adapter structure
115 * @lseq: link sequencer of interest
116 *
117 * Return 0 on success, negative on error.
118 */
119static int asd_seq_pause_lseq(struct asd_ha_struct *asd_ha, int lseq)
120{
121 u32 arp2ctl;
122 int count = PAUSE_TRIES;
123
124 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
125 if (arp2ctl & PAUSED)
126 return 0;
127
128 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl | EPAUSE);
129 do {
130 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
131 if (arp2ctl & PAUSED)
132 return 0;
133 udelay(PAUSE_DELAY);
134 } while (--count > 0);
135
136 ASD_DPRINTK("couldn't pause LSEQ %d\n", lseq);
137 return -1;
138}
139
140/**
141 * asd_pause_lseq - pause the link sequencer(s)
142 * @asd_ha: pointer to host adapter structure
143 * @lseq_mask: mask of link sequencers of interest
144 *
145 * Return 0 on success, negative on failure.
146 */
147static int asd_pause_lseq(struct asd_ha_struct *asd_ha, u8 lseq_mask)
148{
149 int lseq;
150 int err = 0;
151
152 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
153 err = asd_seq_pause_lseq(asd_ha, lseq);
154 if (err)
155 return err;
156 }
157
158 return err;
159}
160
161/**
162 * asd_seq_unpause_lseq - unpause a link sequencer
163 * @asd_ha: pointer to host adapter structure
164 * @lseq: link sequencer of interest
165 *
166 * Return 0 on success, negative on error.
167 */
168static int asd_seq_unpause_lseq(struct asd_ha_struct *asd_ha, int lseq)
169{
170 u32 arp2ctl;
171 int count = PAUSE_TRIES;
172
173 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
174 if (!(arp2ctl & PAUSED))
175 return 0;
176
177 asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl & ~EPAUSE);
178 do {
179 arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
180 if (!(arp2ctl & PAUSED))
181 return 0;
182 udelay(PAUSE_DELAY);
183 } while (--count > 0);
184
185 ASD_DPRINTK("couldn't unpause LSEQ %d\n", lseq);
186 return 0;
187}
188
189
190/* ---------- Downloading CSEQ/LSEQ microcode ---------- */
191
192static int asd_verify_cseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
193 u32 size)
194{
195 u32 addr = CSEQ_RAM_REG_BASE_ADR;
196 const u32 *prog = (u32 *) _prog;
197 u32 i;
198
199 for (i = 0; i < size; i += 4, prog++, addr += 4) {
200 u32 val = asd_read_reg_dword(asd_ha, addr);
201
202 if (le32_to_cpu(*prog) != val) {
203 asd_printk("%s: cseq verify failed at %u "
204 "read:0x%x, wanted:0x%x\n",
205 pci_name(asd_ha->pcidev),
206 i, val, le32_to_cpu(*prog));
207 return -1;
208 }
209 }
210 ASD_DPRINTK("verified %d bytes, passed\n", size);
211 return 0;
212}
213
214/**
215 * asd_verify_lseq - verify the microcode of a link sequencer
216 * @asd_ha: pointer to host adapter structure
217 * @_prog: pointer to the microcode
218 * @size: size of the microcode in bytes
219 * @lseq: link sequencer of interest
220 *
221 * The link sequencer code is accessed in 4 KB pages, which are selected
222 * by setting LmRAMPAGE (bits 8 and 9) of the LmBISTCTL1 register.
223 * The 10 KB LSEQm instruction code is mapped, page at a time, at
224 * LmSEQRAM address.
225 */
226static int asd_verify_lseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
227 u32 size, int lseq)
228{
229#define LSEQ_CODEPAGE_SIZE 4096
230 int pages = (size + LSEQ_CODEPAGE_SIZE - 1) / LSEQ_CODEPAGE_SIZE;
231 u32 page;
232 const u32 *prog = (u32 *) _prog;
233
234 for (page = 0; page < pages; page++) {
235 u32 i;
236
237 asd_write_reg_dword(asd_ha, LmBISTCTL1(lseq),
238 page << LmRAMPAGE_LSHIFT);
239 for (i = 0; size > 0 && i < LSEQ_CODEPAGE_SIZE;
240 i += 4, prog++, size-=4) {
241
242 u32 val = asd_read_reg_dword(asd_ha, LmSEQRAM(lseq)+i);
243
244 if (le32_to_cpu(*prog) != val) {
245 asd_printk("%s: LSEQ%d verify failed "
246 "page:%d, offs:%d\n",
247 pci_name(asd_ha->pcidev),
248 lseq, page, i);
249 return -1;
250 }
251 }
252 }
253 ASD_DPRINTK("LSEQ%d verified %d bytes, passed\n", lseq,
254 (int)((u8 *)prog-_prog));
255 return 0;
256}
257
258/**
259 * asd_verify_seq -- verify CSEQ/LSEQ microcode
260 * @asd_ha: pointer to host adapter structure
261 * @prog: pointer to microcode
262 * @size: size of the microcode
263 * @lseq_mask: if 0, verify CSEQ microcode, else mask of LSEQs of interest
264 *
265 * Return 0 if microcode is correct, negative on mismatch.
266 */
267static int asd_verify_seq(struct asd_ha_struct *asd_ha, const u8 *prog,
268 u32 size, u8 lseq_mask)
269{
270 if (lseq_mask == 0)
271 return asd_verify_cseq(asd_ha, prog, size);
272 else {
273 int lseq, err;
274
275 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
276 err = asd_verify_lseq(asd_ha, prog, size, lseq);
277 if (err)
278 return err;
279 }
280 }
281
282 return 0;
283}
284#define ASD_DMA_MODE_DOWNLOAD
285#ifdef ASD_DMA_MODE_DOWNLOAD
286/* This is the size of the CSEQ Mapped instruction page */
287#define MAX_DMA_OVLY_COUNT ((1U << 14)-1)
288static int asd_download_seq(struct asd_ha_struct *asd_ha,
289 const u8 * const prog, u32 size, u8 lseq_mask)
290{
291 u32 comstaten;
292 u32 reg;
293 int page;
294 const int pages = (size + MAX_DMA_OVLY_COUNT - 1) / MAX_DMA_OVLY_COUNT;
295 struct asd_dma_tok *token;
296 int err = 0;
297
298 if (size % 4) {
299 asd_printk("sequencer program not multiple of 4\n");
300 return -1;
301 }
302
303 asd_pause_cseq(asd_ha);
304 asd_pause_lseq(asd_ha, 0xFF);
305
306 /* save, disable and clear interrupts */
307 comstaten = asd_read_reg_dword(asd_ha, COMSTATEN);
308 asd_write_reg_dword(asd_ha, COMSTATEN, 0);
309 asd_write_reg_dword(asd_ha, COMSTAT, COMSTAT_MASK);
310
311 asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
312 asd_write_reg_dword(asd_ha, CHIMINT, CHIMINT_MASK);
313
314 token = asd_alloc_coherent(asd_ha, MAX_DMA_OVLY_COUNT, GFP_KERNEL);
315 if (!token) {
316 asd_printk("out of memory for dma SEQ download\n");
317 err = -ENOMEM;
318 goto out;
319 }
320 ASD_DPRINTK("dma-ing %d bytes\n", size);
321
322 for (page = 0; page < pages; page++) {
323 int i;
324 u32 left = min(size-page*MAX_DMA_OVLY_COUNT,
325 (u32)MAX_DMA_OVLY_COUNT);
326
327 memcpy(token->vaddr, prog + page*MAX_DMA_OVLY_COUNT, left);
328 asd_write_reg_addr(asd_ha, OVLYDMAADR, token->dma_handle);
329 asd_write_reg_dword(asd_ha, OVLYDMACNT, left);
330 reg = !page ? RESETOVLYDMA : 0;
331 reg |= (STARTOVLYDMA | OVLYHALTERR);
332 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
333 /* Start DMA. */
334 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
335
336 for (i = PAUSE_TRIES*100; i > 0; i--) {
337 u32 dmadone = asd_read_reg_dword(asd_ha, OVLYDMACTL);
338 if (!(dmadone & OVLYDMAACT))
339 break;
340 udelay(PAUSE_DELAY);
341 }
342 }
343
344 reg = asd_read_reg_dword(asd_ha, COMSTAT);
345 if (!(reg & OVLYDMADONE) || (reg & OVLYERR)
346 || (asd_read_reg_dword(asd_ha, CHIMINT) & DEVEXCEPT_MASK)){
347 asd_printk("%s: error DMA-ing sequencer code\n",
348 pci_name(asd_ha->pcidev));
349 err = -ENODEV;
350 }
351
352 asd_free_coherent(asd_ha, token);
353 out:
354 asd_write_reg_dword(asd_ha, COMSTATEN, comstaten);
355
356 return err ? : asd_verify_seq(asd_ha, prog, size, lseq_mask);
357}
358#else /* ASD_DMA_MODE_DOWNLOAD */
359static int asd_download_seq(struct asd_ha_struct *asd_ha, const u8 *_prog,
360 u32 size, u8 lseq_mask)
361{
362 int i;
363 u32 reg = 0;
364 const u32 *prog = (u32 *) _prog;
365
366 if (size % 4) {
367 asd_printk("sequencer program not multiple of 4\n");
368 return -1;
369 }
370
371 asd_pause_cseq(asd_ha);
372 asd_pause_lseq(asd_ha, 0xFF);
373
374 reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
375 reg |= PIOCMODE;
376
377 asd_write_reg_dword(asd_ha, OVLYDMACNT, size);
378 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
379
380 ASD_DPRINTK("downloading %s sequencer%s in PIO mode...\n",
381 lseq_mask ? "LSEQ" : "CSEQ", lseq_mask ? "s" : "");
382
383 for (i = 0; i < size; i += 4, prog++)
384 asd_write_reg_dword(asd_ha, SPIODATA, *prog);
385
386 reg = (reg & ~PIOCMODE) | OVLYHALTERR;
387 asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
388
389 return asd_verify_seq(asd_ha, _prog, size, lseq_mask);
390}
391#endif /* ASD_DMA_MODE_DOWNLOAD */
392
393/**
394 * asd_seq_download_seqs - download the sequencer microcode
395 * @asd_ha: pointer to host adapter structure
396 *
397 * Download the central and link sequencer microcode.
398 */
399static int asd_seq_download_seqs(struct asd_ha_struct *asd_ha)
400{
401 int err;
402
403 if (!asd_ha->hw_prof.enabled_phys) {
404 asd_printk("%s: no enabled phys!\n", pci_name(asd_ha->pcidev));
405 return -ENODEV;
406 }
407
408 /* Download the CSEQ */
409 ASD_DPRINTK("downloading CSEQ...\n");
410 err = asd_download_seq(asd_ha, cseq_code, cseq_code_size, 0);
411 if (err) {
412 asd_printk("CSEQ download failed:%d\n", err);
413 return err;
414 }
415
416 /* Download the Link Sequencers code. All of the Link Sequencers
417 * microcode can be downloaded at the same time.
418 */
419 ASD_DPRINTK("downloading LSEQs...\n");
420 err = asd_download_seq(asd_ha, lseq_code, lseq_code_size,
421 asd_ha->hw_prof.enabled_phys);
422 if (err) {
423 /* Try it one at a time */
424 u8 lseq;
425 u8 lseq_mask = asd_ha->hw_prof.enabled_phys;
426
427 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
428 err = asd_download_seq(asd_ha, lseq_code,
429 lseq_code_size, 1<<lseq);
430 if (err)
431 break;
432 }
433 }
434 if (err)
435 asd_printk("LSEQs download failed:%d\n", err);
436
437 return err;
438}
439
440/* ---------- Initializing the chip, chip memory, etc. ---------- */
441
442/**
443 * asd_init_cseq_mip - initialize CSEQ mode independent pages 4-7
444 * @asd_ha: pointer to host adapter structure
445 */
446static void asd_init_cseq_mip(struct asd_ha_struct *asd_ha)
447{
448 /* CSEQ Mode Independent, page 4 setup. */
449 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_HEAD, 0xFFFF);
450 asd_write_reg_word(asd_ha, CSEQ_Q_EXE_TAIL, 0xFFFF);
451 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_HEAD, 0xFFFF);
452 asd_write_reg_word(asd_ha, CSEQ_Q_DONE_TAIL, 0xFFFF);
453 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_HEAD, 0xFFFF);
454 asd_write_reg_word(asd_ha, CSEQ_Q_SEND_TAIL, 0xFFFF);
455 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_HEAD, 0xFFFF);
456 asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_TAIL, 0xFFFF);
457 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_HEAD, 0xFFFF);
458 asd_write_reg_word(asd_ha, CSEQ_Q_COPY_TAIL, 0xFFFF);
459 asd_write_reg_word(asd_ha, CSEQ_REG0, 0);
460 asd_write_reg_word(asd_ha, CSEQ_REG1, 0);
461 asd_write_reg_dword(asd_ha, CSEQ_REG2, 0);
462 asd_write_reg_byte(asd_ha, CSEQ_LINK_CTL_Q_MAP, 0);
463 {
464 u8 con = asd_read_reg_byte(asd_ha, CCONEXIST);
465 u8 val = hweight8(con);
466 asd_write_reg_byte(asd_ha, CSEQ_MAX_CSEQ_MODE, (val<<4)|val);
467 }
468 asd_write_reg_word(asd_ha, CSEQ_FREE_LIST_HACK_COUNT, 0);
469
470 /* CSEQ Mode independent, page 5 setup. */
471 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE, 0);
472 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE+4, 0);
473 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT, 0);
474 asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT+4, 0);
475 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_HEAD, 0xFFFF);
476 asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_TAIL, 0xFFFF);
477 asd_write_reg_word(asd_ha, CSEQ_NEED_EST_NEXUS_SCB, 0);
478 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_HEAD, 0);
479 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_TAIL, 0);
480 asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_SCB_OFFSET, 0);
481
482 /* CSEQ Mode independent, page 6 setup. */
483 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR0, 0);
484 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR1, 0);
485 asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_SCBPTR, 0);
486 asd_write_reg_byte(asd_ha, CSEQ_INT_ROUT_MODE, 0);
487 asd_write_reg_byte(asd_ha, CSEQ_ISR_SCRATCH_FLAGS, 0);
488 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_SINDEX, 0);
489 asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_DINDEX, 0);
490 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_HEAD, 0xFFFF);
491 asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_TAIL, 0xFFFF);
492 /* Calculate the free scb mask. */
493 {
494 u16 cmdctx = asd_get_cmdctx_size(asd_ha);
495 cmdctx = (~((cmdctx/128)-1)) >> 8;
496 asd_write_reg_byte(asd_ha, CSEQ_FREE_SCB_MASK, (u8)cmdctx);
497 }
498 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_HEAD,
499 first_scb_site_no);
500 asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_TAIL,
501 last_scb_site_no);
502 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_HEAD, 0xFFFF);
503 asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_TAIL, 0xFFFF);
504
505 /* CSEQ Mode independent, page 7 setup. */
506 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE, 0);
507 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE+4, 0);
508 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT, 0);
509 asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT+4, 0);
510 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_HEAD, 0xFFFF);
511 asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_TAIL, 0xFFFF);
512 asd_write_reg_word(asd_ha, CSEQ_NEED_EMPTY_SCB, 0);
513 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_HEAD, 0);
514 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_TAIL, 0);
515 asd_write_reg_byte(asd_ha, CSEQ_EMPTY_SCB_OFFSET, 0);
516 asd_write_reg_word(asd_ha, CSEQ_PRIMITIVE_DATA, 0);
517 asd_write_reg_dword(asd_ha, CSEQ_TIMEOUT_CONST, 0);
518}
519
520/**
521 * asd_init_cseq_mdp - initialize CSEQ Mode dependent pages
522 * @asd_ha: pointer to host adapter structure
523 */
524static void asd_init_cseq_mdp(struct asd_ha_struct *asd_ha)
525{
526 int i;
527 int moffs;
528
529 moffs = CSEQ_PAGE_SIZE * 2;
530
531 /* CSEQ Mode dependent, modes 0-7, page 0 setup. */
532 for (i = 0; i < 8; i++) {
533 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SINDEX, 0);
534 asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCBPTR, 0);
535 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_HEAD, 0xFFFF);
536 asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_TAIL, 0xFFFF);
537 asd_write_reg_byte(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCRPAGE, 0);
538 }
539
540 /* CSEQ Mode dependent, mode 0-7, page 1 and 2 shall be ignored. */
541
542 /* CSEQ Mode dependent, mode 8, page 0 setup. */
543 asd_write_reg_word(asd_ha, CSEQ_RET_ADDR, 0xFFFF);
544 asd_write_reg_word(asd_ha, CSEQ_RET_SCBPTR, 0);
545 asd_write_reg_word(asd_ha, CSEQ_SAVE_SCBPTR, 0);
546 asd_write_reg_word(asd_ha, CSEQ_EMPTY_TRANS_CTX, 0);
547 asd_write_reg_word(asd_ha, CSEQ_RESP_LEN, 0);
548 asd_write_reg_word(asd_ha, CSEQ_TMF_SCBPTR, 0);
549 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_PREV_SCB, 0);
550 asd_write_reg_word(asd_ha, CSEQ_GLOBAL_HEAD, 0);
551 asd_write_reg_word(asd_ha, CSEQ_CLEAR_LU_HEAD, 0);
552 asd_write_reg_byte(asd_ha, CSEQ_TMF_OPCODE, 0);
553 asd_write_reg_byte(asd_ha, CSEQ_SCRATCH_FLAGS, 0);
554 asd_write_reg_word(asd_ha, CSEQ_HSB_SITE, 0);
555 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_SCB_SITE,
556 (u16)last_scb_site_no+1);
557 asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_DDB_SITE,
558 (u16)asd_ha->hw_prof.max_ddbs);
559
560 /* CSEQ Mode dependent, mode 8, page 1 setup. */
561 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR, 0);
562 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR + 4, 0);
563 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK, 0);
564 asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK + 4, 0);
565
566 /* CSEQ Mode dependent, mode 8, page 2 setup. */
567 /* Tell the sequencer the bus address of the first SCB. */
568 asd_write_reg_addr(asd_ha, CSEQ_HQ_NEW_POINTER,
569 asd_ha->seq.next_scb.dma_handle);
570 ASD_DPRINTK("First SCB dma_handle: 0x%llx\n",
571 (unsigned long long)asd_ha->seq.next_scb.dma_handle);
572
573 /* Tell the sequencer the first Done List entry address. */
574 asd_write_reg_addr(asd_ha, CSEQ_HQ_DONE_BASE,
575 asd_ha->seq.actual_dl->dma_handle);
576
577 /* Initialize the Q_DONE_POINTER with the least significant
578 * 4 bytes of the first Done List address. */
579 asd_write_reg_dword(asd_ha, CSEQ_HQ_DONE_POINTER,
580 ASD_BUSADDR_LO(asd_ha->seq.actual_dl->dma_handle));
581
582 asd_write_reg_byte(asd_ha, CSEQ_HQ_DONE_PASS, ASD_DEF_DL_TOGGLE);
583
584 /* CSEQ Mode dependent, mode 8, page 3 shall be ignored. */
585}
586
587/**
588 * asd_init_cseq_scratch -- setup and init CSEQ
589 * @asd_ha: pointer to host adapter structure
590 *
591 * Setup and initialize Central sequencers. Initialize the mode
592 * independent and dependent scratch page to the default settings.
593 */
594static void asd_init_cseq_scratch(struct asd_ha_struct *asd_ha)
595{
596 asd_init_cseq_mip(asd_ha);
597 asd_init_cseq_mdp(asd_ha);
598}
599
600/**
601 * asd_init_lseq_mip -- initialize LSEQ Mode independent pages 0-3
602 * @asd_ha: pointer to host adapter structure
603 */
604static void asd_init_lseq_mip(struct asd_ha_struct *asd_ha, u8 lseq)
605{
606 int i;
607
608 /* LSEQ Mode independent page 0 setup. */
609 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_HEAD(lseq), 0xFFFF);
610 asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_TAIL(lseq), 0xFFFF);
611 asd_write_reg_byte(asd_ha, LmSEQ_LINK_NUMBER(lseq), lseq);
612 asd_write_reg_byte(asd_ha, LmSEQ_SCRATCH_FLAGS(lseq),
613 ASD_NOTIFY_ENABLE_SPINUP);
614 asd_write_reg_dword(asd_ha, LmSEQ_CONNECTION_STATE(lseq),0x08000000);
615 asd_write_reg_word(asd_ha, LmSEQ_CONCTL(lseq), 0);
616 asd_write_reg_byte(asd_ha, LmSEQ_CONSTAT(lseq), 0);
617 asd_write_reg_byte(asd_ha, LmSEQ_CONNECTION_MODES(lseq), 0);
618 asd_write_reg_word(asd_ha, LmSEQ_REG1_ISR(lseq), 0);
619 asd_write_reg_word(asd_ha, LmSEQ_REG2_ISR(lseq), 0);
620 asd_write_reg_word(asd_ha, LmSEQ_REG3_ISR(lseq), 0);
621 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq), 0);
622 asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq)+4, 0);
623
624 /* LSEQ Mode independent page 1 setup. */
625 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR0(lseq), 0xFFFF);
626 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR1(lseq), 0xFFFF);
627 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR2(lseq), 0xFFFF);
628 asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR3(lseq), 0xFFFF);
629 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE0(lseq), 0);
630 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE1(lseq), 0);
631 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE2(lseq), 0);
632 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE3(lseq), 0);
633 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_HEAD(lseq), 0);
634 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_TAIL(lseq), 0);
635 asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_BUF_AVAIL(lseq), 0);
636 asd_write_reg_dword(asd_ha, LmSEQ_TIMEOUT_CONST(lseq), 0);
637 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_SINDEX(lseq), 0);
638 asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_DINDEX(lseq), 0);
639
640 /* LSEQ Mode Independent page 2 setup. */
641 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR0(lseq), 0xFFFF);
642 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR1(lseq), 0xFFFF);
643 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR2(lseq), 0xFFFF);
644 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR3(lseq), 0xFFFF);
645 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD0(lseq), 0);
646 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD1(lseq), 0);
647 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD2(lseq), 0);
648 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD3(lseq), 0);
649 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_HEAD(lseq), 0);
650 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_TAIL(lseq), 0);
651 asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_BUFS_AVAIL(lseq), 0);
652 for (i = 0; i < 12; i += 4)
653 asd_write_reg_dword(asd_ha, LmSEQ_ATA_SCR_REGS(lseq) + i, 0);
654
655 /* LSEQ Mode Independent page 3 setup. */
656
657 /* Device present timer timeout */
658 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TMR_TOUT_CONST(lseq),
659 ASD_DEV_PRESENT_TIMEOUT);
660
661 /* SATA interlock timer disabled */
662 asd_write_reg_dword(asd_ha, LmSEQ_SATA_INTERLOCK_TIMEOUT(lseq),
663 ASD_SATA_INTERLOCK_TIMEOUT);
664
665 /* STP shutdown timer timeout constant, IGNORED by the sequencer,
666 * always 0. */
667 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMEOUT(lseq),
668 ASD_STP_SHUTDOWN_TIMEOUT);
669
670 asd_write_reg_dword(asd_ha, LmSEQ_SRST_ASSERT_TIMEOUT(lseq),
671 ASD_SRST_ASSERT_TIMEOUT);
672
673 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMEOUT(lseq),
674 ASD_RCV_FIS_TIMEOUT);
675
676 asd_write_reg_dword(asd_ha, LmSEQ_ONE_MILLISEC_TIMEOUT(lseq),
677 ASD_ONE_MILLISEC_TIMEOUT);
678
679 /* COM_INIT timer */
680 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(lseq),
681 ASD_TEN_MILLISEC_TIMEOUT);
682
683 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMEOUT(lseq),
684 ASD_SMP_RCV_TIMEOUT);
685}
686
687/**
688 * asd_init_lseq_mdp -- initialize LSEQ mode dependent pages.
689 * @asd_ha: pointer to host adapter structure
690 */
691static void asd_init_lseq_mdp(struct asd_ha_struct *asd_ha, int lseq)
692{
693 int i;
694 u32 moffs;
695 u16 ret_addr[] = {
696 0xFFFF, /* mode 0 */
697 0xFFFF, /* mode 1 */
698 mode2_task, /* mode 2 */
699 0,
700 0xFFFF, /* mode 4/5 */
701 0xFFFF, /* mode 4/5 */
702 };
703
704 /*
705 * Mode 0,1,2 and 4/5 have common field on page 0 for the first
706 * 14 bytes.
707 */
708 for (i = 0; i < 3; i++) {
709 moffs = i * LSEQ_MODE_SCRATCH_SIZE;
710 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR(lseq)+moffs,
711 ret_addr[i]);
712 asd_write_reg_word(asd_ha, LmSEQ_REG0_MODE(lseq)+moffs, 0);
713 asd_write_reg_word(asd_ha, LmSEQ_MODE_FLAGS(lseq)+moffs, 0);
714 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR2(lseq)+moffs,0xFFFF);
715 asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR1(lseq)+moffs,0xFFFF);
716 asd_write_reg_byte(asd_ha, LmSEQ_OPCODE_TO_CSEQ(lseq)+moffs,0);
717 asd_write_reg_word(asd_ha, LmSEQ_DATA_TO_CSEQ(lseq)+moffs,0);
718 }
719 /*
720 * Mode 5 page 0 overlaps the same scratch page with Mode 0 page 3.
721 */
722 asd_write_reg_word(asd_ha,
723 LmSEQ_RET_ADDR(lseq)+LSEQ_MODE5_PAGE0_OFFSET,
724 ret_addr[5]);
725 asd_write_reg_word(asd_ha,
726 LmSEQ_REG0_MODE(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
727 asd_write_reg_word(asd_ha,
728 LmSEQ_MODE_FLAGS(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
729 asd_write_reg_word(asd_ha,
730 LmSEQ_RET_ADDR2(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
731 asd_write_reg_word(asd_ha,
732 LmSEQ_RET_ADDR1(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
733 asd_write_reg_byte(asd_ha,
734 LmSEQ_OPCODE_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
735 asd_write_reg_word(asd_ha,
736 LmSEQ_DATA_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
737
738 /* LSEQ Mode dependent 0, page 0 setup. */
739 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_DDB_SITE(lseq),
740 (u16)asd_ha->hw_prof.max_ddbs);
741 asd_write_reg_word(asd_ha, LmSEQ_EMPTY_TRANS_CTX(lseq), 0);
742 asd_write_reg_word(asd_ha, LmSEQ_RESP_LEN(lseq), 0);
743 asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_SCB_SITE(lseq),
744 (u16)last_scb_site_no+1);
745 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq),
746 (u16) ((LmM0INTEN_MASK & 0xFFFF0000) >> 16));
747 asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq) + 2,
748 (u16) LmM0INTEN_MASK & 0xFFFF);
749 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_FRM_LEN(lseq), 0);
750 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_PROTOCOL(lseq), 0);
751 asd_write_reg_byte(asd_ha, LmSEQ_RESP_STATUS(lseq), 0);
752 asd_write_reg_byte(asd_ha, LmSEQ_LAST_LOADED_SGE(lseq), 0);
753 asd_write_reg_word(asd_ha, LmSEQ_SAVE_SCBPTR(lseq), 0);
754
755 /* LSEQ mode dependent, mode 1, page 0 setup. */
756 asd_write_reg_word(asd_ha, LmSEQ_Q_XMIT_HEAD(lseq), 0xFFFF);
757 asd_write_reg_word(asd_ha, LmSEQ_M1_EMPTY_TRANS_CTX(lseq), 0);
758 asd_write_reg_word(asd_ha, LmSEQ_INI_CONN_TAG(lseq), 0);
759 asd_write_reg_byte(asd_ha, LmSEQ_FAILED_OPEN_STATUS(lseq), 0);
760 asd_write_reg_byte(asd_ha, LmSEQ_XMIT_REQUEST_TYPE(lseq), 0);
761 asd_write_reg_byte(asd_ha, LmSEQ_M1_RESP_STATUS(lseq), 0);
762 asd_write_reg_byte(asd_ha, LmSEQ_M1_LAST_LOADED_SGE(lseq), 0);
763 asd_write_reg_word(asd_ha, LmSEQ_M1_SAVE_SCBPTR(lseq), 0);
764
765 /* LSEQ Mode dependent mode 2, page 0 setup */
766 asd_write_reg_word(asd_ha, LmSEQ_PORT_COUNTER(lseq), 0);
767 asd_write_reg_word(asd_ha, LmSEQ_PM_TABLE_PTR(lseq), 0);
768 asd_write_reg_word(asd_ha, LmSEQ_SATA_INTERLOCK_TMR_SAVE(lseq), 0);
769 asd_write_reg_word(asd_ha, LmSEQ_IP_BITL(lseq), 0);
770 asd_write_reg_word(asd_ha, LmSEQ_COPY_SMP_CONN_TAG(lseq), 0);
771 asd_write_reg_byte(asd_ha, LmSEQ_P0M2_OFFS1AH(lseq), 0);
772
773 /* LSEQ Mode dependent, mode 4/5, page 0 setup. */
774 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_STATUS(lseq), 0);
775 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_MODE(lseq), 0);
776 asd_write_reg_word(asd_ha, LmSEQ_Q_LINK_HEAD(lseq), 0xFFFF);
777 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_ERR(lseq), 0);
778 asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_SIGNALS(lseq), 0);
779 asd_write_reg_byte(asd_ha, LmSEQ_SAS_RESET_MODE(lseq), 0);
780 asd_write_reg_byte(asd_ha, LmSEQ_LINK_RESET_RETRY_COUNT(lseq), 0);
781 asd_write_reg_byte(asd_ha, LmSEQ_NUM_LINK_RESET_RETRIES(lseq), 0);
782 asd_write_reg_word(asd_ha, LmSEQ_OOB_INT_ENABLES(lseq), 0);
783 /*
784 * Set the desired interval between transmissions of the NOTIFY
785 * (ENABLE SPINUP) primitive. Must be initialized to val - 1.
786 */
787 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_TIMEOUT(lseq),
788 ASD_NOTIFY_TIMEOUT - 1);
789 /* No delay for the first NOTIFY to be sent to the attached target. */
790 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_DOWN_COUNT(lseq),
791 ASD_NOTIFY_DOWN_COUNT);
792 asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(lseq),
793 ASD_NOTIFY_DOWN_COUNT);
794
795 /* LSEQ Mode dependent, mode 0 and 1, page 1 setup. */
796 for (i = 0; i < 2; i++) {
797 int j;
798 /* Start from Page 1 of Mode 0 and 1. */
799 moffs = LSEQ_PAGE_SIZE + i*LSEQ_MODE_SCRATCH_SIZE;
800 /* All the fields of page 1 can be initialized to 0. */
801 for (j = 0; j < LSEQ_PAGE_SIZE; j += 4)
802 asd_write_reg_dword(asd_ha, LmSCRATCH(lseq)+moffs+j,0);
803 }
804
805 /* LSEQ Mode dependent, mode 2, page 1 setup. */
806 asd_write_reg_dword(asd_ha, LmSEQ_INVALID_DWORD_COUNT(lseq), 0);
807 asd_write_reg_dword(asd_ha, LmSEQ_DISPARITY_ERROR_COUNT(lseq), 0);
808 asd_write_reg_dword(asd_ha, LmSEQ_LOSS_OF_SYNC_COUNT(lseq), 0);
809
810 /* LSEQ Mode dependent, mode 4/5, page 1. */
811 for (i = 0; i < LSEQ_PAGE_SIZE; i+=4)
812 asd_write_reg_dword(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq)+i, 0);
813 asd_write_reg_byte(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq), 0xFF);
814 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq), 0xFF);
815 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+1,0xFF);
816 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+2,0xFF);
817 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq), 0xFF);
818 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+1, 0xFF);
819 asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+2, 0xFF);
820 asd_write_reg_dword(asd_ha, LmSEQ_DATA_OFFSET(lseq), 0xFFFFFFFF);
821
822 /* LSEQ Mode dependent, mode 0, page 2 setup. */
823 asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMER_TERM_TS(lseq), 0);
824 asd_write_reg_byte(asd_ha, LmSEQ_DEVICE_BITS(lseq), 0);
825 asd_write_reg_word(asd_ha, LmSEQ_SDB_DDB(lseq), 0);
826 asd_write_reg_byte(asd_ha, LmSEQ_SDB_NUM_TAGS(lseq), 0);
827 asd_write_reg_byte(asd_ha, LmSEQ_SDB_CURR_TAG(lseq), 0);
828
829 /* LSEQ Mode Dependent 1, page 2 setup. */
830 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq), 0);
831 asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq)+4, 0);
832 asd_write_reg_dword(asd_ha, LmSEQ_OPEN_TIMER_TERM_TS(lseq), 0);
833 asd_write_reg_dword(asd_ha, LmSEQ_SRST_AS_TIMER_TERM_TS(lseq), 0);
834 asd_write_reg_dword(asd_ha, LmSEQ_LAST_LOADED_SG_EL(lseq), 0);
835
836 /* LSEQ Mode Dependent 2, page 2 setup. */
837 /* The LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS is IGNORED by the sequencer,
838 * i.e. always 0. */
839 asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(lseq),0);
840 asd_write_reg_dword(asd_ha, LmSEQ_CLOSE_TIMER_TERM_TS(lseq), 0);
841 asd_write_reg_dword(asd_ha, LmSEQ_BREAK_TIMER_TERM_TS(lseq), 0);
842 asd_write_reg_dword(asd_ha, LmSEQ_DWS_RESET_TIMER_TERM_TS(lseq), 0);
843 asd_write_reg_dword(asd_ha,LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(lseq),0);
844 asd_write_reg_dword(asd_ha, LmSEQ_MCTL_TIMER_TERM_TS(lseq), 0);
845
846 /* LSEQ Mode Dependent 4/5, page 2 setup. */
847 asd_write_reg_dword(asd_ha, LmSEQ_COMINIT_TIMER_TERM_TS(lseq), 0);
848 asd_write_reg_dword(asd_ha, LmSEQ_RCV_ID_TIMER_TERM_TS(lseq), 0);
849 asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMER_TERM_TS(lseq), 0);
850 asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TIMER_TERM_TS(lseq), 0);
851}
852
853/**
854 * asd_init_lseq_scratch -- setup and init link sequencers
855 * @asd_ha: pointer to host adapter struct
856 */
857static void asd_init_lseq_scratch(struct asd_ha_struct *asd_ha)
858{
859 u8 lseq;
860 u8 lseq_mask;
861
862 lseq_mask = asd_ha->hw_prof.enabled_phys;
863 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
864 asd_init_lseq_mip(asd_ha, lseq);
865 asd_init_lseq_mdp(asd_ha, lseq);
866 }
867}
868
869/**
870 * asd_init_scb_sites -- initialize sequencer SCB sites (memory).
871 * @asd_ha: pointer to host adapter structure
872 *
873 * This should be done before initializing common CSEQ and LSEQ
874 * scratch since those areas depend on some computed values here,
875 * last_scb_site_no, etc.
876 */
877static void asd_init_scb_sites(struct asd_ha_struct *asd_ha)
878{
879 u16 site_no;
880 u16 max_scbs = 0;
881
882 for (site_no = asd_ha->hw_prof.max_scbs-1;
883 site_no != (u16) -1;
884 site_no--) {
885 u16 i;
886
887 /* Initialize all fields in the SCB site to 0. */
888 for (i = 0; i < ASD_SCB_SIZE; i += 4)
889 asd_scbsite_write_dword(asd_ha, site_no, i, 0);
890
891 /* Initialize SCB Site Opcode field to invalid. */
892 asd_scbsite_write_byte(asd_ha, site_no,
893 offsetof(struct scb_header, opcode),
894 0xFF);
895
896 /* Initialize SCB Site Flags field to mean a response
897 * frame has been received. This means inadvertent
898 * frames received to be dropped. */
899 asd_scbsite_write_byte(asd_ha, site_no, 0x49, 0x01);
900
901 /* Workaround needed by SEQ to fix a SATA issue is to exclude
902 * certain SCB sites from the free list. */
903 if (!SCB_SITE_VALID(site_no))
904 continue;
905
906 if (last_scb_site_no == 0)
907 last_scb_site_no = site_no;
908
909 /* For every SCB site, we need to initialize the
910 * following fields: Q_NEXT, SCB_OPCODE, SCB_FLAGS,
911 * and SG Element Flag. */
912
913 /* Q_NEXT field of the last SCB is invalidated. */
914 asd_scbsite_write_word(asd_ha, site_no, 0, first_scb_site_no);
915
916 first_scb_site_no = site_no;
917 max_scbs++;
918 }
919 asd_ha->hw_prof.max_scbs = max_scbs;
920 ASD_DPRINTK("max_scbs:%d\n", asd_ha->hw_prof.max_scbs);
921 ASD_DPRINTK("first_scb_site_no:0x%x\n", first_scb_site_no);
922 ASD_DPRINTK("last_scb_site_no:0x%x\n", last_scb_site_no);
923}
924
925/**
926 * asd_init_cseq_cio - initialize CSEQ CIO registers
927 * @asd_ha: pointer to host adapter structure
928 */
929static void asd_init_cseq_cio(struct asd_ha_struct *asd_ha)
930{
931 int i;
932
933 asd_write_reg_byte(asd_ha, CSEQCOMINTEN, 0);
934 asd_write_reg_byte(asd_ha, CSEQDLCTL, ASD_DL_SIZE_BITS);
935 asd_write_reg_byte(asd_ha, CSEQDLOFFS, 0);
936 asd_write_reg_byte(asd_ha, CSEQDLOFFS+1, 0);
937 asd_ha->seq.scbpro = 0;
938 asd_write_reg_dword(asd_ha, SCBPRO, 0);
939 asd_write_reg_dword(asd_ha, CSEQCON, 0);
940
941 /* Initialize CSEQ Mode 11 Interrupt Vectors.
942 * The addresses are 16 bit wide and in dword units.
943 * The values of their macros are in byte units.
944 * Thus we have to divide by 4. */
945 asd_write_reg_word(asd_ha, CM11INTVEC0, cseq_vecs[0]);
946 asd_write_reg_word(asd_ha, CM11INTVEC1, cseq_vecs[1]);
947 asd_write_reg_word(asd_ha, CM11INTVEC2, cseq_vecs[2]);
948
949 /* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
950 asd_write_reg_byte(asd_ha, CARP2INTEN, EN_ARP2HALTC);
951
952 /* Initialize CSEQ Scratch Page to 0x04. */
953 asd_write_reg_byte(asd_ha, CSCRATCHPAGE, 0x04);
954
955 /* Initialize CSEQ Mode[0-8] Dependent registers. */
956 /* Initialize Scratch Page to 0. */
957 for (i = 0; i < 9; i++)
958 asd_write_reg_byte(asd_ha, CMnSCRATCHPAGE(i), 0);
959
960 /* Reset the ARP2 Program Count. */
961 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
962
963 for (i = 0; i < 8; i++) {
964 /* Initialize Mode n Link m Interrupt Enable. */
965 asd_write_reg_dword(asd_ha, CMnINTEN(i), EN_CMnRSPMBXF);
966 /* Initialize Mode n Request Mailbox. */
967 asd_write_reg_dword(asd_ha, CMnREQMBX(i), 0);
968 }
969}
970
971/**
972 * asd_init_lseq_cio -- initialize LmSEQ CIO registers
973 * @asd_ha: pointer to host adapter structure
974 */
975static void asd_init_lseq_cio(struct asd_ha_struct *asd_ha, int lseq)
976{
977 u8 *sas_addr;
978 int i;
979
980 /* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
981 asd_write_reg_dword(asd_ha, LmARP2INTEN(lseq), EN_ARP2HALTC);
982
983 asd_write_reg_byte(asd_ha, LmSCRATCHPAGE(lseq), 0);
984
985 /* Initialize Mode 0,1, and 2 SCRATCHPAGE to 0. */
986 for (i = 0; i < 3; i++)
987 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, i), 0);
988
989 /* Initialize Mode 5 SCRATCHPAGE to 0. */
990 asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, 5), 0);
991
992 asd_write_reg_dword(asd_ha, LmRSPMBX(lseq), 0);
993 /* Initialize Mode 0,1,2 and 5 Interrupt Enable and
994 * Interrupt registers. */
995 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 0), LmM0INTEN_MASK);
996 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 0), 0xFFFFFFFF);
997 /* Mode 1 */
998 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 1), LmM1INTEN_MASK);
999 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 1), 0xFFFFFFFF);
1000 /* Mode 2 */
1001 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 2), LmM2INTEN_MASK);
1002 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 2), 0xFFFFFFFF);
1003 /* Mode 5 */
1004 asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 5), LmM5INTEN_MASK);
1005 asd_write_reg_dword(asd_ha, LmMnINT(lseq, 5), 0xFFFFFFFF);
1006
1007 /* Enable HW Timer status. */
1008 asd_write_reg_byte(asd_ha, LmHWTSTATEN(lseq), LmHWTSTATEN_MASK);
1009
1010 /* Enable Primitive Status 0 and 1. */
1011 asd_write_reg_dword(asd_ha, LmPRIMSTAT0EN(lseq), LmPRIMSTAT0EN_MASK);
1012 asd_write_reg_dword(asd_ha, LmPRIMSTAT1EN(lseq), LmPRIMSTAT1EN_MASK);
1013
1014 /* Enable Frame Error. */
1015 asd_write_reg_dword(asd_ha, LmFRMERREN(lseq), LmFRMERREN_MASK);
1016 asd_write_reg_byte(asd_ha, LmMnHOLDLVL(lseq, 0), 0x50);
1017
1018 /* Initialize Mode 0 Transfer Level to 512. */
1019 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 0), LmMnXFRLVL_512);
1020 /* Initialize Mode 1 Transfer Level to 256. */
1021 asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 1), LmMnXFRLVL_256);
1022
1023 /* Initialize Program Count. */
1024 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1025
1026 /* Enable Blind SG Move. */
1027 asd_write_reg_dword(asd_ha, LmMODECTL(lseq), LmBLIND48);
1028 asd_write_reg_word(asd_ha, LmM3SATATIMER(lseq),
1029 ASD_SATA_INTERLOCK_TIMEOUT);
1030
1031 (void) asd_read_reg_dword(asd_ha, LmREQMBX(lseq));
1032
1033 /* Clear Primitive Status 0 and 1. */
1034 asd_write_reg_dword(asd_ha, LmPRMSTAT0(lseq), 0xFFFFFFFF);
1035 asd_write_reg_dword(asd_ha, LmPRMSTAT1(lseq), 0xFFFFFFFF);
1036
1037 /* Clear HW Timer status. */
1038 asd_write_reg_byte(asd_ha, LmHWTSTAT(lseq), 0xFF);
1039
1040 /* Clear DMA Errors for Mode 0 and 1. */
1041 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 0), 0xFF);
1042 asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 1), 0xFF);
1043
1044 /* Clear SG DMA Errors for Mode 0 and 1. */
1045 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 0), 0xFF);
1046 asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 1), 0xFF);
1047
1048 /* Clear Mode 0 Buffer Parity Error. */
1049 asd_write_reg_byte(asd_ha, LmMnBUFSTAT(lseq, 0), LmMnBUFPERR);
1050
1051 /* Clear Mode 0 Frame Error register. */
1052 asd_write_reg_dword(asd_ha, LmMnFRMERR(lseq, 0), 0xFFFFFFFF);
1053
1054 /* Reset LSEQ external interrupt arbiter. */
1055 asd_write_reg_byte(asd_ha, LmARP2INTCTL(lseq), RSTINTCTL);
1056
1057 /* Set the Phy SAS for the LmSEQ WWN. */
1058 sas_addr = asd_ha->phys[lseq].phy_desc->sas_addr;
1059 for (i = 0; i < SAS_ADDR_SIZE; i++)
1060 asd_write_reg_byte(asd_ha, LmWWN(lseq) + i, sas_addr[i]);
1061
1062 /* Set the Transmit Size to 1024 bytes, 0 = 256 Dwords. */
1063 asd_write_reg_byte(asd_ha, LmMnXMTSIZE(lseq, 1), 0);
1064
1065 /* Set the Bus Inactivity Time Limit Timer. */
1066 asd_write_reg_word(asd_ha, LmBITL_TIMER(lseq), 9);
1067
1068 /* Enable SATA Port Multiplier. */
1069 asd_write_reg_byte(asd_ha, LmMnSATAFS(lseq, 1), 0x80);
1070
1071 /* Initialize Interrupt Vector[0-10] address in Mode 3.
1072 * See the comment on CSEQ_INT_* */
1073 asd_write_reg_word(asd_ha, LmM3INTVEC0(lseq), lseq_vecs[0]);
1074 asd_write_reg_word(asd_ha, LmM3INTVEC1(lseq), lseq_vecs[1]);
1075 asd_write_reg_word(asd_ha, LmM3INTVEC2(lseq), lseq_vecs[2]);
1076 asd_write_reg_word(asd_ha, LmM3INTVEC3(lseq), lseq_vecs[3]);
1077 asd_write_reg_word(asd_ha, LmM3INTVEC4(lseq), lseq_vecs[4]);
1078 asd_write_reg_word(asd_ha, LmM3INTVEC5(lseq), lseq_vecs[5]);
1079 asd_write_reg_word(asd_ha, LmM3INTVEC6(lseq), lseq_vecs[6]);
1080 asd_write_reg_word(asd_ha, LmM3INTVEC7(lseq), lseq_vecs[7]);
1081 asd_write_reg_word(asd_ha, LmM3INTVEC8(lseq), lseq_vecs[8]);
1082 asd_write_reg_word(asd_ha, LmM3INTVEC9(lseq), lseq_vecs[9]);
1083 asd_write_reg_word(asd_ha, LmM3INTVEC10(lseq), lseq_vecs[10]);
1084 /*
1085 * Program the Link LED control, applicable only for
1086 * Chip Rev. B or later.
1087 */
1088 asd_write_reg_dword(asd_ha, LmCONTROL(lseq),
1089 (LEDTIMER | LEDMODE_TXRX | LEDTIMERS_100ms));
1090
1091 /* Set the Align Rate for SAS and STP mode. */
1092 asd_write_reg_byte(asd_ha, LmM1SASALIGN(lseq), SAS_ALIGN_DEFAULT);
1093 asd_write_reg_byte(asd_ha, LmM1STPALIGN(lseq), STP_ALIGN_DEFAULT);
1094}
1095
1096
1097/**
1098 * asd_post_init_cseq -- clear CSEQ Mode n Int. status and Response mailbox
1099 * @asd_ha: pointer to host adapter struct
1100 */
1101static void asd_post_init_cseq(struct asd_ha_struct *asd_ha)
1102{
1103 int i;
1104
1105 for (i = 0; i < 8; i++)
1106 asd_write_reg_dword(asd_ha, CMnINT(i), 0xFFFFFFFF);
1107 for (i = 0; i < 8; i++)
1108 asd_read_reg_dword(asd_ha, CMnRSPMBX(i));
1109 /* Reset the external interrupt arbiter. */
1110 asd_write_reg_byte(asd_ha, CARP2INTCTL, RSTINTCTL);
1111}
1112
1113/**
1114 * asd_init_ddb_0 -- initialize DDB 0
1115 * @asd_ha: pointer to host adapter structure
1116 *
1117 * Initialize DDB site 0 which is used internally by the sequencer.
1118 */
1119static void asd_init_ddb_0(struct asd_ha_struct *asd_ha)
1120{
1121 int i;
1122
1123 /* Zero out the DDB explicitly */
1124 for (i = 0; i < sizeof(struct asd_ddb_seq_shared); i+=4)
1125 asd_ddbsite_write_dword(asd_ha, 0, i, 0);
1126
1127 asd_ddbsite_write_word(asd_ha, 0,
1128 offsetof(struct asd_ddb_seq_shared, q_free_ddb_head), 0);
1129 asd_ddbsite_write_word(asd_ha, 0,
1130 offsetof(struct asd_ddb_seq_shared, q_free_ddb_tail),
1131 asd_ha->hw_prof.max_ddbs-1);
1132 asd_ddbsite_write_word(asd_ha, 0,
1133 offsetof(struct asd_ddb_seq_shared, q_free_ddb_cnt), 0);
1134 asd_ddbsite_write_word(asd_ha, 0,
1135 offsetof(struct asd_ddb_seq_shared, q_used_ddb_head), 0xFFFF);
1136 asd_ddbsite_write_word(asd_ha, 0,
1137 offsetof(struct asd_ddb_seq_shared, q_used_ddb_tail), 0xFFFF);
1138 asd_ddbsite_write_word(asd_ha, 0,
1139 offsetof(struct asd_ddb_seq_shared, shared_mem_lock), 0);
1140 asd_ddbsite_write_word(asd_ha, 0,
1141 offsetof(struct asd_ddb_seq_shared, smp_conn_tag), 0);
1142 asd_ddbsite_write_word(asd_ha, 0,
1143 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_cnt), 0);
1144 asd_ddbsite_write_word(asd_ha, 0,
1145 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_thresh),
1146 asd_ha->hw_prof.num_phys * 2);
1147 asd_ddbsite_write_byte(asd_ha, 0,
1148 offsetof(struct asd_ddb_seq_shared, settable_max_contexts),0);
1149 asd_ddbsite_write_byte(asd_ha, 0,
1150 offsetof(struct asd_ddb_seq_shared, conn_not_active), 0xFF);
1151 asd_ddbsite_write_byte(asd_ha, 0,
1152 offsetof(struct asd_ddb_seq_shared, phy_is_up), 0x00);
1153 /* DDB 0 is reserved */
1154 set_bit(0, asd_ha->hw_prof.ddb_bitmap);
1155}
1156
1157static void asd_seq_init_ddb_sites(struct asd_ha_struct *asd_ha)
1158{
1159 unsigned int i;
1160 unsigned int ddb_site;
1161
1162 for (ddb_site = 0 ; ddb_site < ASD_MAX_DDBS; ddb_site++)
1163 for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4)
1164 asd_ddbsite_write_dword(asd_ha, ddb_site, i, 0);
1165}
1166
1167/**
1168 * asd_seq_setup_seqs -- setup and initialize central and link sequencers
1169 * @asd_ha: pointer to host adapter structure
1170 */
1171static void asd_seq_setup_seqs(struct asd_ha_struct *asd_ha)
1172{
1173 int lseq;
1174 u8 lseq_mask;
1175
1176 /* Initialize DDB sites */
1177 asd_seq_init_ddb_sites(asd_ha);
1178
1179 /* Initialize SCB sites. Done first to compute some values which
1180 * the rest of the init code depends on. */
1181 asd_init_scb_sites(asd_ha);
1182
1183 /* Initialize CSEQ Scratch RAM registers. */
1184 asd_init_cseq_scratch(asd_ha);
1185
1186 /* Initialize LmSEQ Scratch RAM registers. */
1187 asd_init_lseq_scratch(asd_ha);
1188
1189 /* Initialize CSEQ CIO registers. */
1190 asd_init_cseq_cio(asd_ha);
1191
1192 asd_init_ddb_0(asd_ha);
1193
1194 /* Initialize LmSEQ CIO registers. */
1195 lseq_mask = asd_ha->hw_prof.enabled_phys;
1196 for_each_sequencer(lseq_mask, lseq_mask, lseq)
1197 asd_init_lseq_cio(asd_ha, lseq);
1198 asd_post_init_cseq(asd_ha);
1199}
1200
1201
1202/**
1203 * asd_seq_start_cseq -- start the central sequencer, CSEQ
1204 * @asd_ha: pointer to host adapter structure
1205 */
1206static int asd_seq_start_cseq(struct asd_ha_struct *asd_ha)
1207{
1208 /* Reset the ARP2 instruction to location zero. */
1209 asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
1210
1211 /* Unpause the CSEQ */
1212 return asd_unpause_cseq(asd_ha);
1213}
1214
1215/**
1216 * asd_seq_start_lseq -- start a link sequencer
1217 * @asd_ha: pointer to host adapter structure
1218 * @lseq: the link sequencer of interest
1219 */
1220static int asd_seq_start_lseq(struct asd_ha_struct *asd_ha, int lseq)
1221{
1222 /* Reset the ARP2 instruction to location zero. */
1223 asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1224
1225 /* Unpause the LmSEQ */
1226 return asd_seq_unpause_lseq(asd_ha, lseq);
1227}
1228
1229int asd_release_firmware(void)
1230{
1231 if (sequencer_fw)
1232 release_firmware(sequencer_fw);
1233 return 0;
1234}
1235
1236static int asd_request_firmware(struct asd_ha_struct *asd_ha)
1237{
1238 int err, i;
1239 struct sequencer_file_header header;
1240 const struct sequencer_file_header *hdr_ptr;
1241 u32 csum = 0;
1242 u16 *ptr_cseq_vecs, *ptr_lseq_vecs;
1243
1244 if (sequencer_fw)
1245 /* already loaded */
1246 return 0;
1247
1248 err = request_firmware(&sequencer_fw,
1249 SAS_RAZOR_SEQUENCER_FW_FILE,
1250 &asd_ha->pcidev->dev);
1251 if (err)
1252 return err;
1253
1254 hdr_ptr = (const struct sequencer_file_header *)sequencer_fw->data;
1255
1256 header.csum = le32_to_cpu(hdr_ptr->csum);
1257 header.major = le32_to_cpu(hdr_ptr->major);
1258 header.minor = le32_to_cpu(hdr_ptr->minor);
1259 header.cseq_table_offset = le32_to_cpu(hdr_ptr->cseq_table_offset);
1260 header.cseq_table_size = le32_to_cpu(hdr_ptr->cseq_table_size);
1261 header.lseq_table_offset = le32_to_cpu(hdr_ptr->lseq_table_offset);
1262 header.lseq_table_size = le32_to_cpu(hdr_ptr->lseq_table_size);
1263 header.cseq_code_offset = le32_to_cpu(hdr_ptr->cseq_code_offset);
1264 header.cseq_code_size = le32_to_cpu(hdr_ptr->cseq_code_size);
1265 header.lseq_code_offset = le32_to_cpu(hdr_ptr->lseq_code_offset);
1266 header.lseq_code_size = le32_to_cpu(hdr_ptr->lseq_code_size);
1267 header.mode2_task = le16_to_cpu(hdr_ptr->mode2_task);
1268 header.cseq_idle_loop = le16_to_cpu(hdr_ptr->cseq_idle_loop);
1269 header.lseq_idle_loop = le16_to_cpu(hdr_ptr->lseq_idle_loop);
1270
1271 for (i = sizeof(header.csum); i < sequencer_fw->size; i++)
1272 csum += sequencer_fw->data[i];
1273
1274 if (csum != header.csum) {
1275 asd_printk("Firmware file checksum mismatch\n");
1276 return -EINVAL;
1277 }
1278
1279 if (header.cseq_table_size != CSEQ_NUM_VECS ||
1280 header.lseq_table_size != LSEQ_NUM_VECS) {
1281 asd_printk("Firmware file table size mismatch\n");
1282 return -EINVAL;
1283 }
1284
1285 asd_printk("Found sequencer Firmware version %d.%d (%s)\n",
1286 header.major, header.minor, hdr_ptr->version);
1287
1288 if (header.major != SAS_RAZOR_SEQUENCER_FW_MAJOR) {
1289 asd_printk("Firmware Major Version Mismatch;"
1290 "driver requires version %d.X",
1291 SAS_RAZOR_SEQUENCER_FW_MAJOR);
1292 return -EINVAL;
1293 }
1294
1295 ptr_cseq_vecs = (u16 *)&sequencer_fw->data[header.cseq_table_offset];
1296 ptr_lseq_vecs = (u16 *)&sequencer_fw->data[header.lseq_table_offset];
1297 mode2_task = header.mode2_task;
1298 cseq_idle_loop = header.cseq_idle_loop;
1299 lseq_idle_loop = header.lseq_idle_loop;
1300
1301 for (i = 0; i < CSEQ_NUM_VECS; i++)
1302 cseq_vecs[i] = le16_to_cpu(ptr_cseq_vecs[i]);
1303
1304 for (i = 0; i < LSEQ_NUM_VECS; i++)
1305 lseq_vecs[i] = le16_to_cpu(ptr_lseq_vecs[i]);
1306
1307 cseq_code = &sequencer_fw->data[header.cseq_code_offset];
1308 cseq_code_size = header.cseq_code_size;
1309 lseq_code = &sequencer_fw->data[header.lseq_code_offset];
1310 lseq_code_size = header.lseq_code_size;
1311
1312 return 0;
1313}
1314
1315int asd_init_seqs(struct asd_ha_struct *asd_ha)
1316{
1317 int err;
1318
1319 err = asd_request_firmware(asd_ha);
1320
1321 if (err) {
1322 asd_printk("Failed to load sequencer firmware file %s, error %d\n",
1323 SAS_RAZOR_SEQUENCER_FW_FILE, err);
1324 return err;
1325 }
1326
1327 err = asd_seq_download_seqs(asd_ha);
1328 if (err) {
1329 asd_printk("couldn't download sequencers for %s\n",
1330 pci_name(asd_ha->pcidev));
1331 return err;
1332 }
1333
1334 asd_seq_setup_seqs(asd_ha);
1335
1336 return 0;
1337}
1338
1339int asd_start_seqs(struct asd_ha_struct *asd_ha)
1340{
1341 int err;
1342 u8 lseq_mask;
1343 int lseq;
1344
1345 err = asd_seq_start_cseq(asd_ha);
1346 if (err) {
1347 asd_printk("couldn't start CSEQ for %s\n",
1348 pci_name(asd_ha->pcidev));
1349 return err;
1350 }
1351
1352 lseq_mask = asd_ha->hw_prof.enabled_phys;
1353 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
1354 err = asd_seq_start_lseq(asd_ha, lseq);
1355 if (err) {
1356 asd_printk("coudln't start LSEQ %d for %s\n", lseq,
1357 pci_name(asd_ha->pcidev));
1358 return err;
1359 }
1360 }
1361
1362 return 0;
1363}
1364
1365/**
1366 * asd_update_port_links -- update port_map_by_links and phy_is_up
1367 * @sas_phy: pointer to the phy which has been added to a port
1368 *
1369 * 1) When a link reset has completed and we got BYTES DMAED with a
1370 * valid frame we call this function for that phy, to indicate that
1371 * the phy is up, i.e. we update the phy_is_up in DDB 0. The
1372 * sequencer checks phy_is_up when pending SCBs are to be sent, and
1373 * when an open address frame has been received.
1374 *
1375 * 2) When we know of ports, we call this function to update the map
1376 * of phys participaing in that port, i.e. we update the
1377 * port_map_by_links in DDB 0. When a HARD_RESET primitive has been
1378 * received, the sequencer disables all phys in that port.
1379 * port_map_by_links is also used as the conn_mask byte in the
1380 * initiator/target port DDB.
1381 */
1382void asd_update_port_links(struct asd_ha_struct *asd_ha, struct asd_phy *phy)
1383{
1384 const u8 phy_mask = (u8) phy->asd_port->phy_mask;
1385 u8 phy_is_up;
1386 u8 mask;
1387 int i, err;
1388 unsigned long flags;
1389
1390 spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
1391 for_each_phy(phy_mask, mask, i)
1392 asd_ddbsite_write_byte(asd_ha, 0,
1393 offsetof(struct asd_ddb_seq_shared,
1394 port_map_by_links)+i,phy_mask);
1395
1396 for (i = 0; i < 12; i++) {
1397 phy_is_up = asd_ddbsite_read_byte(asd_ha, 0,
1398 offsetof(struct asd_ddb_seq_shared, phy_is_up));
1399 err = asd_ddbsite_update_byte(asd_ha, 0,
1400 offsetof(struct asd_ddb_seq_shared, phy_is_up),
1401 phy_is_up,
1402 phy_is_up | phy_mask);
1403 if (!err)
1404 break;
1405 else if (err == -EFAULT) {
1406 asd_printk("phy_is_up: parity error in DDB 0\n");
1407 break;
1408 }
1409 }
1410 spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
1411
1412 if (err)
1413 asd_printk("couldn't update DDB 0:error:%d\n", err);
1414}
1415
1416MODULE_FIRMWARE(SAS_RAZOR_SEQUENCER_FW_FILE);