Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale FlexTimer Module (FTM) PWM Driver
4 *
5 * Copyright 2012-2013 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/mutex.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm.h>
17#include <linux/pwm.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/fsl/ftm.h>
21
22#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
23
24enum fsl_pwm_clk {
25 FSL_PWM_CLK_SYS,
26 FSL_PWM_CLK_FIX,
27 FSL_PWM_CLK_EXT,
28 FSL_PWM_CLK_CNTEN,
29 FSL_PWM_CLK_MAX
30};
31
32struct fsl_ftm_soc {
33 bool has_enable_bits;
34};
35
36struct fsl_pwm_periodcfg {
37 enum fsl_pwm_clk clk_select;
38 unsigned int clk_ps;
39 unsigned int mod_period;
40};
41
42struct fsl_pwm_chip {
43 struct pwm_chip chip;
44 struct mutex lock;
45 struct regmap *regmap;
46
47 /* This value is valid iff a pwm is running */
48 struct fsl_pwm_periodcfg period;
49
50 struct clk *ipg_clk;
51 struct clk *clk[FSL_PWM_CLK_MAX];
52
53 const struct fsl_ftm_soc *soc;
54};
55
56static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
57{
58 return container_of(chip, struct fsl_pwm_chip, chip);
59}
60
61static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
62{
63 u32 val;
64
65 regmap_read(fpc->regmap, FTM_FMS, &val);
66 if (val & FTM_FMS_WPEN)
67 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
68}
69
70static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
71{
72 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
73}
74
75static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
76 const struct fsl_pwm_periodcfg *b)
77{
78 if (a->clk_select != b->clk_select)
79 return false;
80 if (a->clk_ps != b->clk_ps)
81 return false;
82 if (a->mod_period != b->mod_period)
83 return false;
84 return true;
85}
86
87static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
88{
89 int ret;
90 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
91
92 ret = clk_prepare_enable(fpc->ipg_clk);
93 if (!ret && fpc->soc->has_enable_bits) {
94 mutex_lock(&fpc->lock);
95 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
96 mutex_unlock(&fpc->lock);
97 }
98
99 return ret;
100}
101
102static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
103{
104 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
105
106 if (fpc->soc->has_enable_bits) {
107 mutex_lock(&fpc->lock);
108 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
109 mutex_unlock(&fpc->lock);
110 }
111
112 clk_disable_unprepare(fpc->ipg_clk);
113}
114
115static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
116 unsigned int ticks)
117{
118 unsigned long rate;
119 unsigned long long exval;
120
121 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
122 exval = ticks;
123 exval *= 1000000000UL;
124 do_div(exval, rate >> fpc->period.clk_ps);
125 return exval;
126}
127
128static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
129 unsigned int period_ns,
130 enum fsl_pwm_clk index,
131 struct fsl_pwm_periodcfg *periodcfg
132 )
133{
134 unsigned long long c;
135 unsigned int ps;
136
137 c = clk_get_rate(fpc->clk[index]);
138 c = c * period_ns;
139 do_div(c, 1000000000UL);
140
141 if (c == 0)
142 return false;
143
144 for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
145 if (c <= 0x10000) {
146 periodcfg->clk_select = index;
147 periodcfg->clk_ps = ps;
148 periodcfg->mod_period = c - 1;
149 return true;
150 }
151 }
152 return false;
153}
154
155static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
156 unsigned int period_ns,
157 struct fsl_pwm_periodcfg *periodcfg)
158{
159 enum fsl_pwm_clk m0, m1;
160 unsigned long fix_rate, ext_rate;
161 bool ret;
162
163 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
164 periodcfg);
165 if (ret)
166 return true;
167
168 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
169 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
170
171 if (fix_rate > ext_rate) {
172 m0 = FSL_PWM_CLK_FIX;
173 m1 = FSL_PWM_CLK_EXT;
174 } else {
175 m0 = FSL_PWM_CLK_EXT;
176 m1 = FSL_PWM_CLK_FIX;
177 }
178
179 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
180 if (ret)
181 return true;
182
183 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
184}
185
186static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
187 unsigned int duty_ns)
188{
189 unsigned long long duty;
190
191 unsigned int period = fpc->period.mod_period + 1;
192 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
193
194 duty = (unsigned long long)duty_ns * period;
195 do_div(duty, period_ns);
196
197 return (unsigned int)duty;
198}
199
200static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
201 struct pwm_device *pwm)
202{
203 u32 val;
204
205 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
206 if (~val & 0xFF)
207 return true;
208 else
209 return false;
210}
211
212static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
213 struct pwm_device *pwm)
214{
215 u32 val;
216
217 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
218 if (~(val | BIT(pwm->hwpwm)) & 0xFF)
219 return true;
220 else
221 return false;
222}
223
224static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
225 struct pwm_device *pwm,
226 const struct pwm_state *newstate)
227{
228 unsigned int duty;
229 u32 reg_polarity;
230
231 struct fsl_pwm_periodcfg periodcfg;
232 bool do_write_period = false;
233
234 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
235 dev_err(fpc->chip.dev, "failed to calculate new period\n");
236 return -EINVAL;
237 }
238
239 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
240 do_write_period = true;
241 /*
242 * The Freescale FTM controller supports only a single period for
243 * all PWM channels, therefore verify if the newly computed period
244 * is different than the current period being used. In such case
245 * we allow to change the period only if no other pwm is running.
246 */
247 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
248 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
249 dev_err(fpc->chip.dev,
250 "Cannot change period for PWM %u, disable other PWMs first\n",
251 pwm->hwpwm);
252 return -EBUSY;
253 }
254 if (fpc->period.clk_select != periodcfg.clk_select) {
255 int ret;
256 enum fsl_pwm_clk oldclk = fpc->period.clk_select;
257 enum fsl_pwm_clk newclk = periodcfg.clk_select;
258
259 ret = clk_prepare_enable(fpc->clk[newclk]);
260 if (ret)
261 return ret;
262 clk_disable_unprepare(fpc->clk[oldclk]);
263 }
264 do_write_period = true;
265 }
266
267 ftm_clear_write_protection(fpc);
268
269 if (do_write_period) {
270 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
271 FTM_SC_CLK(periodcfg.clk_select));
272 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
273 periodcfg.clk_ps);
274 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
275
276 fpc->period = periodcfg;
277 }
278
279 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
280
281 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
282 FTM_CSC_MSB | FTM_CSC_ELSB);
283 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
284
285 reg_polarity = 0;
286 if (newstate->polarity == PWM_POLARITY_INVERSED)
287 reg_polarity = BIT(pwm->hwpwm);
288
289 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
290
291 ftm_set_write_protection(fpc);
292
293 return 0;
294}
295
296static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
297 const struct pwm_state *newstate)
298{
299 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
300 struct pwm_state *oldstate = &pwm->state;
301 int ret = 0;
302
303 /*
304 * oldstate to newstate : action
305 *
306 * disabled to disabled : ignore
307 * enabled to disabled : disable
308 * enabled to enabled : update settings
309 * disabled to enabled : update settings + enable
310 */
311
312 mutex_lock(&fpc->lock);
313
314 if (!newstate->enabled) {
315 if (oldstate->enabled) {
316 regmap_set_bits(fpc->regmap, FTM_OUTMASK,
317 BIT(pwm->hwpwm));
318 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
319 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
320 }
321
322 goto end_mutex;
323 }
324
325 ret = fsl_pwm_apply_config(fpc, pwm, newstate);
326 if (ret)
327 goto end_mutex;
328
329 /* check if need to enable */
330 if (!oldstate->enabled) {
331 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
332 if (ret)
333 goto end_mutex;
334
335 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
336 if (ret) {
337 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
338 goto end_mutex;
339 }
340
341 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
342 }
343
344end_mutex:
345 mutex_unlock(&fpc->lock);
346 return ret;
347}
348
349static const struct pwm_ops fsl_pwm_ops = {
350 .request = fsl_pwm_request,
351 .free = fsl_pwm_free,
352 .apply = fsl_pwm_apply,
353};
354
355static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
356{
357 int ret;
358
359 ret = clk_prepare_enable(fpc->ipg_clk);
360 if (ret)
361 return ret;
362
363 regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
364 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
365 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
366
367 clk_disable_unprepare(fpc->ipg_clk);
368
369 return 0;
370}
371
372static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
373{
374 switch (reg) {
375 case FTM_FMS:
376 case FTM_MODE:
377 case FTM_CNT:
378 return true;
379 }
380 return false;
381}
382
383static const struct regmap_config fsl_pwm_regmap_config = {
384 .reg_bits = 32,
385 .reg_stride = 4,
386 .val_bits = 32,
387
388 .max_register = FTM_PWMLOAD,
389 .volatile_reg = fsl_pwm_volatile_reg,
390 .cache_type = REGCACHE_FLAT,
391};
392
393static int fsl_pwm_probe(struct platform_device *pdev)
394{
395 struct fsl_pwm_chip *fpc;
396 void __iomem *base;
397 int ret;
398
399 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
400 if (!fpc)
401 return -ENOMEM;
402
403 mutex_init(&fpc->lock);
404
405 fpc->soc = of_device_get_match_data(&pdev->dev);
406 fpc->chip.dev = &pdev->dev;
407
408 base = devm_platform_ioremap_resource(pdev, 0);
409 if (IS_ERR(base))
410 return PTR_ERR(base);
411
412 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
413 &fsl_pwm_regmap_config);
414 if (IS_ERR(fpc->regmap)) {
415 dev_err(&pdev->dev, "regmap init failed\n");
416 return PTR_ERR(fpc->regmap);
417 }
418
419 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
420 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
421 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
422 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
423 }
424
425 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
426 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
427 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
428
429 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
430 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
431 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
432
433 fpc->clk[FSL_PWM_CLK_CNTEN] =
434 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
435 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
436 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
437
438 /*
439 * ipg_clk is the interface clock for the IP. If not provided, use the
440 * ftm_sys clock as the default.
441 */
442 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
443 if (IS_ERR(fpc->ipg_clk))
444 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
445
446
447 fpc->chip.ops = &fsl_pwm_ops;
448 fpc->chip.npwm = 8;
449
450 ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
451 if (ret < 0) {
452 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
453 return ret;
454 }
455
456 platform_set_drvdata(pdev, fpc);
457
458 return fsl_pwm_init(fpc);
459}
460
461#ifdef CONFIG_PM_SLEEP
462static int fsl_pwm_suspend(struct device *dev)
463{
464 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
465 int i;
466
467 regcache_cache_only(fpc->regmap, true);
468 regcache_mark_dirty(fpc->regmap);
469
470 for (i = 0; i < fpc->chip.npwm; i++) {
471 struct pwm_device *pwm = &fpc->chip.pwms[i];
472
473 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
474 continue;
475
476 clk_disable_unprepare(fpc->ipg_clk);
477
478 if (!pwm_is_enabled(pwm))
479 continue;
480
481 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
482 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
483 }
484
485 return 0;
486}
487
488static int fsl_pwm_resume(struct device *dev)
489{
490 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
491 int i;
492
493 for (i = 0; i < fpc->chip.npwm; i++) {
494 struct pwm_device *pwm = &fpc->chip.pwms[i];
495
496 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
497 continue;
498
499 clk_prepare_enable(fpc->ipg_clk);
500
501 if (!pwm_is_enabled(pwm))
502 continue;
503
504 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
505 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
506 }
507
508 /* restore all registers from cache */
509 regcache_cache_only(fpc->regmap, false);
510 regcache_sync(fpc->regmap);
511
512 return 0;
513}
514#endif
515
516static const struct dev_pm_ops fsl_pwm_pm_ops = {
517 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
518};
519
520static const struct fsl_ftm_soc vf610_ftm_pwm = {
521 .has_enable_bits = false,
522};
523
524static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
525 .has_enable_bits = true,
526};
527
528static const struct of_device_id fsl_pwm_dt_ids[] = {
529 { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
530 { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
531 { /* sentinel */ }
532};
533MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
534
535static struct platform_driver fsl_pwm_driver = {
536 .driver = {
537 .name = "fsl-ftm-pwm",
538 .of_match_table = fsl_pwm_dt_ids,
539 .pm = &fsl_pwm_pm_ops,
540 },
541 .probe = fsl_pwm_probe,
542};
543module_platform_driver(fsl_pwm_driver);
544
545MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
546MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
547MODULE_ALIAS("platform:fsl-ftm-pwm");
548MODULE_LICENSE("GPL");