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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (C) 2016-2020 Arm Limited
3// CMN-600 Coherent Mesh Network PMU driver
4
5#include <linux/acpi.h>
6#include <linux/bitfield.h>
7#include <linux/bitops.h>
8#include <linux/debugfs.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/io-64-nonatomic-lo-hi.h>
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/perf_event.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/sort.h>
20
21/* Common register stuff */
22#define CMN_NODE_INFO 0x0000
23#define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)
24#define CMN_NI_NODE_ID GENMASK_ULL(31, 16)
25#define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)
26
27#define CMN_NODEID_DEVID(reg) ((reg) & 3)
28#define CMN_NODEID_EXT_DEVID(reg) ((reg) & 1)
29#define CMN_NODEID_PID(reg) (((reg) >> 2) & 1)
30#define CMN_NODEID_EXT_PID(reg) (((reg) >> 1) & 3)
31#define CMN_NODEID_1x1_PID(reg) (((reg) >> 2) & 7)
32#define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits)))
33#define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1))
34
35#define CMN_CHILD_INFO 0x0080
36#define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)
37#define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)
38
39#define CMN_CHILD_NODE_ADDR GENMASK(29, 0)
40#define CMN_CHILD_NODE_EXTERNAL BIT(31)
41
42#define CMN_MAX_DIMENSION 12
43#define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
44#define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
45
46/* The CFG node has various info besides the discovery tree */
47#define CMN_CFGM_PERIPH_ID_01 0x0008
48#define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0)
49#define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32)
50#define CMN_CFGM_PERIPH_ID_23 0x0010
51#define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4)
52
53#define CMN_CFGM_INFO_GLOBAL 0x900
54#define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63)
55#define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52)
56#define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50)
57
58#define CMN_CFGM_INFO_GLOBAL_1 0x908
59#define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2)
60#define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0)
61
62/* XPs also have some local topology info which has uses too */
63#define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p))
64#define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(4, 0)
65
66#define CMN_MAX_PORTS 6
67#define CI700_CONNECT_INFO_P2_5_OFFSET 0x10
68
69/* PMU registers occupy the 3rd 4KB page of each node's region */
70#define CMN_PMU_OFFSET 0x2000
71
72/* For most nodes, this is all there is */
73#define CMN_PMU_EVENT_SEL 0x000
74#define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42)
75#define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39)
76#define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37)
77#define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35)
78/* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
79#define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32)
80
81/* HN-Ps are weird... */
82#define CMN_HNP_PMU_EVENT_SEL 0x008
83
84/* DTMs live in the PMU space of XP registers */
85#define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
86#define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
87#define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19)
88#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17)
89#define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9)
90#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
91#define CMN600_WPn_CONFIG_WP_COMBINE BIT(6)
92#define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
93#define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4)
94#define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
95#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
96#define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
97#define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10)
98
99#define CMN_DTM_PMU_CONFIG 0x210
100#define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)
101#define CMN__PMEVCNT0_INPUT_SEL_WP 0x00
102#define CMN__PMEVCNT0_INPUT_SEL_XP 0x04
103#define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10
104#define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)
105#define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4)
106#define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))
107#define CMN__PMEVCNT23_COMBINED BIT(2)
108#define CMN__PMEVCNT01_COMBINED BIT(1)
109#define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0)
110
111#define CMN_DTM_PMEVCNT 0x220
112
113#define CMN_DTM_PMEVCNTSR 0x240
114
115#define CMN650_DTM_UNIT_INFO 0x0910
116#define CMN_DTM_UNIT_INFO 0x0960
117#define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0)
118
119#define CMN_DTM_NUM_COUNTERS 4
120/* Want more local counters? Why not replicate the whole DTM! Ugh... */
121#define CMN_DTM_OFFSET(n) ((n) * 0x200)
122
123/* The DTC node is where the magic happens */
124#define CMN_DT_DTC_CTL 0x0a00
125#define CMN_DT_DTC_CTL_DT_EN BIT(0)
126
127/* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
128#define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4)
129#define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
130#define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40)
131
132#define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
133#define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90)
134
135#define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100)
136#define CMN_DT_PMCR_PMU_EN BIT(0)
137#define CMN_DT_PMCR_CNTR_RST BIT(5)
138#define CMN_DT_PMCR_OVFL_INTR_EN BIT(6)
139
140#define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118)
141#define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120)
142
143#define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128)
144#define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)
145
146#define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130)
147#define CMN_DT_PMSRR_SS_REQ BIT(0)
148
149#define CMN_DT_NUM_COUNTERS 8
150#define CMN_MAX_DTCS 4
151
152/*
153 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
154 * so throwing away one bit to make overflow handling easy is no big deal.
155 */
156#define CMN_COUNTER_INIT 0x80000000
157/* Similarly for the 40-bit cycle counter */
158#define CMN_CC_INIT 0x8000000000ULL
159
160
161/* Event attributes */
162#define CMN_CONFIG_TYPE GENMASK_ULL(15, 0)
163#define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16)
164#define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27)
165#define CMN_CONFIG_BYNODEID BIT_ULL(31)
166#define CMN_CONFIG_NODEID GENMASK_ULL(47, 32)
167
168#define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
169#define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
170#define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
171#define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
172#define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
173
174#define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27)
175#define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48)
176#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51)
177/* Note that we don't yet support the tertiary match group on newer IPs */
178#define CMN_CONFIG_WP_GRP BIT_ULL(56)
179#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57)
180#define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0)
181#define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0)
182
183#define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
184#define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
185#define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
186#define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
187#define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
188#define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
189#define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
190
191/* Made-up event IDs for watchpoint direction */
192#define CMN_WP_UP 0
193#define CMN_WP_DOWN 2
194
195
196/* Internal values for encoding event support */
197enum cmn_model {
198 CMN600 = 1,
199 CMN650 = 2,
200 CMN700 = 4,
201 CI700 = 8,
202 /* ...and then we can use bitmap tricks for commonality */
203 CMN_ANY = -1,
204 NOT_CMN600 = -2,
205 CMN_650ON = CMN650 | CMN700,
206};
207
208/* Actual part numbers and revision IDs defined by the hardware */
209enum cmn_part {
210 PART_CMN600 = 0x434,
211 PART_CMN650 = 0x436,
212 PART_CMN700 = 0x43c,
213 PART_CI700 = 0x43a,
214};
215
216/* CMN-600 r0px shouldn't exist in silicon, thankfully */
217enum cmn_revision {
218 REV_CMN600_R1P0,
219 REV_CMN600_R1P1,
220 REV_CMN600_R1P2,
221 REV_CMN600_R1P3,
222 REV_CMN600_R2P0,
223 REV_CMN600_R3P0,
224 REV_CMN600_R3P1,
225 REV_CMN650_R0P0 = 0,
226 REV_CMN650_R1P0,
227 REV_CMN650_R1P1,
228 REV_CMN650_R2P0,
229 REV_CMN650_R1P2,
230 REV_CMN700_R0P0 = 0,
231 REV_CMN700_R1P0,
232 REV_CMN700_R2P0,
233 REV_CMN700_R3P0,
234 REV_CI700_R0P0 = 0,
235 REV_CI700_R1P0,
236 REV_CI700_R2P0,
237};
238
239enum cmn_node_type {
240 CMN_TYPE_INVALID,
241 CMN_TYPE_DVM,
242 CMN_TYPE_CFG,
243 CMN_TYPE_DTC,
244 CMN_TYPE_HNI,
245 CMN_TYPE_HNF,
246 CMN_TYPE_XP,
247 CMN_TYPE_SBSX,
248 CMN_TYPE_MPAM_S,
249 CMN_TYPE_MPAM_NS,
250 CMN_TYPE_RNI,
251 CMN_TYPE_RND = 0xd,
252 CMN_TYPE_RNSAM = 0xf,
253 CMN_TYPE_MTSX,
254 CMN_TYPE_HNP,
255 CMN_TYPE_CXRA = 0x100,
256 CMN_TYPE_CXHA,
257 CMN_TYPE_CXLA,
258 CMN_TYPE_CCRA,
259 CMN_TYPE_CCHA,
260 CMN_TYPE_CCLA,
261 CMN_TYPE_CCLA_RNI,
262 CMN_TYPE_HNS = 0x200,
263 CMN_TYPE_HNS_MPAM_S,
264 CMN_TYPE_HNS_MPAM_NS,
265 /* Not a real node type */
266 CMN_TYPE_WP = 0x7770
267};
268
269enum cmn_filter_select {
270 SEL_NONE = -1,
271 SEL_OCCUP1ID,
272 SEL_CLASS_OCCUP_ID,
273 SEL_CBUSY_SNTHROTTLE_SEL,
274 SEL_HBT_LBT_SEL,
275 SEL_SN_HOME_SEL,
276 SEL_MAX
277};
278
279struct arm_cmn_node {
280 void __iomem *pmu_base;
281 u16 id, logid;
282 enum cmn_node_type type;
283
284 u8 dtm;
285 s8 dtc;
286 /* DN/HN-F/CXHA */
287 struct {
288 u8 val : 4;
289 u8 count : 4;
290 } occupid[SEL_MAX];
291 union {
292 u8 event[4];
293 __le32 event_sel;
294 u16 event_w[4];
295 __le64 event_sel_w;
296 };
297};
298
299struct arm_cmn_dtm {
300 void __iomem *base;
301 u32 pmu_config_low;
302 union {
303 u8 input_sel[4];
304 __le32 pmu_config_high;
305 };
306 s8 wp_event[4];
307};
308
309struct arm_cmn_dtc {
310 void __iomem *base;
311 int irq;
312 int irq_friend;
313 bool cc_active;
314
315 struct perf_event *counters[CMN_DT_NUM_COUNTERS];
316 struct perf_event *cycles;
317};
318
319#define CMN_STATE_DISABLED BIT(0)
320#define CMN_STATE_TXN BIT(1)
321
322struct arm_cmn {
323 struct device *dev;
324 void __iomem *base;
325 unsigned int state;
326
327 enum cmn_revision rev;
328 enum cmn_part part;
329 u8 mesh_x;
330 u8 mesh_y;
331 u16 num_xps;
332 u16 num_dns;
333 bool multi_dtm;
334 u8 ports_used;
335 struct {
336 unsigned int rsp_vc_num : 2;
337 unsigned int dat_vc_num : 2;
338 unsigned int snp_vc_num : 2;
339 unsigned int req_vc_num : 2;
340 };
341
342 struct arm_cmn_node *xps;
343 struct arm_cmn_node *dns;
344
345 struct arm_cmn_dtm *dtms;
346 struct arm_cmn_dtc *dtc;
347 unsigned int num_dtcs;
348
349 int cpu;
350 struct hlist_node cpuhp_node;
351
352 struct pmu pmu;
353 struct dentry *debug;
354};
355
356#define to_cmn(p) container_of(p, struct arm_cmn, pmu)
357
358static int arm_cmn_hp_state;
359
360struct arm_cmn_nodeid {
361 u8 x;
362 u8 y;
363 u8 port;
364 u8 dev;
365};
366
367static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
368{
369 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1) | 2);
370}
371
372static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn *cmn, u16 id)
373{
374 struct arm_cmn_nodeid nid;
375
376 if (cmn->num_xps == 1) {
377 nid.x = 0;
378 nid.y = 0;
379 nid.port = CMN_NODEID_1x1_PID(id);
380 nid.dev = CMN_NODEID_DEVID(id);
381 } else {
382 int bits = arm_cmn_xyidbits(cmn);
383
384 nid.x = CMN_NODEID_X(id, bits);
385 nid.y = CMN_NODEID_Y(id, bits);
386 if (cmn->ports_used & 0xc) {
387 nid.port = CMN_NODEID_EXT_PID(id);
388 nid.dev = CMN_NODEID_EXT_DEVID(id);
389 } else {
390 nid.port = CMN_NODEID_PID(id);
391 nid.dev = CMN_NODEID_DEVID(id);
392 }
393 }
394 return nid;
395}
396
397static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
398 const struct arm_cmn_node *dn)
399{
400 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
401 int xp_idx = cmn->mesh_x * nid.y + nid.x;
402
403 return cmn->xps + xp_idx;
404}
405static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
406 enum cmn_node_type type)
407{
408 struct arm_cmn_node *dn;
409
410 for (dn = cmn->dns; dn->type; dn++)
411 if (dn->type == type)
412 return dn;
413 return NULL;
414}
415
416static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
417{
418 switch (cmn->part) {
419 case PART_CMN600:
420 return CMN600;
421 case PART_CMN650:
422 return CMN650;
423 case PART_CMN700:
424 return CMN700;
425 case PART_CI700:
426 return CI700;
427 default:
428 return 0;
429 };
430}
431
432static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
433 const struct arm_cmn_node *xp, int port)
434{
435 int offset = CMN_MXP__CONNECT_INFO(port);
436
437 if (port >= 2) {
438 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
439 return 0;
440 /*
441 * CI-700 may have extra ports, but still has the
442 * mesh_port_connect_info registers in the way.
443 */
444 if (cmn->part == PART_CI700)
445 offset += CI700_CONNECT_INFO_P2_5_OFFSET;
446 }
447
448 return readl_relaxed(xp->pmu_base - CMN_PMU_OFFSET + offset);
449}
450
451static struct dentry *arm_cmn_debugfs;
452
453#ifdef CONFIG_DEBUG_FS
454static const char *arm_cmn_device_type(u8 type)
455{
456 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
457 case 0x00: return " |";
458 case 0x01: return " RN-I |";
459 case 0x02: return " RN-D |";
460 case 0x04: return " RN-F_B |";
461 case 0x05: return "RN-F_B_E|";
462 case 0x06: return " RN-F_A |";
463 case 0x07: return "RN-F_A_E|";
464 case 0x08: return " HN-T |";
465 case 0x09: return " HN-I |";
466 case 0x0a: return " HN-D |";
467 case 0x0b: return " HN-P |";
468 case 0x0c: return " SN-F |";
469 case 0x0d: return " SBSX |";
470 case 0x0e: return " HN-F |";
471 case 0x0f: return " SN-F_E |";
472 case 0x10: return " SN-F_D |";
473 case 0x11: return " CXHA |";
474 case 0x12: return " CXRA |";
475 case 0x13: return " CXRH |";
476 case 0x14: return " RN-F_D |";
477 case 0x15: return "RN-F_D_E|";
478 case 0x16: return " RN-F_C |";
479 case 0x17: return "RN-F_C_E|";
480 case 0x18: return " RN-F_E |";
481 case 0x19: return "RN-F_E_E|";
482 case 0x1c: return " MTSX |";
483 case 0x1d: return " HN-V |";
484 case 0x1e: return " CCG |";
485 default: return " ???? |";
486 }
487}
488
489static void arm_cmn_show_logid(struct seq_file *s, int x, int y, int p, int d)
490{
491 struct arm_cmn *cmn = s->private;
492 struct arm_cmn_node *dn;
493
494 for (dn = cmn->dns; dn->type; dn++) {
495 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
496
497 if (dn->type == CMN_TYPE_XP)
498 continue;
499 /* Ignore the extra components that will overlap on some ports */
500 if (dn->type < CMN_TYPE_HNI)
501 continue;
502
503 if (nid.x != x || nid.y != y || nid.port != p || nid.dev != d)
504 continue;
505
506 seq_printf(s, " #%-2d |", dn->logid);
507 return;
508 }
509 seq_puts(s, " |");
510}
511
512static int arm_cmn_map_show(struct seq_file *s, void *data)
513{
514 struct arm_cmn *cmn = s->private;
515 int x, y, p, pmax = fls(cmn->ports_used);
516
517 seq_puts(s, " X");
518 for (x = 0; x < cmn->mesh_x; x++)
519 seq_printf(s, " %d ", x);
520 seq_puts(s, "\nY P D+");
521 y = cmn->mesh_y;
522 while (y--) {
523 int xp_base = cmn->mesh_x * y;
524 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
525
526 for (x = 0; x < cmn->mesh_x; x++)
527 seq_puts(s, "--------+");
528
529 seq_printf(s, "\n%d |", y);
530 for (x = 0; x < cmn->mesh_x; x++) {
531 struct arm_cmn_node *xp = cmn->xps + xp_base + x;
532
533 for (p = 0; p < CMN_MAX_PORTS; p++)
534 port[p][x] = arm_cmn_device_connect_info(cmn, xp, p);
535 seq_printf(s, " XP #%-2d |", xp_base + x);
536 }
537
538 seq_puts(s, "\n |");
539 for (x = 0; x < cmn->mesh_x; x++) {
540 s8 dtc = cmn->xps[xp_base + x].dtc;
541
542 if (dtc < 0)
543 seq_puts(s, " DTC ?? |");
544 else
545 seq_printf(s, " DTC %d |", dtc);
546 }
547 seq_puts(s, "\n |");
548 for (x = 0; x < cmn->mesh_x; x++)
549 seq_puts(s, "........|");
550
551 for (p = 0; p < pmax; p++) {
552 seq_printf(s, "\n %d |", p);
553 for (x = 0; x < cmn->mesh_x; x++)
554 seq_puts(s, arm_cmn_device_type(port[p][x]));
555 seq_puts(s, "\n 0|");
556 for (x = 0; x < cmn->mesh_x; x++)
557 arm_cmn_show_logid(s, x, y, p, 0);
558 seq_puts(s, "\n 1|");
559 for (x = 0; x < cmn->mesh_x; x++)
560 arm_cmn_show_logid(s, x, y, p, 1);
561 }
562 seq_puts(s, "\n-----+");
563 }
564 for (x = 0; x < cmn->mesh_x; x++)
565 seq_puts(s, "--------+");
566 seq_puts(s, "\n");
567 return 0;
568}
569DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
570
571static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
572{
573 const char *name = "map";
574
575 if (id > 0)
576 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
577 if (!name)
578 return;
579
580 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
581}
582#else
583static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
584#endif
585
586struct arm_cmn_hw_event {
587 struct arm_cmn_node *dn;
588 u64 dtm_idx[4];
589 s8 dtc_idx[CMN_MAX_DTCS];
590 u8 num_dns;
591 u8 dtm_offset;
592 bool wide_sel;
593 enum cmn_filter_select filter_sel;
594};
595
596#define for_each_hw_dn(hw, dn, i) \
597 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
598
599/* @i is the DTC number, @idx is the counter index on that DTC */
600#define for_each_hw_dtc_idx(hw, i, idx) \
601 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0)
602
603static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
604{
605 BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
606 return (struct arm_cmn_hw_event *)&event->hw;
607}
608
609static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
610{
611 x[pos / 32] |= (u64)val << ((pos % 32) * 2);
612}
613
614static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
615{
616 return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
617}
618
619struct arm_cmn_event_attr {
620 struct device_attribute attr;
621 enum cmn_model model;
622 enum cmn_node_type type;
623 enum cmn_filter_select fsel;
624 u16 eventid;
625 u8 occupid;
626};
627
628struct arm_cmn_format_attr {
629 struct device_attribute attr;
630 u64 field;
631 int config;
632};
633
634#define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
635 (&((struct arm_cmn_event_attr[]) {{ \
636 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \
637 .model = _model, \
638 .type = _type, \
639 .eventid = _eventid, \
640 .occupid = _occupid, \
641 .fsel = _fsel, \
642 }})[0].attr.attr)
643#define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \
644 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
645
646static ssize_t arm_cmn_event_show(struct device *dev,
647 struct device_attribute *attr, char *buf)
648{
649 struct arm_cmn_event_attr *eattr;
650
651 eattr = container_of(attr, typeof(*eattr), attr);
652
653 if (eattr->type == CMN_TYPE_DTC)
654 return sysfs_emit(buf, "type=0x%x\n", eattr->type);
655
656 if (eattr->type == CMN_TYPE_WP)
657 return sysfs_emit(buf,
658 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
659 eattr->type, eattr->eventid);
660
661 if (eattr->fsel > SEL_NONE)
662 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
663 eattr->type, eattr->eventid, eattr->occupid);
664
665 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
666 eattr->eventid);
667}
668
669static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
670 struct attribute *attr,
671 int unused)
672{
673 struct device *dev = kobj_to_dev(kobj);
674 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
675 struct arm_cmn_event_attr *eattr;
676 enum cmn_node_type type;
677 u16 eventid;
678
679 eattr = container_of(attr, typeof(*eattr), attr.attr);
680
681 if (!(eattr->model & arm_cmn_model(cmn)))
682 return 0;
683
684 type = eattr->type;
685 eventid = eattr->eventid;
686
687 /* Watchpoints aren't nodes, so avoid confusion */
688 if (type == CMN_TYPE_WP)
689 return attr->mode;
690
691 /* Hide XP events for unused interfaces/channels */
692 if (type == CMN_TYPE_XP) {
693 unsigned int intf = (eventid >> 2) & 7;
694 unsigned int chan = eventid >> 5;
695
696 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
697 return 0;
698
699 if (chan == 4 && cmn->part == PART_CMN600)
700 return 0;
701
702 if ((chan == 5 && cmn->rsp_vc_num < 2) ||
703 (chan == 6 && cmn->dat_vc_num < 2) ||
704 (chan == 7 && cmn->snp_vc_num < 2) ||
705 (chan == 8 && cmn->req_vc_num < 2))
706 return 0;
707 }
708
709 /* Revision-specific differences */
710 if (cmn->part == PART_CMN600) {
711 if (cmn->rev < REV_CMN600_R1P3) {
712 if (type == CMN_TYPE_CXRA && eventid > 0x10)
713 return 0;
714 }
715 if (cmn->rev < REV_CMN600_R1P2) {
716 if (type == CMN_TYPE_HNF && eventid == 0x1b)
717 return 0;
718 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
719 return 0;
720 }
721 } else if (cmn->part == PART_CMN650) {
722 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
723 if (type == CMN_TYPE_HNF && eventid > 0x22)
724 return 0;
725 if (type == CMN_TYPE_SBSX && eventid == 0x17)
726 return 0;
727 if (type == CMN_TYPE_RNI && eventid > 0x10)
728 return 0;
729 }
730 } else if (cmn->part == PART_CMN700) {
731 if (cmn->rev < REV_CMN700_R2P0) {
732 if (type == CMN_TYPE_HNF && eventid > 0x2c)
733 return 0;
734 if (type == CMN_TYPE_CCHA && eventid > 0x74)
735 return 0;
736 if (type == CMN_TYPE_CCLA && eventid > 0x27)
737 return 0;
738 }
739 if (cmn->rev < REV_CMN700_R1P0) {
740 if (type == CMN_TYPE_HNF && eventid > 0x2b)
741 return 0;
742 }
743 }
744
745 if (!arm_cmn_node(cmn, type))
746 return 0;
747
748 return attr->mode;
749}
750
751#define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \
752 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
753#define CMN_EVENT_DTC(_name) \
754 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
755#define CMN_EVENT_HNF(_model, _name, _event) \
756 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event)
757#define CMN_EVENT_HNI(_name, _event) \
758 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
759#define CMN_EVENT_HNP(_name, _event) \
760 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
761#define __CMN_EVENT_XP(_name, _event) \
762 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
763#define CMN_EVENT_SBSX(_model, _name, _event) \
764 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
765#define CMN_EVENT_RNID(_model, _name, _event) \
766 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
767#define CMN_EVENT_MTSX(_name, _event) \
768 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
769#define CMN_EVENT_CXRA(_model, _name, _event) \
770 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
771#define CMN_EVENT_CXHA(_name, _event) \
772 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
773#define CMN_EVENT_CCRA(_name, _event) \
774 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
775#define CMN_EVENT_CCHA(_name, _event) \
776 CMN_EVENT_ATTR(CMN_ANY, ccha_##_name, CMN_TYPE_CCHA, _event)
777#define CMN_EVENT_CCLA(_name, _event) \
778 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
779#define CMN_EVENT_CCLA_RNI(_name, _event) \
780 CMN_EVENT_ATTR(CMN_ANY, ccla_rni_##_name, CMN_TYPE_CCLA_RNI, _event)
781#define CMN_EVENT_HNS(_name, _event) \
782 CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
783
784#define CMN_EVENT_DVM(_model, _name, _event) \
785 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
786#define CMN_EVENT_DVM_OCC(_model, _name, _event) \
787 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \
788 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
789 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
790
791#define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \
792 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \
793 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \
794 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \
795 _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \
796 _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID)
797#define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \
798 _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \
799 _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \
800 _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \
801 _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID)
802#define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \
803 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
804 _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
805 _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
806 _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
807 _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
808 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
809 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
810
811#define CMN_EVENT_HNF_OCC(_model, _name, _event) \
812 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event)
813#define CMN_EVENT_HNF_CLS(_model, _name, _event) \
814 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event)
815#define CMN_EVENT_HNF_SNT(_model, _name, _event) \
816 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event)
817
818#define CMN_EVENT_HNS_OCC(_name, _event) \
819 CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event), \
820 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \
821 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \
822 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID)
823#define CMN_EVENT_HNS_CLS( _name, _event) \
824 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
825#define CMN_EVENT_HNS_SNT(_name, _event) \
826 CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
827#define CMN_EVENT_HNS_HBT(_name, _event) \
828 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \
829 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \
830 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL)
831#define CMN_EVENT_HNS_SNH(_name, _event) \
832 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \
833 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \
834 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL)
835
836#define _CMN_EVENT_XP_MESH(_name, _event) \
837 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \
838 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \
839 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \
840 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2))
841
842#define _CMN_EVENT_XP_PORT(_name, _event) \
843 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \
844 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \
845 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \
846 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
847
848#define _CMN_EVENT_XP(_name, _event) \
849 _CMN_EVENT_XP_MESH(_name, _event), \
850 _CMN_EVENT_XP_PORT(_name, _event)
851
852/* Good thing there are only 3 fundamental XP events... */
853#define CMN_EVENT_XP(_name, _event) \
854 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \
855 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \
856 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \
857 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \
858 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \
859 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \
860 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \
861 _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \
862 _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
863
864#define CMN_EVENT_XP_DAT(_name, _event) \
865 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \
866 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5))
867
868
869static struct attribute *arm_cmn_event_attrs[] = {
870 CMN_EVENT_DTC(cycles),
871
872 /*
873 * DVM node events conflict with HN-I events in the equivalent PMU
874 * slot, but our lazy short-cut of using the DTM counter index for
875 * the PMU index as well happens to avoid that by construction.
876 */
877 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01),
878 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02),
879 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
880 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04),
881 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05),
882 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01),
883 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02),
884 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03),
885 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04),
886 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05),
887 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06),
888 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07),
889 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08),
890 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09),
891 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a),
892 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b),
893 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c),
894 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d),
895 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e),
896 CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f),
897 CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10),
898 CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11),
899 CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12),
900 CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13),
901 CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14),
902
903 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01),
904 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02),
905 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03),
906 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04),
907 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05),
908 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06),
909 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07),
910 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08),
911 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09),
912 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a),
913 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b),
914 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c),
915 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d),
916 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e),
917 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f),
918 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10),
919 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11),
920 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12),
921 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13),
922 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14),
923 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15),
924 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16),
925 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17),
926 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18),
927 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19),
928 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a),
929 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b),
930 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c),
931 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d),
932 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e),
933 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f),
934 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20),
935 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21),
936 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22),
937 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23),
938 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24),
939 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25),
940 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26),
941 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27),
942 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28),
943 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29),
944 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a),
945 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b),
946 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c),
947 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d),
948 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e),
949 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f),
950
951 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20),
952 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21),
953 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22),
954 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23),
955 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24),
956 CMN_EVENT_HNI(rrt_rd_alloc, 0x25),
957 CMN_EVENT_HNI(rrt_wr_alloc, 0x26),
958 CMN_EVENT_HNI(rdt_rd_alloc, 0x27),
959 CMN_EVENT_HNI(rdt_wr_alloc, 0x28),
960 CMN_EVENT_HNI(wdb_alloc, 0x29),
961 CMN_EVENT_HNI(txrsp_retryack, 0x2a),
962 CMN_EVENT_HNI(arvalid_no_arready, 0x2b),
963 CMN_EVENT_HNI(arready_no_arvalid, 0x2c),
964 CMN_EVENT_HNI(awvalid_no_awready, 0x2d),
965 CMN_EVENT_HNI(awready_no_awvalid, 0x2e),
966 CMN_EVENT_HNI(wvalid_no_wready, 0x2f),
967 CMN_EVENT_HNI(txdat_stall, 0x30),
968 CMN_EVENT_HNI(nonpcie_serialization, 0x31),
969 CMN_EVENT_HNI(pcie_serialization, 0x32),
970
971 /*
972 * HN-P events squat on top of the HN-I similarly to DVM events, except
973 * for being crammed into the same physical node as well. And of course
974 * where would the fun be if the same events were in the same order...
975 */
976 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01),
977 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02),
978 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03),
979 CMN_EVENT_HNP(rrt_wr_alloc, 0x04),
980 CMN_EVENT_HNP(rdt_wr_alloc, 0x05),
981 CMN_EVENT_HNP(wdb_alloc, 0x06),
982 CMN_EVENT_HNP(awvalid_no_awready, 0x07),
983 CMN_EVENT_HNP(awready_no_awvalid, 0x08),
984 CMN_EVENT_HNP(wvalid_no_wready, 0x09),
985 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11),
986 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12),
987 CMN_EVENT_HNP(rrt_rd_alloc, 0x13),
988 CMN_EVENT_HNP(rdt_rd_alloc, 0x14),
989 CMN_EVENT_HNP(arvalid_no_arready, 0x15),
990 CMN_EVENT_HNP(arready_no_arvalid, 0x16),
991
992 CMN_EVENT_XP(txflit_valid, 0x01),
993 CMN_EVENT_XP(txflit_stall, 0x02),
994 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03),
995 /* We treat watchpoints as a special made-up class of XP events */
996 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
997 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
998
999 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01),
1000 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02),
1001 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03),
1002 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04),
1003 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05),
1004 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06),
1005 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
1006 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
1007 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
1008 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14),
1009 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
1010 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
1011 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17),
1012 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21),
1013 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22),
1014 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23),
1015 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24),
1016 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25),
1017
1018 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01),
1019 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02),
1020 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03),
1021 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04),
1022 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05),
1023 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06),
1024 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07),
1025 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08),
1026 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09),
1027 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a),
1028 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b),
1029 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c),
1030 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d),
1031 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e),
1032 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f),
1033 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10),
1034 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11),
1035 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12),
1036 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13),
1037 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14),
1038 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11),
1039 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12),
1040 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
1041 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
1042 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
1043 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16),
1044 CMN_EVENT_RNID(CMN700, ldb_full, 0x17),
1045 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
1046 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
1047 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
1048 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
1049 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
1050 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
1051 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
1052 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
1053 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20),
1054 CMN_EVENT_RNID(CMN700, awid_hash, 0x21),
1055 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22),
1056 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23),
1057
1058 CMN_EVENT_MTSX(tc_lookup, 0x01),
1059 CMN_EVENT_MTSX(tc_fill, 0x02),
1060 CMN_EVENT_MTSX(tc_miss, 0x03),
1061 CMN_EVENT_MTSX(tdb_forward, 0x04),
1062 CMN_EVENT_MTSX(tcq_hazard, 0x05),
1063 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06),
1064 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07),
1065 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08),
1066 CMN_EVENT_MTSX(axi_rd_req, 0x09),
1067 CMN_EVENT_MTSX(axi_wr_req, 0x0a),
1068 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b),
1069 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c),
1070
1071 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01),
1072 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02),
1073 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03),
1074 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04),
1075 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05),
1076 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06),
1077 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07),
1078 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08),
1079 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09),
1080 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a),
1081 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
1082 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
1083 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
1084 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
1085 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
1086 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
1087 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
1088 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
1089 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
1090 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
1091 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
1092
1093 CMN_EVENT_CXHA(rddatbyp, 0x21),
1094 CMN_EVENT_CXHA(chirsp_up_stall, 0x22),
1095 CMN_EVENT_CXHA(chidat_up_stall, 0x23),
1096 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24),
1097 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25),
1098 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26),
1099 CMN_EVENT_CXHA(reqtrk_occ, 0x27),
1100 CMN_EVENT_CXHA(rdb_occ, 0x28),
1101 CMN_EVENT_CXHA(rdbyp_occ, 0x29),
1102 CMN_EVENT_CXHA(wdb_occ, 0x2a),
1103 CMN_EVENT_CXHA(snptrk_occ, 0x2b),
1104 CMN_EVENT_CXHA(sdb_occ, 0x2c),
1105 CMN_EVENT_CXHA(snphaz_occ, 0x2d),
1106
1107 CMN_EVENT_CCRA(rht_occ, 0x41),
1108 CMN_EVENT_CCRA(sht_occ, 0x42),
1109 CMN_EVENT_CCRA(rdb_occ, 0x43),
1110 CMN_EVENT_CCRA(wdb_occ, 0x44),
1111 CMN_EVENT_CCRA(ssb_occ, 0x45),
1112 CMN_EVENT_CCRA(snp_bcasts, 0x46),
1113 CMN_EVENT_CCRA(req_chains, 0x47),
1114 CMN_EVENT_CCRA(req_chain_avglen, 0x48),
1115 CMN_EVENT_CCRA(chirsp_stalls, 0x49),
1116 CMN_EVENT_CCRA(chidat_stalls, 0x4a),
1117 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b),
1118 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c),
1119 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d),
1120 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e),
1121 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f),
1122 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50),
1123 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51),
1124 CMN_EVENT_CCRA(external_chidat_stalls, 0x52),
1125 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53),
1126 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54),
1127 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55),
1128 CMN_EVENT_CCRA(rht_alloc, 0x56),
1129 CMN_EVENT_CCRA(sht_alloc, 0x57),
1130 CMN_EVENT_CCRA(rdb_alloc, 0x58),
1131 CMN_EVENT_CCRA(wdb_alloc, 0x59),
1132 CMN_EVENT_CCRA(ssb_alloc, 0x5a),
1133
1134 CMN_EVENT_CCHA(rddatbyp, 0x61),
1135 CMN_EVENT_CCHA(chirsp_up_stall, 0x62),
1136 CMN_EVENT_CCHA(chidat_up_stall, 0x63),
1137 CMN_EVENT_CCHA(snppcrd_link0_stall, 0x64),
1138 CMN_EVENT_CCHA(snppcrd_link1_stall, 0x65),
1139 CMN_EVENT_CCHA(snppcrd_link2_stall, 0x66),
1140 CMN_EVENT_CCHA(reqtrk_occ, 0x67),
1141 CMN_EVENT_CCHA(rdb_occ, 0x68),
1142 CMN_EVENT_CCHA(rdbyp_occ, 0x69),
1143 CMN_EVENT_CCHA(wdb_occ, 0x6a),
1144 CMN_EVENT_CCHA(snptrk_occ, 0x6b),
1145 CMN_EVENT_CCHA(sdb_occ, 0x6c),
1146 CMN_EVENT_CCHA(snphaz_occ, 0x6d),
1147 CMN_EVENT_CCHA(reqtrk_alloc, 0x6e),
1148 CMN_EVENT_CCHA(rdb_alloc, 0x6f),
1149 CMN_EVENT_CCHA(rdbyp_alloc, 0x70),
1150 CMN_EVENT_CCHA(wdb_alloc, 0x71),
1151 CMN_EVENT_CCHA(snptrk_alloc, 0x72),
1152 CMN_EVENT_CCHA(sdb_alloc, 0x73),
1153 CMN_EVENT_CCHA(snphaz_alloc, 0x74),
1154 CMN_EVENT_CCHA(pb_rhu_req_occ, 0x75),
1155 CMN_EVENT_CCHA(pb_rhu_req_alloc, 0x76),
1156 CMN_EVENT_CCHA(pb_rhu_pcie_req_occ, 0x77),
1157 CMN_EVENT_CCHA(pb_rhu_pcie_req_alloc, 0x78),
1158 CMN_EVENT_CCHA(pb_pcie_wr_req_occ, 0x79),
1159 CMN_EVENT_CCHA(pb_pcie_wr_req_alloc, 0x7a),
1160 CMN_EVENT_CCHA(pb_pcie_reg_req_occ, 0x7b),
1161 CMN_EVENT_CCHA(pb_pcie_reg_req_alloc, 0x7c),
1162 CMN_EVENT_CCHA(pb_pcie_rsvd_req_occ, 0x7d),
1163 CMN_EVENT_CCHA(pb_pcie_rsvd_req_alloc, 0x7e),
1164 CMN_EVENT_CCHA(pb_rhu_dat_occ, 0x7f),
1165 CMN_EVENT_CCHA(pb_rhu_dat_alloc, 0x80),
1166 CMN_EVENT_CCHA(pb_rhu_pcie_dat_occ, 0x81),
1167 CMN_EVENT_CCHA(pb_rhu_pcie_dat_alloc, 0x82),
1168 CMN_EVENT_CCHA(pb_pcie_wr_dat_occ, 0x83),
1169 CMN_EVENT_CCHA(pb_pcie_wr_dat_alloc, 0x84),
1170
1171 CMN_EVENT_CCLA(rx_cxs, 0x21),
1172 CMN_EVENT_CCLA(tx_cxs, 0x22),
1173 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23),
1174 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24),
1175 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25),
1176 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26),
1177 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27),
1178 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28),
1179 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29),
1180 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a),
1181 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b),
1182
1183 CMN_EVENT_HNS_HBT(cache_miss, 0x01),
1184 CMN_EVENT_HNS_HBT(slc_sf_cache_access, 0x02),
1185 CMN_EVENT_HNS_HBT(cache_fill, 0x03),
1186 CMN_EVENT_HNS_HBT(pocq_retry, 0x04),
1187 CMN_EVENT_HNS_HBT(pocq_reqs_recvd, 0x05),
1188 CMN_EVENT_HNS_HBT(sf_hit, 0x06),
1189 CMN_EVENT_HNS_HBT(sf_evictions, 0x07),
1190 CMN_EVENT_HNS(dir_snoops_sent, 0x08),
1191 CMN_EVENT_HNS(brd_snoops_sent, 0x09),
1192 CMN_EVENT_HNS_HBT(slc_eviction, 0x0a),
1193 CMN_EVENT_HNS_HBT(slc_fill_invalid_way, 0x0b),
1194 CMN_EVENT_HNS(mc_retries_local, 0x0c),
1195 CMN_EVENT_HNS_SNH(mc_reqs_local, 0x0d),
1196 CMN_EVENT_HNS(qos_hh_retry, 0x0e),
1197 CMN_EVENT_HNS_OCC(qos_pocq_occupancy, 0x0f),
1198 CMN_EVENT_HNS(pocq_addrhaz, 0x10),
1199 CMN_EVENT_HNS(pocq_atomic_addrhaz, 0x11),
1200 CMN_EVENT_HNS(ld_st_swp_adq_full, 0x12),
1201 CMN_EVENT_HNS(cmp_adq_full, 0x13),
1202 CMN_EVENT_HNS(txdat_stall, 0x14),
1203 CMN_EVENT_HNS(txrsp_stall, 0x15),
1204 CMN_EVENT_HNS(seq_full, 0x16),
1205 CMN_EVENT_HNS(seq_hit, 0x17),
1206 CMN_EVENT_HNS(snp_sent, 0x18),
1207 CMN_EVENT_HNS(sfbi_dir_snp_sent, 0x19),
1208 CMN_EVENT_HNS(sfbi_brd_snp_sent, 0x1a),
1209 CMN_EVENT_HNS(intv_dirty, 0x1c),
1210 CMN_EVENT_HNS(stash_snp_sent, 0x1d),
1211 CMN_EVENT_HNS(stash_data_pull, 0x1e),
1212 CMN_EVENT_HNS(snp_fwded, 0x1f),
1213 CMN_EVENT_HNS(atomic_fwd, 0x20),
1214 CMN_EVENT_HNS(mpam_hardlim, 0x21),
1215 CMN_EVENT_HNS(mpam_softlim, 0x22),
1216 CMN_EVENT_HNS(snp_sent_cluster, 0x23),
1217 CMN_EVENT_HNS(sf_imprecise_evict, 0x24),
1218 CMN_EVENT_HNS(sf_evict_shared_line, 0x25),
1219 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26),
1220 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27),
1221 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28),
1222 CMN_EVENT_HNS_CLS(class_cgnt_cmin, 0x29),
1223 CMN_EVENT_HNS_SNT(sn_throttle, 0x2a),
1224 CMN_EVENT_HNS_SNT(sn_throttle_min, 0x2b),
1225 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c),
1226 CMN_EVENT_HNS(snp_intv_cln, 0x2d),
1227 CMN_EVENT_HNS(nc_excl, 0x2e),
1228 CMN_EVENT_HNS(excl_mon_ovfl, 0x2f),
1229 CMN_EVENT_HNS(snp_req_recvd, 0x30),
1230 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31),
1231 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32),
1232 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33),
1233 CMN_EVENT_HNS(ccgha_snp_stall, 0x34),
1234 CMN_EVENT_HNS(lbt_req_hardlim, 0x35),
1235 CMN_EVENT_HNS(hbt_req_hardlim, 0x36),
1236 CMN_EVENT_HNS(sf_reupdate, 0x37),
1237 CMN_EVENT_HNS(excl_sf_imprecise, 0x38),
1238 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39),
1239 CMN_EVENT_HNS(mc_retries_remote, 0x3a),
1240 CMN_EVENT_HNS_SNH(mc_reqs_remote, 0x3b),
1241 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c),
1242
1243 NULL
1244};
1245
1246static const struct attribute_group arm_cmn_event_attrs_group = {
1247 .name = "events",
1248 .attrs = arm_cmn_event_attrs,
1249 .is_visible = arm_cmn_event_attr_is_visible,
1250};
1251
1252static ssize_t arm_cmn_format_show(struct device *dev,
1253 struct device_attribute *attr, char *buf)
1254{
1255 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
1256 int lo = __ffs(fmt->field), hi = __fls(fmt->field);
1257
1258 if (lo == hi)
1259 return sysfs_emit(buf, "config:%d\n", lo);
1260
1261 if (!fmt->config)
1262 return sysfs_emit(buf, "config:%d-%d\n", lo, hi);
1263
1264 return sysfs_emit(buf, "config%d:%d-%d\n", fmt->config, lo, hi);
1265}
1266
1267#define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \
1268 (&((struct arm_cmn_format_attr[]) {{ \
1269 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
1270 .config = _cfg, \
1271 .field = _fld, \
1272 }})[0].attr.attr)
1273#define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld)
1274
1275static struct attribute *arm_cmn_format_attrs[] = {
1276 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
1277 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
1278 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
1279 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
1280 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
1281
1282 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
1283 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
1284 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
1285 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
1286 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
1287
1288 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
1289 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
1290
1291 NULL
1292};
1293
1294static const struct attribute_group arm_cmn_format_attrs_group = {
1295 .name = "format",
1296 .attrs = arm_cmn_format_attrs,
1297};
1298
1299static ssize_t arm_cmn_cpumask_show(struct device *dev,
1300 struct device_attribute *attr, char *buf)
1301{
1302 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1303
1304 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
1305}
1306
1307static struct device_attribute arm_cmn_cpumask_attr =
1308 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
1309
1310static ssize_t arm_cmn_identifier_show(struct device *dev,
1311 struct device_attribute *attr, char *buf)
1312{
1313 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1314
1315 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev);
1316}
1317
1318static struct device_attribute arm_cmn_identifier_attr =
1319 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL);
1320
1321static struct attribute *arm_cmn_other_attrs[] = {
1322 &arm_cmn_cpumask_attr.attr,
1323 &arm_cmn_identifier_attr.attr,
1324 NULL,
1325};
1326
1327static const struct attribute_group arm_cmn_other_attrs_group = {
1328 .attrs = arm_cmn_other_attrs,
1329};
1330
1331static const struct attribute_group *arm_cmn_attr_groups[] = {
1332 &arm_cmn_event_attrs_group,
1333 &arm_cmn_format_attrs_group,
1334 &arm_cmn_other_attrs_group,
1335 NULL
1336};
1337
1338static int arm_cmn_wp_idx(struct perf_event *event)
1339{
1340 return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
1341}
1342
1343static u32 arm_cmn_wp_config(struct perf_event *event)
1344{
1345 u32 config;
1346 u32 dev = CMN_EVENT_WP_DEV_SEL(event);
1347 u32 chn = CMN_EVENT_WP_CHN_SEL(event);
1348 u32 grp = CMN_EVENT_WP_GRP(event);
1349 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
1350 u32 combine = CMN_EVENT_WP_COMBINE(event);
1351 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
1352
1353 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
1354 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
1355 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
1356 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
1357 if (exc)
1358 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
1359 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
1360 if (combine && !grp)
1361 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
1362 CMN_DTM_WPn_CONFIG_WP_COMBINE;
1363 return config;
1364}
1365
1366static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
1367{
1368 if (!cmn->state)
1369 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1370 cmn->state |= state;
1371}
1372
1373static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
1374{
1375 cmn->state &= ~state;
1376 if (!cmn->state)
1377 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
1378 cmn->dtc[0].base + CMN_DT_PMCR);
1379}
1380
1381static void arm_cmn_pmu_enable(struct pmu *pmu)
1382{
1383 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
1384}
1385
1386static void arm_cmn_pmu_disable(struct pmu *pmu)
1387{
1388 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
1389}
1390
1391static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
1392 bool snapshot)
1393{
1394 struct arm_cmn_dtm *dtm = NULL;
1395 struct arm_cmn_node *dn;
1396 unsigned int i, offset, dtm_idx;
1397 u64 reg, count = 0;
1398
1399 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
1400 for_each_hw_dn(hw, dn, i) {
1401 if (dtm != &cmn->dtms[dn->dtm]) {
1402 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1403 reg = readq_relaxed(dtm->base + offset);
1404 }
1405 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1406 count += (u16)(reg >> (dtm_idx * 16));
1407 }
1408 return count;
1409}
1410
1411static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1412{
1413 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1414
1415 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1416 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
1417}
1418
1419static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1420{
1421 u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
1422
1423 val = readl_relaxed(dtc->base + pmevcnt);
1424 writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1425 return val - CMN_COUNTER_INIT;
1426}
1427
1428static void arm_cmn_init_counter(struct perf_event *event)
1429{
1430 struct arm_cmn *cmn = to_cmn(event->pmu);
1431 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1432 u64 count;
1433
1434 for_each_hw_dtc_idx(hw, i, idx) {
1435 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + CMN_DT_PMEVCNT(idx));
1436 cmn->dtc[i].counters[idx] = event;
1437 }
1438
1439 count = arm_cmn_read_dtm(cmn, hw, false);
1440 local64_set(&event->hw.prev_count, count);
1441}
1442
1443static void arm_cmn_event_read(struct perf_event *event)
1444{
1445 struct arm_cmn *cmn = to_cmn(event->pmu);
1446 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1447 u64 delta, new, prev;
1448 unsigned long flags;
1449
1450 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) {
1451 delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]);
1452 local64_add(delta, &event->count);
1453 return;
1454 }
1455 new = arm_cmn_read_dtm(cmn, hw, false);
1456 prev = local64_xchg(&event->hw.prev_count, new);
1457
1458 delta = new - prev;
1459
1460 local_irq_save(flags);
1461 for_each_hw_dtc_idx(hw, i, idx) {
1462 new = arm_cmn_read_counter(cmn->dtc + i, idx);
1463 delta += new << 16;
1464 }
1465 local_irq_restore(flags);
1466 local64_add(delta, &event->count);
1467}
1468
1469static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
1470 enum cmn_filter_select fsel, u8 occupid)
1471{
1472 u64 reg;
1473
1474 if (fsel == SEL_NONE)
1475 return 0;
1476
1477 if (!dn->occupid[fsel].count) {
1478 dn->occupid[fsel].val = occupid;
1479 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
1480 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
1481 FIELD_PREP(CMN__PMU_SN_HOME_SEL,
1482 dn->occupid[SEL_SN_HOME_SEL].val) |
1483 FIELD_PREP(CMN__PMU_HBT_LBT_SEL,
1484 dn->occupid[SEL_HBT_LBT_SEL].val) |
1485 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
1486 dn->occupid[SEL_CLASS_OCCUP_ID].val) |
1487 FIELD_PREP(CMN__PMU_OCCUP1_ID,
1488 dn->occupid[SEL_OCCUP1ID].val);
1489 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
1490 } else if (dn->occupid[fsel].val != occupid) {
1491 return -EBUSY;
1492 }
1493 dn->occupid[fsel].count++;
1494 return 0;
1495}
1496
1497static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
1498 int eventid, bool wide_sel)
1499{
1500 if (wide_sel) {
1501 dn->event_w[dtm_idx] = eventid;
1502 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1503 } else {
1504 dn->event[dtm_idx] = eventid;
1505 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
1506 }
1507}
1508
1509static void arm_cmn_event_start(struct perf_event *event, int flags)
1510{
1511 struct arm_cmn *cmn = to_cmn(event->pmu);
1512 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1513 struct arm_cmn_node *dn;
1514 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1515 int i;
1516
1517 if (type == CMN_TYPE_DTC) {
1518 i = hw->dtc_idx[0];
1519 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1520 cmn->dtc[i].cc_active = true;
1521 } else if (type == CMN_TYPE_WP) {
1522 int wp_idx = arm_cmn_wp_idx(event);
1523 u64 val = CMN_EVENT_WP_VAL(event);
1524 u64 mask = CMN_EVENT_WP_MASK(event);
1525
1526 for_each_hw_dn(hw, dn, i) {
1527 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1528
1529 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1530 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1531 }
1532 } else for_each_hw_dn(hw, dn, i) {
1533 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1534
1535 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
1536 hw->wide_sel);
1537 }
1538}
1539
1540static void arm_cmn_event_stop(struct perf_event *event, int flags)
1541{
1542 struct arm_cmn *cmn = to_cmn(event->pmu);
1543 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1544 struct arm_cmn_node *dn;
1545 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1546 int i;
1547
1548 if (type == CMN_TYPE_DTC) {
1549 i = hw->dtc_idx[0];
1550 cmn->dtc[i].cc_active = false;
1551 } else if (type == CMN_TYPE_WP) {
1552 int wp_idx = arm_cmn_wp_idx(event);
1553
1554 for_each_hw_dn(hw, dn, i) {
1555 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1556
1557 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1558 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1559 }
1560 } else for_each_hw_dn(hw, dn, i) {
1561 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1562
1563 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
1564 }
1565
1566 arm_cmn_event_read(event);
1567}
1568
1569struct arm_cmn_val {
1570 u8 dtm_count[CMN_MAX_DTMS];
1571 u8 occupid[CMN_MAX_DTMS][SEL_MAX];
1572 u8 wp[CMN_MAX_DTMS][4];
1573 int dtc_count[CMN_MAX_DTCS];
1574 bool cycles;
1575};
1576
1577static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
1578 struct perf_event *event)
1579{
1580 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1581 struct arm_cmn_node *dn;
1582 enum cmn_node_type type;
1583 int i;
1584
1585 if (is_software_event(event))
1586 return;
1587
1588 type = CMN_EVENT_TYPE(event);
1589 if (type == CMN_TYPE_DTC) {
1590 val->cycles = true;
1591 return;
1592 }
1593
1594 for_each_hw_dtc_idx(hw, dtc, idx)
1595 val->dtc_count[dtc]++;
1596
1597 for_each_hw_dn(hw, dn, i) {
1598 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1599
1600 val->dtm_count[dtm]++;
1601
1602 if (sel > SEL_NONE)
1603 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
1604
1605 if (type != CMN_TYPE_WP)
1606 continue;
1607
1608 wp_idx = arm_cmn_wp_idx(event);
1609 val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
1610 }
1611}
1612
1613static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
1614{
1615 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1616 struct arm_cmn_node *dn;
1617 struct perf_event *sibling, *leader = event->group_leader;
1618 enum cmn_node_type type;
1619 struct arm_cmn_val *val;
1620 int i, ret = -EINVAL;
1621
1622 if (leader == event)
1623 return 0;
1624
1625 if (event->pmu != leader->pmu && !is_software_event(leader))
1626 return -EINVAL;
1627
1628 val = kzalloc(sizeof(*val), GFP_KERNEL);
1629 if (!val)
1630 return -ENOMEM;
1631
1632 arm_cmn_val_add_event(cmn, val, leader);
1633 for_each_sibling_event(sibling, leader)
1634 arm_cmn_val_add_event(cmn, val, sibling);
1635
1636 type = CMN_EVENT_TYPE(event);
1637 if (type == CMN_TYPE_DTC) {
1638 ret = val->cycles ? -EINVAL : 0;
1639 goto done;
1640 }
1641
1642 for (i = 0; i < CMN_MAX_DTCS; i++)
1643 if (val->dtc_count[i] == CMN_DT_NUM_COUNTERS)
1644 goto done;
1645
1646 for_each_hw_dn(hw, dn, i) {
1647 int wp_idx, wp_cmb, dtm = dn->dtm, sel = hw->filter_sel;
1648
1649 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
1650 goto done;
1651
1652 if (sel > SEL_NONE && val->occupid[dtm][sel] &&
1653 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
1654 goto done;
1655
1656 if (type != CMN_TYPE_WP)
1657 continue;
1658
1659 wp_idx = arm_cmn_wp_idx(event);
1660 if (val->wp[dtm][wp_idx])
1661 goto done;
1662
1663 wp_cmb = val->wp[dtm][wp_idx ^ 1];
1664 if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
1665 goto done;
1666 }
1667
1668 ret = 0;
1669done:
1670 kfree(val);
1671 return ret;
1672}
1673
1674static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
1675 enum cmn_node_type type,
1676 unsigned int eventid)
1677{
1678 struct arm_cmn_event_attr *e;
1679 enum cmn_model model = arm_cmn_model(cmn);
1680
1681 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
1682 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
1683 if (e->model & model && e->type == type && e->eventid == eventid)
1684 return e->fsel;
1685 }
1686 return SEL_NONE;
1687}
1688
1689
1690static int arm_cmn_event_init(struct perf_event *event)
1691{
1692 struct arm_cmn *cmn = to_cmn(event->pmu);
1693 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1694 struct arm_cmn_node *dn;
1695 enum cmn_node_type type;
1696 bool bynodeid;
1697 u16 nodeid, eventid;
1698
1699 if (event->attr.type != event->pmu->type)
1700 return -ENOENT;
1701
1702 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1703 return -EINVAL;
1704
1705 event->cpu = cmn->cpu;
1706 if (event->cpu < 0)
1707 return -EINVAL;
1708
1709 type = CMN_EVENT_TYPE(event);
1710 /* DTC events (i.e. cycles) already have everything they need */
1711 if (type == CMN_TYPE_DTC)
1712 return arm_cmn_validate_group(cmn, event);
1713
1714 eventid = CMN_EVENT_EVENTID(event);
1715 /* For watchpoints we need the actual XP node here */
1716 if (type == CMN_TYPE_WP) {
1717 type = CMN_TYPE_XP;
1718 /* ...and we need a "real" direction */
1719 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
1720 return -EINVAL;
1721 /* ...but the DTM may depend on which port we're watching */
1722 if (cmn->multi_dtm)
1723 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
1724 } else if (type == CMN_TYPE_XP && cmn->part == PART_CMN700) {
1725 hw->wide_sel = true;
1726 }
1727
1728 /* This is sufficiently annoying to recalculate, so cache it */
1729 hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
1730
1731 bynodeid = CMN_EVENT_BYNODEID(event);
1732 nodeid = CMN_EVENT_NODEID(event);
1733
1734 hw->dn = arm_cmn_node(cmn, type);
1735 if (!hw->dn)
1736 return -EINVAL;
1737
1738 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx));
1739 for (dn = hw->dn; dn->type == type; dn++) {
1740 if (bynodeid && dn->id != nodeid) {
1741 hw->dn++;
1742 continue;
1743 }
1744 hw->num_dns++;
1745 if (dn->dtc < 0)
1746 memset(hw->dtc_idx, 0, cmn->num_dtcs);
1747 else
1748 hw->dtc_idx[dn->dtc] = 0;
1749
1750 if (bynodeid)
1751 break;
1752 }
1753
1754 if (!hw->num_dns) {
1755 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, nodeid);
1756
1757 dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
1758 nodeid, nid.x, nid.y, nid.port, nid.dev, type);
1759 return -EINVAL;
1760 }
1761
1762 return arm_cmn_validate_group(cmn, event);
1763}
1764
1765static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
1766 int i)
1767{
1768 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1769 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1770
1771 while (i--) {
1772 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
1773 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1774
1775 if (type == CMN_TYPE_WP)
1776 dtm->wp_event[arm_cmn_wp_idx(event)] = -1;
1777
1778 if (hw->filter_sel > SEL_NONE)
1779 hw->dn[i].occupid[hw->filter_sel].count--;
1780
1781 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1782 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1783 }
1784 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
1785
1786 for_each_hw_dtc_idx(hw, j, idx)
1787 cmn->dtc[j].counters[idx] = NULL;
1788}
1789
1790static int arm_cmn_event_add(struct perf_event *event, int flags)
1791{
1792 struct arm_cmn *cmn = to_cmn(event->pmu);
1793 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1794 struct arm_cmn_node *dn;
1795 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1796 unsigned int input_sel, i = 0;
1797
1798 if (type == CMN_TYPE_DTC) {
1799 while (cmn->dtc[i].cycles)
1800 if (++i == cmn->num_dtcs)
1801 return -ENOSPC;
1802
1803 cmn->dtc[i].cycles = event;
1804 hw->dtc_idx[0] = i;
1805
1806 if (flags & PERF_EF_START)
1807 arm_cmn_event_start(event, 0);
1808 return 0;
1809 }
1810
1811 /* Grab the global counters first... */
1812 for_each_hw_dtc_idx(hw, j, idx) {
1813 if (cmn->part == PART_CMN600 && j > 0) {
1814 idx = hw->dtc_idx[0];
1815 } else {
1816 idx = 0;
1817 while (cmn->dtc[j].counters[idx])
1818 if (++idx == CMN_DT_NUM_COUNTERS)
1819 return -ENOSPC;
1820 }
1821 hw->dtc_idx[j] = idx;
1822 }
1823
1824 /* ...then the local counters to feed them */
1825 for_each_hw_dn(hw, dn, i) {
1826 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1827 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0);
1828 u64 reg;
1829
1830 dtm_idx = 0;
1831 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1832 if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
1833 goto free_dtms;
1834
1835 if (type == CMN_TYPE_XP) {
1836 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
1837 } else if (type == CMN_TYPE_WP) {
1838 int tmp, wp_idx = arm_cmn_wp_idx(event);
1839 u32 cfg = arm_cmn_wp_config(event);
1840
1841 if (dtm->wp_event[wp_idx] >= 0)
1842 goto free_dtms;
1843
1844 tmp = dtm->wp_event[wp_idx ^ 1];
1845 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
1846 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp]))
1847 goto free_dtms;
1848
1849 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
1850 dtm->wp_event[wp_idx] = hw->dtc_idx[d];
1851 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1852 } else {
1853 struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
1854
1855 if (cmn->multi_dtm)
1856 nid.port %= 2;
1857
1858 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
1859 (nid.port << 4) + (nid.dev << 2);
1860
1861 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
1862 goto free_dtms;
1863 }
1864
1865 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
1866
1867 dtm->input_sel[dtm_idx] = input_sel;
1868 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
1869 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1870 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift;
1871 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1872 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
1873 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1874 }
1875
1876 /* Go go go! */
1877 arm_cmn_init_counter(event);
1878
1879 if (flags & PERF_EF_START)
1880 arm_cmn_event_start(event, 0);
1881
1882 return 0;
1883
1884free_dtms:
1885 arm_cmn_event_clear(cmn, event, i);
1886 return -ENOSPC;
1887}
1888
1889static void arm_cmn_event_del(struct perf_event *event, int flags)
1890{
1891 struct arm_cmn *cmn = to_cmn(event->pmu);
1892 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1893 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1894
1895 arm_cmn_event_stop(event, PERF_EF_UPDATE);
1896
1897 if (type == CMN_TYPE_DTC)
1898 cmn->dtc[hw->dtc_idx[0]].cycles = NULL;
1899 else
1900 arm_cmn_event_clear(cmn, event, hw->num_dns);
1901}
1902
1903/*
1904 * We stop the PMU for both add and read, to avoid skew across DTM counters.
1905 * In theory we could use snapshots to read without stopping, but then it
1906 * becomes a lot trickier to deal with overlow and racing against interrupts,
1907 * plus it seems they don't work properly on some hardware anyway :(
1908 */
1909static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
1910{
1911 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
1912}
1913
1914static void arm_cmn_end_txn(struct pmu *pmu)
1915{
1916 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
1917}
1918
1919static int arm_cmn_commit_txn(struct pmu *pmu)
1920{
1921 arm_cmn_end_txn(pmu);
1922 return 0;
1923}
1924
1925static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
1926{
1927 unsigned int i;
1928
1929 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
1930 for (i = 0; i < cmn->num_dtcs; i++)
1931 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
1932 cmn->cpu = cpu;
1933}
1934
1935static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1936{
1937 struct arm_cmn *cmn;
1938 int node;
1939
1940 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1941 node = dev_to_node(cmn->dev);
1942 if (node != NUMA_NO_NODE && cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
1943 arm_cmn_migrate(cmn, cpu);
1944 return 0;
1945}
1946
1947static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
1948{
1949 struct arm_cmn *cmn;
1950 unsigned int target;
1951 int node;
1952 cpumask_t mask;
1953
1954 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
1955 if (cpu != cmn->cpu)
1956 return 0;
1957
1958 node = dev_to_node(cmn->dev);
1959 if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) &&
1960 cpumask_andnot(&mask, &mask, cpumask_of(cpu)))
1961 target = cpumask_any(&mask);
1962 else
1963 target = cpumask_any_but(cpu_online_mask, cpu);
1964 if (target < nr_cpu_ids)
1965 arm_cmn_migrate(cmn, target);
1966 return 0;
1967}
1968
1969static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
1970{
1971 struct arm_cmn_dtc *dtc = dev_id;
1972 irqreturn_t ret = IRQ_NONE;
1973
1974 for (;;) {
1975 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
1976 u64 delta;
1977 int i;
1978
1979 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
1980 if (status & (1U << i)) {
1981 ret = IRQ_HANDLED;
1982 if (WARN_ON(!dtc->counters[i]))
1983 continue;
1984 delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
1985 local64_add(delta, &dtc->counters[i]->count);
1986 }
1987 }
1988
1989 if (status & (1U << CMN_DT_NUM_COUNTERS)) {
1990 ret = IRQ_HANDLED;
1991 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
1992 delta = arm_cmn_read_cc(dtc);
1993 local64_add(delta, &dtc->cycles->count);
1994 }
1995 }
1996
1997 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
1998
1999 if (!dtc->irq_friend)
2000 return ret;
2001 dtc += dtc->irq_friend;
2002 }
2003}
2004
2005/* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
2006static int arm_cmn_init_irqs(struct arm_cmn *cmn)
2007{
2008 int i, j, irq, err;
2009
2010 for (i = 0; i < cmn->num_dtcs; i++) {
2011 irq = cmn->dtc[i].irq;
2012 for (j = i; j--; ) {
2013 if (cmn->dtc[j].irq == irq) {
2014 cmn->dtc[j].irq_friend = i - j;
2015 goto next;
2016 }
2017 }
2018 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
2019 IRQF_NOBALANCING | IRQF_NO_THREAD,
2020 dev_name(cmn->dev), &cmn->dtc[i]);
2021 if (err)
2022 return err;
2023
2024 err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
2025 if (err)
2026 return err;
2027 next:
2028 ; /* isn't C great? */
2029 }
2030 return 0;
2031}
2032
2033static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
2034{
2035 int i;
2036
2037 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
2038 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
2039 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2040 for (i = 0; i < 4; i++) {
2041 dtm->wp_event[i] = -1;
2042 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
2043 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
2044 }
2045}
2046
2047static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
2048{
2049 struct arm_cmn_dtc *dtc = cmn->dtc + idx;
2050
2051 dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
2052 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
2053 if (dtc->irq < 0)
2054 return dtc->irq;
2055
2056 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2057 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
2058 writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
2059 writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
2060
2061 return 0;
2062}
2063
2064static int arm_cmn_node_cmp(const void *a, const void *b)
2065{
2066 const struct arm_cmn_node *dna = a, *dnb = b;
2067 int cmp;
2068
2069 cmp = dna->type - dnb->type;
2070 if (!cmp)
2071 cmp = dna->logid - dnb->logid;
2072 return cmp;
2073}
2074
2075static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
2076{
2077 struct arm_cmn_node *dn, *xp;
2078 int dtc_idx = 0;
2079
2080 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
2081 if (!cmn->dtc)
2082 return -ENOMEM;
2083
2084 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
2085
2086 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
2087
2088 if (cmn->part == PART_CMN600 && cmn->num_dtcs > 1) {
2089 /* We do at least know that a DTC's XP must be in that DTC's domain */
2090 dn = arm_cmn_node(cmn, CMN_TYPE_DTC);
2091 for (int i = 0; i < cmn->num_dtcs; i++)
2092 arm_cmn_node_to_xp(cmn, dn + i)->dtc = i;
2093 }
2094
2095 for (dn = cmn->dns; dn->type; dn++) {
2096 if (dn->type == CMN_TYPE_XP)
2097 continue;
2098
2099 xp = arm_cmn_node_to_xp(cmn, dn);
2100 dn->dtc = xp->dtc;
2101 dn->dtm = xp->dtm;
2102 if (cmn->multi_dtm)
2103 dn->dtm += arm_cmn_nid(cmn, dn->id).port / 2;
2104
2105 if (dn->type == CMN_TYPE_DTC) {
2106 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
2107
2108 if (err)
2109 return err;
2110 }
2111
2112 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
2113 if (dn->type == CMN_TYPE_RND)
2114 dn->type = CMN_TYPE_RNI;
2115
2116 /* We split the RN-I off already, so let the CCLA part match CCLA events */
2117 if (dn->type == CMN_TYPE_CCLA_RNI)
2118 dn->type = CMN_TYPE_CCLA;
2119 }
2120
2121 arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
2122
2123 return 0;
2124}
2125
2126static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region)
2127{
2128 int offset = CMN_DTM_UNIT_INFO;
2129
2130 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700)
2131 offset = CMN650_DTM_UNIT_INFO;
2132
2133 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));
2134}
2135
2136static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
2137{
2138 int level;
2139 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2140
2141 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
2142 node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
2143 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
2144
2145 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
2146
2147 if (node->type == CMN_TYPE_CFG)
2148 level = 0;
2149 else if (node->type == CMN_TYPE_XP)
2150 level = 1;
2151 else
2152 level = 2;
2153
2154 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
2155 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
2156 node->type, node->logid, offset);
2157}
2158
2159static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
2160{
2161 switch (type) {
2162 case CMN_TYPE_HNP:
2163 return CMN_TYPE_HNI;
2164 case CMN_TYPE_CCLA_RNI:
2165 return CMN_TYPE_RNI;
2166 default:
2167 return CMN_TYPE_INVALID;
2168 }
2169}
2170
2171static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
2172{
2173 void __iomem *cfg_region;
2174 struct arm_cmn_node cfg, *dn;
2175 struct arm_cmn_dtm *dtm;
2176 enum cmn_part part;
2177 u16 child_count, child_poff;
2178 u32 xp_offset[CMN_MAX_XPS];
2179 u64 reg;
2180 int i, j;
2181 size_t sz;
2182
2183 arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
2184 if (cfg.type != CMN_TYPE_CFG)
2185 return -ENODEV;
2186
2187 cfg_region = cmn->base + rgn_offset;
2188
2189 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
2190 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
2191 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
2192 if (cmn->part && cmn->part != part)
2193 dev_warn(cmn->dev,
2194 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
2195 cmn->part, part);
2196 cmn->part = part;
2197 if (!arm_cmn_model(cmn))
2198 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
2199
2200 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
2201 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
2202
2203 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
2204 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
2205 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
2206 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
2207
2208 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
2209 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
2210 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
2211
2212 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
2213 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2214 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2215
2216 cmn->num_xps = child_count;
2217 cmn->num_dns = cmn->num_xps;
2218
2219 /* Pass 1: visit the XPs, enumerate their children */
2220 for (i = 0; i < cmn->num_xps; i++) {
2221 reg = readq_relaxed(cfg_region + child_poff + i * 8);
2222 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
2223
2224 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2225 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2226 }
2227
2228 /*
2229 * Some nodes effectively have two separate types, which we'll handle
2230 * by creating one of each internally. For a (very) safe initial upper
2231 * bound, account for double the number of non-XP nodes.
2232 */
2233 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
2234 sizeof(*dn), GFP_KERNEL);
2235 if (!dn)
2236 return -ENOMEM;
2237
2238 /* Initial safe upper bound on DTMs for any possible mesh layout */
2239 i = cmn->num_xps;
2240 if (cmn->multi_dtm)
2241 i += cmn->num_xps + 1;
2242 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
2243 if (!dtm)
2244 return -ENOMEM;
2245
2246 /* Pass 2: now we can actually populate the nodes */
2247 cmn->dns = dn;
2248 cmn->dtms = dtm;
2249 for (i = 0; i < cmn->num_xps; i++) {
2250 void __iomem *xp_region = cmn->base + xp_offset[i];
2251 struct arm_cmn_node *xp = dn++;
2252 unsigned int xp_ports = 0;
2253
2254 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
2255 /*
2256 * Thanks to the order in which XP logical IDs seem to be
2257 * assigned, we can handily infer the mesh X dimension by
2258 * looking out for the XP at (0,1) without needing to know
2259 * the exact node ID format, which we can later derive.
2260 */
2261 if (xp->id == (1 << 3))
2262 cmn->mesh_x = xp->logid;
2263
2264 if (cmn->part == PART_CMN600)
2265 xp->dtc = -1;
2266 else
2267 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);
2268
2269 xp->dtm = dtm - cmn->dtms;
2270 arm_cmn_init_dtm(dtm++, xp, 0);
2271 /*
2272 * Keeping track of connected ports will let us filter out
2273 * unnecessary XP events easily. We can also reliably infer the
2274 * "extra device ports" configuration for the node ID format
2275 * from this, since in that case we will see at least one XP
2276 * with port 2 connected, for the HN-D.
2277 */
2278 for (int p = 0; p < CMN_MAX_PORTS; p++)
2279 if (arm_cmn_device_connect_info(cmn, xp, p))
2280 xp_ports |= BIT(p);
2281
2282 if (cmn->multi_dtm && (xp_ports & 0xc))
2283 arm_cmn_init_dtm(dtm++, xp, 1);
2284 if (cmn->multi_dtm && (xp_ports & 0x30))
2285 arm_cmn_init_dtm(dtm++, xp, 2);
2286
2287 cmn->ports_used |= xp_ports;
2288
2289 reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
2290 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2291 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2292
2293 for (j = 0; j < child_count; j++) {
2294 reg = readq_relaxed(xp_region + child_poff + j * 8);
2295 /*
2296 * Don't even try to touch anything external, since in general
2297 * we haven't a clue how to power up arbitrary CHI requesters.
2298 * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
2299 * neither of which have any PMU events anyway.
2300 * (Actually, CXLAs do seem to have grown some events in r1p2,
2301 * but they don't go to regular XP DTMs, and they depend on
2302 * secure configuration which we can't easily deal with)
2303 */
2304 if (reg & CMN_CHILD_NODE_EXTERNAL) {
2305 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2306 continue;
2307 }
2308 /*
2309 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus
2310 * child count larger than the number of valid child pointers.
2311 * A child offset of 0 can only occur on CMN-600; otherwise it
2312 * would imply the root node being its own grandchild, which
2313 * we can safely dismiss in general.
2314 */
2315 if (reg == 0 && cmn->part != PART_CMN600) {
2316 dev_dbg(cmn->dev, "bogus child pointer?\n");
2317 continue;
2318 }
2319
2320 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2321
2322 switch (dn->type) {
2323 case CMN_TYPE_DTC:
2324 cmn->num_dtcs++;
2325 dn++;
2326 break;
2327 /* These guys have PMU events */
2328 case CMN_TYPE_DVM:
2329 case CMN_TYPE_HNI:
2330 case CMN_TYPE_HNF:
2331 case CMN_TYPE_SBSX:
2332 case CMN_TYPE_RNI:
2333 case CMN_TYPE_RND:
2334 case CMN_TYPE_MTSX:
2335 case CMN_TYPE_CXRA:
2336 case CMN_TYPE_CXHA:
2337 case CMN_TYPE_CCRA:
2338 case CMN_TYPE_CCHA:
2339 case CMN_TYPE_CCLA:
2340 case CMN_TYPE_HNS:
2341 dn++;
2342 break;
2343 /* Nothing to see here */
2344 case CMN_TYPE_MPAM_S:
2345 case CMN_TYPE_MPAM_NS:
2346 case CMN_TYPE_RNSAM:
2347 case CMN_TYPE_CXLA:
2348 case CMN_TYPE_HNS_MPAM_S:
2349 case CMN_TYPE_HNS_MPAM_NS:
2350 break;
2351 /*
2352 * Split "optimised" combination nodes into separate
2353 * types for the different event sets. Offsetting the
2354 * base address lets us handle the second pmu_event_sel
2355 * register via the normal mechanism later.
2356 */
2357 case CMN_TYPE_HNP:
2358 case CMN_TYPE_CCLA_RNI:
2359 dn[1] = dn[0];
2360 dn[0].pmu_base += CMN_HNP_PMU_EVENT_SEL;
2361 dn[1].type = arm_cmn_subtype(dn->type);
2362 dn += 2;
2363 break;
2364 /* Something has gone horribly wrong */
2365 default:
2366 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
2367 return -ENODEV;
2368 }
2369 }
2370 }
2371
2372 /* Correct for any nodes we added or skipped */
2373 cmn->num_dns = dn - cmn->dns;
2374
2375 /* Cheeky +1 to help terminate pointer-based iteration later */
2376 sz = (void *)(dn + 1) - (void *)cmn->dns;
2377 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
2378 if (dn)
2379 cmn->dns = dn;
2380
2381 sz = (void *)dtm - (void *)cmn->dtms;
2382 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
2383 if (dtm)
2384 cmn->dtms = dtm;
2385
2386 /*
2387 * If mesh_x wasn't set during discovery then we never saw
2388 * an XP at (0,1), thus we must have an Nx1 configuration.
2389 */
2390 if (!cmn->mesh_x)
2391 cmn->mesh_x = cmn->num_xps;
2392 cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
2393
2394 /* 1x1 config plays havoc with XP event encodings */
2395 if (cmn->num_xps == 1)
2396 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
2397
2398 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
2399 reg = cmn->ports_used;
2400 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
2401 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®,
2402 cmn->multi_dtm ? ", multi-DTM" : "");
2403
2404 return 0;
2405}
2406
2407static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
2408{
2409 struct resource *cfg, *root;
2410
2411 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2412 if (!cfg)
2413 return -EINVAL;
2414
2415 root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2416 if (!root)
2417 return -EINVAL;
2418
2419 if (!resource_contains(cfg, root))
2420 swap(cfg, root);
2421 /*
2422 * Note that devm_ioremap_resource() is dumb and won't let the platform
2423 * device claim cfg when the ACPI companion device has already claimed
2424 * root within it. But since they *are* already both claimed in the
2425 * appropriate name, we don't really need to do it again here anyway.
2426 */
2427 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2428 if (!cmn->base)
2429 return -ENOMEM;
2430
2431 return root->start - cfg->start;
2432}
2433
2434static int arm_cmn600_of_probe(struct device_node *np)
2435{
2436 u32 rootnode;
2437
2438 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
2439}
2440
2441static int arm_cmn_probe(struct platform_device *pdev)
2442{
2443 struct arm_cmn *cmn;
2444 const char *name;
2445 static atomic_t id;
2446 int err, rootnode, this_id;
2447
2448 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
2449 if (!cmn)
2450 return -ENOMEM;
2451
2452 cmn->dev = &pdev->dev;
2453 cmn->part = (unsigned long)device_get_match_data(cmn->dev);
2454 platform_set_drvdata(pdev, cmn);
2455
2456 if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
2457 rootnode = arm_cmn600_acpi_probe(pdev, cmn);
2458 } else {
2459 rootnode = 0;
2460 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2461 if (IS_ERR(cmn->base))
2462 return PTR_ERR(cmn->base);
2463 if (cmn->part == PART_CMN600)
2464 rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
2465 }
2466 if (rootnode < 0)
2467 return rootnode;
2468
2469 err = arm_cmn_discover(cmn, rootnode);
2470 if (err)
2471 return err;
2472
2473 err = arm_cmn_init_dtcs(cmn);
2474 if (err)
2475 return err;
2476
2477 err = arm_cmn_init_irqs(cmn);
2478 if (err)
2479 return err;
2480
2481 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
2482 cmn->pmu = (struct pmu) {
2483 .module = THIS_MODULE,
2484 .attr_groups = arm_cmn_attr_groups,
2485 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
2486 .task_ctx_nr = perf_invalid_context,
2487 .pmu_enable = arm_cmn_pmu_enable,
2488 .pmu_disable = arm_cmn_pmu_disable,
2489 .event_init = arm_cmn_event_init,
2490 .add = arm_cmn_event_add,
2491 .del = arm_cmn_event_del,
2492 .start = arm_cmn_event_start,
2493 .stop = arm_cmn_event_stop,
2494 .read = arm_cmn_event_read,
2495 .start_txn = arm_cmn_start_txn,
2496 .commit_txn = arm_cmn_commit_txn,
2497 .cancel_txn = arm_cmn_end_txn,
2498 };
2499
2500 this_id = atomic_fetch_inc(&id);
2501 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
2502 if (!name)
2503 return -ENOMEM;
2504
2505 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
2506 if (err)
2507 return err;
2508
2509 err = perf_pmu_register(&cmn->pmu, name, -1);
2510 if (err)
2511 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2512 else
2513 arm_cmn_debugfs_init(cmn, this_id);
2514
2515 return err;
2516}
2517
2518static int arm_cmn_remove(struct platform_device *pdev)
2519{
2520 struct arm_cmn *cmn = platform_get_drvdata(pdev);
2521
2522 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
2523
2524 perf_pmu_unregister(&cmn->pmu);
2525 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2526 debugfs_remove(cmn->debug);
2527 return 0;
2528}
2529
2530#ifdef CONFIG_OF
2531static const struct of_device_id arm_cmn_of_match[] = {
2532 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
2533 { .compatible = "arm,cmn-650" },
2534 { .compatible = "arm,cmn-700" },
2535 { .compatible = "arm,ci-700" },
2536 {}
2537};
2538MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
2539#endif
2540
2541#ifdef CONFIG_ACPI
2542static const struct acpi_device_id arm_cmn_acpi_match[] = {
2543 { "ARMHC600", PART_CMN600 },
2544 { "ARMHC650" },
2545 { "ARMHC700" },
2546 {}
2547};
2548MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
2549#endif
2550
2551static struct platform_driver arm_cmn_driver = {
2552 .driver = {
2553 .name = "arm-cmn",
2554 .of_match_table = of_match_ptr(arm_cmn_of_match),
2555 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
2556 },
2557 .probe = arm_cmn_probe,
2558 .remove = arm_cmn_remove,
2559};
2560
2561static int __init arm_cmn_init(void)
2562{
2563 int ret;
2564
2565 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
2566 "perf/arm/cmn:online",
2567 arm_cmn_pmu_online_cpu,
2568 arm_cmn_pmu_offline_cpu);
2569 if (ret < 0)
2570 return ret;
2571
2572 arm_cmn_hp_state = ret;
2573 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
2574
2575 ret = platform_driver_register(&arm_cmn_driver);
2576 if (ret) {
2577 cpuhp_remove_multi_state(arm_cmn_hp_state);
2578 debugfs_remove(arm_cmn_debugfs);
2579 }
2580 return ret;
2581}
2582
2583static void __exit arm_cmn_exit(void)
2584{
2585 platform_driver_unregister(&arm_cmn_driver);
2586 cpuhp_remove_multi_state(arm_cmn_hp_state);
2587 debugfs_remove(arm_cmn_debugfs);
2588}
2589
2590module_init(arm_cmn_init);
2591module_exit(arm_cmn_exit);
2592
2593MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
2594MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
2595MODULE_LICENSE("GPL v2");