1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (C) 2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2020, 2022 Intel Corporation
  5 */
  6#ifndef __iwl_context_info_file_h__
  7#define __iwl_context_info_file_h__
  8
  9/* maximmum number of DRAM map entries supported by FW */
 10#define IWL_MAX_DRAM_ENTRY	64
 11#define CSR_CTXT_INFO_BA	0x40
 12
 13/**
 14 * enum iwl_context_info_flags - Context information control flags
 15 * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
 16 *	the init done for driver command that configures several system modes
 17 * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
 18 * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
 19 * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
 20 *	exponent, the actual size is 2**value, valid sizes are 8-2048.
 21 *	The value is four bits long. Maximum valid exponent is 12
 22 * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
 23 *	default is short format - not supported by the driver)
 24 * @IWL_CTXT_INFO_RB_SIZE: RB size mask
 25 *	(values are IWL_CTXT_INFO_RB_SIZE_*K)
 26 * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
 27 * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
 28 * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
 29 * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
 30 * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
 31 * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
 32 * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
 33 * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
 34 * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
 35 * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
 36 */
 37enum iwl_context_info_flags {
 38	IWL_CTXT_INFO_AUTO_FUNC_INIT	= 0x0001,
 39	IWL_CTXT_INFO_EARLY_DEBUG	= 0x0002,
 40	IWL_CTXT_INFO_ENABLE_CDMP	= 0x0004,
 41	IWL_CTXT_INFO_RB_CB_SIZE	= 0x00f0,
 42	IWL_CTXT_INFO_TFD_FORMAT_LONG	= 0x0100,
 43	IWL_CTXT_INFO_RB_SIZE		= 0x1e00,
 44	IWL_CTXT_INFO_RB_SIZE_1K	= 0x1,
 45	IWL_CTXT_INFO_RB_SIZE_2K	= 0x2,
 46	IWL_CTXT_INFO_RB_SIZE_4K	= 0x4,
 47	IWL_CTXT_INFO_RB_SIZE_8K	= 0x8,
 48	IWL_CTXT_INFO_RB_SIZE_12K	= 0x9,
 49	IWL_CTXT_INFO_RB_SIZE_16K	= 0xa,
 50	IWL_CTXT_INFO_RB_SIZE_20K	= 0xb,
 51	IWL_CTXT_INFO_RB_SIZE_24K	= 0xc,
 52	IWL_CTXT_INFO_RB_SIZE_28K	= 0xd,
 53	IWL_CTXT_INFO_RB_SIZE_32K	= 0xe,
 54};
 55
 56/*
 57 * struct iwl_context_info_version - version structure
 58 * @mac_id: SKU and revision id
 59 * @version: context information version id
 60 * @size: the size of the context information in DWs
 61 */
 62struct iwl_context_info_version {
 63	__le16 mac_id;
 64	__le16 version;
 65	__le16 size;
 66	__le16 reserved;
 67} __packed;
 68
 69/*
 70 * struct iwl_context_info_control - version structure
 71 * @control_flags: context information flags see &enum iwl_context_info_flags
 72 */
 73struct iwl_context_info_control {
 74	__le32 control_flags;
 75	__le32 reserved;
 76} __packed;
 77
 78/*
 79 * struct iwl_context_info_dram - images DRAM map
 80 * each entry in the map represents a DRAM chunk of up to 32 KB
 81 * @umac_img: UMAC image DRAM map
 82 * @lmac_img: LMAC image DRAM map
 83 * @virtual_img: paged image DRAM map
 84 */
 85struct iwl_context_info_dram {
 86	__le64 umac_img[IWL_MAX_DRAM_ENTRY];
 87	__le64 lmac_img[IWL_MAX_DRAM_ENTRY];
 88	__le64 virtual_img[IWL_MAX_DRAM_ENTRY];
 89} __packed;
 90
 91/*
 92 * struct iwl_context_info_rbd_cfg - RBDs configuration
 93 * @free_rbd_addr: default queue free RB CB base address
 94 * @used_rbd_addr: default queue used RB CB base address
 95 * @status_wr_ptr: default queue used RB status write pointer
 96 */
 97struct iwl_context_info_rbd_cfg {
 98	__le64 free_rbd_addr;
 99	__le64 used_rbd_addr;
100	__le64 status_wr_ptr;
101} __packed;
102
103/*
104 * struct iwl_context_info_hcmd_cfg  - command queue configuration
105 * @cmd_queue_addr: address of command queue
106 * @cmd_queue_size: number of entries
107 */
108struct iwl_context_info_hcmd_cfg {
109	__le64 cmd_queue_addr;
110	u8 cmd_queue_size;
111	u8 reserved[7];
112} __packed;
113
114/*
115 * struct iwl_context_info_dump_cfg - Core Dump configuration
116 * @core_dump_addr: core dump (debug DRAM address) start address
117 * @core_dump_size: size, in DWs
118 */
119struct iwl_context_info_dump_cfg {
120	__le64 core_dump_addr;
121	__le32 core_dump_size;
122	__le32 reserved;
123} __packed;
124
125/*
126 * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
127 * @platform_nvm_addr: Platform NVM data start address
128 * @platform_nvm_size: size in DWs
129 */
130struct iwl_context_info_pnvm_cfg {
131	__le64 platform_nvm_addr;
132	__le32 platform_nvm_size;
133	__le32 reserved;
134} __packed;
135
136/*
137 * struct iwl_context_info_early_dbg_cfg - early debug configuration for
138 *	dumping DRAM addresses
139 * @early_debug_addr: early debug start address
140 * @early_debug_size: size in DWs
141 */
142struct iwl_context_info_early_dbg_cfg {
143	__le64 early_debug_addr;
144	__le32 early_debug_size;
145	__le32 reserved;
146} __packed;
147
148/*
149 * struct iwl_context_info - device INIT configuration
150 * @version: version information of context info and HW
151 * @control: control flags of FH configurations
152 * @rbd_cfg: default RX queue configuration
153 * @hcmd_cfg: command queue configuration
154 * @dump_cfg: core dump data
155 * @edbg_cfg: early debug configuration
156 * @pnvm_cfg: platform nvm configuration
157 * @dram: firmware image addresses in DRAM
158 */
159struct iwl_context_info {
160	struct iwl_context_info_version version;
161	struct iwl_context_info_control control;
162	__le64 reserved0;
163	struct iwl_context_info_rbd_cfg rbd_cfg;
164	struct iwl_context_info_hcmd_cfg hcmd_cfg;
165	__le32 reserved1[4];
166	struct iwl_context_info_dump_cfg dump_cfg;
167	struct iwl_context_info_early_dbg_cfg edbg_cfg;
168	struct iwl_context_info_pnvm_cfg pnvm_cfg;
169	__le32 reserved2[16];
170	struct iwl_context_info_dram dram;
171	__le32 reserved3[16];
172} __packed;
173
174int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
175void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
176void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
177int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
178			 const struct fw_img *fw,
179			 struct iwl_context_info_dram *ctxt_dram);
180void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
181					    size_t size,
182					    dma_addr_t *phys);
183int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
184				 const void *data, u32 len,
185				 struct iwl_dram_data *dram);
186
187#endif /* __iwl_context_info_file_h__ */