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1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22/****************************\
23 Reset function and helpers
24\****************************/
25
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28#include <asm/unaligned.h>
29
30#include <linux/pci.h> /* To determine if a card is pci-e */
31#include <linux/log2.h>
32#include <linux/platform_device.h>
33#include "ath5k.h"
34#include "reg.h"
35#include "debug.h"
36
37
38/**
39 * DOC: Reset function and helpers
40 *
41 * Here we implement the main reset routine, used to bring the card
42 * to a working state and ready to receive. We also handle routines
43 * that don't fit on other places such as clock, sleep and power control
44 */
45
46
47/******************\
48* Helper functions *
49\******************/
50
51/**
52 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
53 * @ah: The &struct ath5k_hw
54 * @reg: The register to read
55 * @flag: The flag/field to check on the register
56 * @val: The field value we expect (if we check a field)
57 * @is_set: Instead of checking if the flag got cleared, check if it got set
58 *
59 * Some registers contain flags that indicate that an operation is
60 * running. We use this function to poll these registers and check
61 * if these flags get cleared. We also use it to poll a register
62 * field (containing multiple flags) until it gets a specific value.
63 *
64 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
65 */
66int
67ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
68 bool is_set)
69{
70 int i;
71 u32 data;
72
73 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
74 data = ath5k_hw_reg_read(ah, reg);
75 if (is_set && (data & flag))
76 break;
77 else if ((data & flag) == val)
78 break;
79 udelay(15);
80 }
81
82 return (i <= 0) ? -EAGAIN : 0;
83}
84
85
86/*************************\
87* Clock related functions *
88\*************************/
89
90/**
91 * ath5k_hw_htoclock() - Translate usec to hw clock units
92 * @ah: The &struct ath5k_hw
93 * @usec: value in microseconds
94 *
95 * Translate usecs to hw clock units based on the current
96 * hw clock rate.
97 *
98 * Returns number of clock units
99 */
100unsigned int
101ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
102{
103 struct ath_common *common = ath5k_hw_common(ah);
104 return usec * common->clockrate;
105}
106
107/**
108 * ath5k_hw_clocktoh() - Translate hw clock units to usec
109 * @ah: The &struct ath5k_hw
110 * @clock: value in hw clock units
111 *
112 * Translate hw clock units to usecs based on the current
113 * hw clock rate.
114 *
115 * Returns number of usecs
116 */
117unsigned int
118ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
119{
120 struct ath_common *common = ath5k_hw_common(ah);
121 return clock / common->clockrate;
122}
123
124/**
125 * ath5k_hw_init_core_clock() - Initialize core clock
126 * @ah: The &struct ath5k_hw
127 *
128 * Initialize core clock parameters (usec, usec32, latencies etc),
129 * based on current bwmode and chipset properties.
130 */
131static void
132ath5k_hw_init_core_clock(struct ath5k_hw *ah)
133{
134 struct ieee80211_channel *channel = ah->ah_current_channel;
135 struct ath_common *common = ath5k_hw_common(ah);
136 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
137
138 /*
139 * Set core clock frequency
140 */
141 switch (channel->hw_value) {
142 case AR5K_MODE_11A:
143 clock = 40;
144 break;
145 case AR5K_MODE_11B:
146 clock = 22;
147 break;
148 case AR5K_MODE_11G:
149 default:
150 clock = 44;
151 break;
152 }
153
154 /* Use clock multiplier for non-default
155 * bwmode */
156 switch (ah->ah_bwmode) {
157 case AR5K_BWMODE_40MHZ:
158 clock *= 2;
159 break;
160 case AR5K_BWMODE_10MHZ:
161 clock /= 2;
162 break;
163 case AR5K_BWMODE_5MHZ:
164 clock /= 4;
165 break;
166 default:
167 break;
168 }
169
170 common->clockrate = clock;
171
172 /*
173 * Set USEC parameters
174 */
175 /* Set USEC counter on PCU*/
176 usec = clock - 1;
177 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
178
179 /* Set usec duration on DCU */
180 if (ah->ah_version != AR5K_AR5210)
181 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
182 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
183 clock);
184
185 /* Set 32MHz USEC counter */
186 if ((ah->ah_radio == AR5K_RF5112) ||
187 (ah->ah_radio == AR5K_RF2413) ||
188 (ah->ah_radio == AR5K_RF5413) ||
189 (ah->ah_radio == AR5K_RF2316) ||
190 (ah->ah_radio == AR5K_RF2317))
191 /* Remain on 40MHz clock ? */
192 sclock = 40 - 1;
193 else
194 sclock = 32 - 1;
195 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
196
197 /*
198 * Set tx/rx latencies
199 */
200 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
201 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
202 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
203
204 /*
205 * Set default Tx frame to Tx data start delay
206 */
207 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
208
209 /*
210 * 5210 initvals don't include usec settings
211 * so we need to use magic values here for
212 * tx/rx latencies
213 */
214 if (ah->ah_version == AR5K_AR5210) {
215 /* same for turbo */
216 txlat = AR5K_INIT_TX_LATENCY_5210;
217 rxlat = AR5K_INIT_RX_LATENCY_5210;
218 }
219
220 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
221 /* 5311 has different tx/rx latency masks
222 * from 5211, since we deal 5311 the same
223 * as 5211 when setting initvals, shift
224 * values here to their proper locations
225 *
226 * Note: Initvals indicate tx/rx/ latencies
227 * are the same for turbo mode */
228 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
229 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
230 } else
231 switch (ah->ah_bwmode) {
232 case AR5K_BWMODE_10MHZ:
233 txlat = AR5K_REG_SM(txlat * 2,
234 AR5K_USEC_TX_LATENCY_5211);
235 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
236 AR5K_USEC_RX_LATENCY_5211);
237 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
238 break;
239 case AR5K_BWMODE_5MHZ:
240 txlat = AR5K_REG_SM(txlat * 4,
241 AR5K_USEC_TX_LATENCY_5211);
242 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
243 AR5K_USEC_RX_LATENCY_5211);
244 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
245 break;
246 case AR5K_BWMODE_40MHZ:
247 txlat = AR5K_INIT_TX_LAT_MIN;
248 rxlat = AR5K_REG_SM(rxlat / 2,
249 AR5K_USEC_RX_LATENCY_5211);
250 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
251 break;
252 default:
253 break;
254 }
255
256 usec_reg = (usec | sclock | txlat | rxlat);
257 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
258
259 /* On 5112 set tx frame to tx data start delay */
260 if (ah->ah_radio == AR5K_RF5112) {
261 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
262 AR5K_PHY_RF_CTL2_TXF2TXD_START,
263 txf2txs);
264 }
265}
266
267/**
268 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
269 * @ah: The &struct ath5k_hw
270 * @enable: Enable sleep clock operation (false to disable)
271 *
272 * If there is an external 32KHz crystal available, use it
273 * as ref. clock instead of 32/40MHz clock and baseband clocks
274 * to save power during sleep or restore normal 32/40MHz
275 * operation.
276 *
277 * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
278 * 123 - 127) require delay on access.
279 */
280static void
281ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
282{
283 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
284 u32 scal, spending, sclock;
285
286 /* Only set 32KHz settings if we have an external
287 * 32KHz crystal present */
288 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
289 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
290 enable) {
291
292 /* 1 usec/cycle */
293 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
294 /* Set up tsf increment on each cycle */
295 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
296
297 /* Set baseband sleep control registers
298 * and sleep control rate */
299 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
300
301 if ((ah->ah_radio == AR5K_RF5112) ||
302 (ah->ah_radio == AR5K_RF5413) ||
303 (ah->ah_radio == AR5K_RF2316) ||
304 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
305 spending = 0x14;
306 else
307 spending = 0x18;
308 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
309
310 if ((ah->ah_radio == AR5K_RF5112) ||
311 (ah->ah_radio == AR5K_RF5413) ||
312 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
314 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
315 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
316 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
317 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
318 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
319 } else {
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
321 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
322 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
323 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
324 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
325 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
326 }
327
328 /* Enable sleep clock operation */
329 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
330 AR5K_PCICFG_SLEEP_CLOCK_EN);
331
332 } else {
333
334 /* Disable sleep clock operation and
335 * restore default parameters */
336 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
337 AR5K_PCICFG_SLEEP_CLOCK_EN);
338
339 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
340 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
341
342 /* Set DAC/ADC delays */
343 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
345
346 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
347 scal = AR5K_PHY_SCAL_32MHZ_2417;
348 else if (ee->ee_is_hb63)
349 scal = AR5K_PHY_SCAL_32MHZ_HB63;
350 else
351 scal = AR5K_PHY_SCAL_32MHZ;
352 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
353
354 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
355 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
356
357 if ((ah->ah_radio == AR5K_RF5112) ||
358 (ah->ah_radio == AR5K_RF5413) ||
359 (ah->ah_radio == AR5K_RF2316) ||
360 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
361 spending = 0x14;
362 else
363 spending = 0x18;
364 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
365
366 /* Set up tsf increment on each cycle */
367 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
368
369 if ((ah->ah_radio == AR5K_RF5112) ||
370 (ah->ah_radio == AR5K_RF5413) ||
371 (ah->ah_radio == AR5K_RF2316) ||
372 (ah->ah_radio == AR5K_RF2317))
373 sclock = 40 - 1;
374 else
375 sclock = 32 - 1;
376 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
377 }
378}
379
380
381/*********************\
382* Reset/Sleep control *
383\*********************/
384
385/**
386 * ath5k_hw_nic_reset() - Reset the various chipset units
387 * @ah: The &struct ath5k_hw
388 * @val: Mask to indicate what units to reset
389 *
390 * To reset the various chipset units we need to write
391 * the mask to AR5K_RESET_CTL and poll the register until
392 * all flags are cleared.
393 *
394 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
395 */
396static int
397ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
398{
399 int ret;
400 u32 mask = val ? val : ~0U;
401
402 /* Read-and-clear RX Descriptor Pointer*/
403 ath5k_hw_reg_read(ah, AR5K_RXDP);
404
405 /*
406 * Reset the device and wait until success
407 */
408 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
409
410 /* Wait at least 128 PCI clocks */
411 usleep_range(15, 20);
412
413 if (ah->ah_version == AR5K_AR5210) {
414 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
415 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
416 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
417 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
418 } else {
419 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
420 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
421 }
422
423 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
424
425 /*
426 * Reset configuration register (for hw byte-swap). Note that this
427 * is only set for big endian. We do the necessary magic in
428 * AR5K_INIT_CFG.
429 */
430 if ((val & AR5K_RESET_CTL_PCU) == 0)
431 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
432
433 return ret;
434}
435
436/**
437 * ath5k_hw_wisoc_reset() - Reset AHB chipset
438 * @ah: The &struct ath5k_hw
439 * @flags: Mask to indicate what units to reset
440 *
441 * Same as ath5k_hw_nic_reset but for AHB based devices
442 *
443 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
444 */
445static int
446ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
447{
448 u32 mask = flags ? flags : ~0U;
449 u32 __iomem *reg;
450 u32 regval;
451 u32 val = 0;
452
453 /* ah->ah_mac_srev is not available at this point yet */
454 if (ah->devid >= AR5K_SREV_AR2315_R6) {
455 reg = (u32 __iomem *) AR5K_AR2315_RESET;
456 if (mask & AR5K_RESET_CTL_PCU)
457 val |= AR5K_AR2315_RESET_WMAC;
458 if (mask & AR5K_RESET_CTL_BASEBAND)
459 val |= AR5K_AR2315_RESET_BB_WARM;
460 } else {
461 reg = (u32 __iomem *) AR5K_AR5312_RESET;
462 if (to_platform_device(ah->dev)->id == 0) {
463 if (mask & AR5K_RESET_CTL_PCU)
464 val |= AR5K_AR5312_RESET_WMAC0;
465 if (mask & AR5K_RESET_CTL_BASEBAND)
466 val |= AR5K_AR5312_RESET_BB0_COLD |
467 AR5K_AR5312_RESET_BB0_WARM;
468 } else {
469 if (mask & AR5K_RESET_CTL_PCU)
470 val |= AR5K_AR5312_RESET_WMAC1;
471 if (mask & AR5K_RESET_CTL_BASEBAND)
472 val |= AR5K_AR5312_RESET_BB1_COLD |
473 AR5K_AR5312_RESET_BB1_WARM;
474 }
475 }
476
477 /* Put BB/MAC into reset */
478 regval = ioread32(reg);
479 iowrite32(regval | val, reg);
480 regval = ioread32(reg);
481 udelay(100); /* NB: should be atomic */
482
483 /* Bring BB/MAC out of reset */
484 iowrite32(regval & ~val, reg);
485 regval = ioread32(reg);
486
487 /*
488 * Reset configuration register (for hw byte-swap). Note that this
489 * is only set for big endian. We do the necessary magic in
490 * AR5K_INIT_CFG.
491 */
492 if ((flags & AR5K_RESET_CTL_PCU) == 0)
493 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
494
495 return 0;
496}
497
498/**
499 * ath5k_hw_set_power_mode() - Set power mode
500 * @ah: The &struct ath5k_hw
501 * @mode: One of enum ath5k_power_mode
502 * @set_chip: Set to true to write sleep control register
503 * @sleep_duration: How much time the device is allowed to sleep
504 * when sleep logic is enabled (in 128 microsecond increments).
505 *
506 * This function is used to configure sleep policy and allowed
507 * sleep modes. For more information check out the sleep control
508 * register on reg.h and STA_ID1.
509 *
510 * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
511 * mode is requested.
512 */
513static int
514ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
515 bool set_chip, u16 sleep_duration)
516{
517 unsigned int i;
518 u32 staid, data;
519
520 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
521
522 switch (mode) {
523 case AR5K_PM_AUTO:
524 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
525 fallthrough;
526 case AR5K_PM_NETWORK_SLEEP:
527 if (set_chip)
528 ath5k_hw_reg_write(ah,
529 AR5K_SLEEP_CTL_SLE_ALLOW |
530 sleep_duration,
531 AR5K_SLEEP_CTL);
532
533 staid |= AR5K_STA_ID1_PWR_SV;
534 break;
535
536 case AR5K_PM_FULL_SLEEP:
537 if (set_chip)
538 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
539 AR5K_SLEEP_CTL);
540
541 staid |= AR5K_STA_ID1_PWR_SV;
542 break;
543
544 case AR5K_PM_AWAKE:
545
546 staid &= ~AR5K_STA_ID1_PWR_SV;
547
548 if (!set_chip)
549 goto commit;
550
551 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
552
553 /* If card is down we 'll get 0xffff... so we
554 * need to clean this up before we write the register
555 */
556 if (data & 0xffc00000)
557 data = 0;
558 else
559 /* Preserve sleep duration etc */
560 data = data & ~AR5K_SLEEP_CTL_SLE;
561
562 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
563 AR5K_SLEEP_CTL);
564 usleep_range(15, 20);
565
566 for (i = 200; i > 0; i--) {
567 /* Check if the chip did wake up */
568 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
569 AR5K_PCICFG_SPWR_DN) == 0)
570 break;
571
572 /* Wait a bit and retry */
573 usleep_range(50, 75);
574 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
575 AR5K_SLEEP_CTL);
576 }
577
578 /* Fail if the chip didn't wake up */
579 if (i == 0)
580 return -EIO;
581
582 break;
583
584 default:
585 return -EINVAL;
586 }
587
588commit:
589 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
590
591 return 0;
592}
593
594/**
595 * ath5k_hw_on_hold() - Put device on hold
596 * @ah: The &struct ath5k_hw
597 *
598 * Put MAC and Baseband on warm reset and keep that state
599 * (don't clean sleep control register). After this MAC
600 * and Baseband are disabled and a full reset is needed
601 * to come back. This way we save as much power as possible
602 * without putting the card on full sleep.
603 *
604 * Returns 0 on success or -EIO on error
605 */
606int
607ath5k_hw_on_hold(struct ath5k_hw *ah)
608{
609 struct pci_dev *pdev = ah->pdev;
610 u32 bus_flags;
611 int ret;
612
613 if (ath5k_get_bus_type(ah) == ATH_AHB)
614 return 0;
615
616 /* Make sure device is awake */
617 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
618 if (ret) {
619 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
620 return ret;
621 }
622
623 /*
624 * Put chipset on warm reset...
625 *
626 * Note: putting PCI core on warm reset on PCI-E cards
627 * results card to hang and always return 0xffff... so
628 * we ignore that flag for PCI-E cards. On PCI cards
629 * this flag gets cleared after 64 PCI clocks.
630 */
631 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
632
633 if (ah->ah_version == AR5K_AR5210) {
634 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
635 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
636 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
637 usleep_range(2000, 2500);
638 } else {
639 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
640 AR5K_RESET_CTL_BASEBAND | bus_flags);
641 }
642
643 if (ret) {
644 ATH5K_ERR(ah, "failed to put device on warm reset\n");
645 return -EIO;
646 }
647
648 /* ...wakeup again!*/
649 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
650 if (ret) {
651 ATH5K_ERR(ah, "failed to put device on hold\n");
652 return ret;
653 }
654
655 return ret;
656}
657
658/**
659 * ath5k_hw_nic_wakeup() - Force card out of sleep
660 * @ah: The &struct ath5k_hw
661 * @channel: The &struct ieee80211_channel
662 *
663 * Bring up MAC + PHY Chips and program PLL
664 * NOTE: Channel is NULL for the initial wakeup.
665 *
666 * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
667 */
668int
669ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
670{
671 struct pci_dev *pdev = ah->pdev;
672 u32 turbo, mode, clock, bus_flags;
673 int ret;
674
675 turbo = 0;
676 mode = 0;
677 clock = 0;
678
679 if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
680 /* Wakeup the device */
681 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
682 if (ret) {
683 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
684 return ret;
685 }
686 }
687
688 /*
689 * Put chipset on warm reset...
690 *
691 * Note: putting PCI core on warm reset on PCI-E cards
692 * results card to hang and always return 0xffff... so
693 * we ignore that flag for PCI-E cards. On PCI cards
694 * this flag gets cleared after 64 PCI clocks.
695 */
696 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
697
698 if (ah->ah_version == AR5K_AR5210) {
699 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
700 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
701 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
702 usleep_range(2000, 2500);
703 } else {
704 if (ath5k_get_bus_type(ah) == ATH_AHB)
705 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
706 AR5K_RESET_CTL_BASEBAND);
707 else
708 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
709 AR5K_RESET_CTL_BASEBAND | bus_flags);
710 }
711
712 if (ret) {
713 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
714 return -EIO;
715 }
716
717 /* ...wakeup again!...*/
718 ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
719 if (ret) {
720 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
721 return ret;
722 }
723
724 /* ...reset configuration register on Wisoc ...
725 * ...clear reset control register and pull device out of
726 * warm reset on others */
727 if (ath5k_get_bus_type(ah) == ATH_AHB)
728 ret = ath5k_hw_wisoc_reset(ah, 0);
729 else
730 ret = ath5k_hw_nic_reset(ah, 0);
731
732 if (ret) {
733 ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
734 return -EIO;
735 }
736
737 /* On initialization skip PLL programming since we don't have
738 * a channel / mode set yet */
739 if (!channel)
740 return 0;
741
742 if (ah->ah_version != AR5K_AR5210) {
743 /*
744 * Get channel mode flags
745 */
746
747 if (ah->ah_radio >= AR5K_RF5112) {
748 mode = AR5K_PHY_MODE_RAD_RF5112;
749 clock = AR5K_PHY_PLL_RF5112;
750 } else {
751 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
752 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
753 }
754
755 if (channel->band == NL80211_BAND_2GHZ) {
756 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
757 clock |= AR5K_PHY_PLL_44MHZ;
758
759 if (channel->hw_value == AR5K_MODE_11B) {
760 mode |= AR5K_PHY_MODE_MOD_CCK;
761 } else {
762 /* XXX Dynamic OFDM/CCK is not supported by the
763 * AR5211 so we set MOD_OFDM for plain g (no
764 * CCK headers) operation. We need to test
765 * this, 5211 might support ofdm-only g after
766 * all, there are also initial register values
767 * in the code for g mode (see initvals.c).
768 */
769 if (ah->ah_version == AR5K_AR5211)
770 mode |= AR5K_PHY_MODE_MOD_OFDM;
771 else
772 mode |= AR5K_PHY_MODE_MOD_DYN;
773 }
774 } else if (channel->band == NL80211_BAND_5GHZ) {
775 mode |= (AR5K_PHY_MODE_FREQ_5GHZ |
776 AR5K_PHY_MODE_MOD_OFDM);
777
778 /* Different PLL setting for 5413 */
779 if (ah->ah_radio == AR5K_RF5413)
780 clock = AR5K_PHY_PLL_40MHZ_5413;
781 else
782 clock |= AR5K_PHY_PLL_40MHZ;
783 } else {
784 ATH5K_ERR(ah, "invalid radio frequency mode\n");
785 return -EINVAL;
786 }
787
788 /*XXX: Can bwmode be used with dynamic mode ?
789 * (I don't think it supports 44MHz) */
790 /* On 2425 initvals TURBO_SHORT is not present */
791 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
792 turbo = AR5K_PHY_TURBO_MODE;
793 if (ah->ah_radio != AR5K_RF2425)
794 turbo |= AR5K_PHY_TURBO_SHORT;
795 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
796 if (ah->ah_radio == AR5K_RF5413) {
797 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
798 AR5K_PHY_MODE_HALF_RATE :
799 AR5K_PHY_MODE_QUARTER_RATE;
800 } else if (ah->ah_version == AR5K_AR5212) {
801 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
802 AR5K_PHY_PLL_HALF_RATE :
803 AR5K_PHY_PLL_QUARTER_RATE;
804 }
805 }
806
807 } else { /* Reset the device */
808
809 /* ...enable Atheros turbo mode if requested */
810 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
811 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
812 AR5K_PHY_TURBO);
813 }
814
815 if (ah->ah_version != AR5K_AR5210) {
816
817 /* ...update PLL if needed */
818 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
819 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
820 usleep_range(300, 350);
821 }
822
823 /* ...set the PHY operating mode */
824 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
825 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
826 }
827
828 return 0;
829}
830
831
832/**************************************\
833* Post-initvals register modifications *
834\**************************************/
835
836/**
837 * ath5k_hw_tweak_initval_settings() - Tweak initial settings
838 * @ah: The &struct ath5k_hw
839 * @channel: The &struct ieee80211_channel
840 *
841 * Some settings are not handled on initvals, e.g. bwmode
842 * settings, some phy settings, workarounds etc that in general
843 * don't fit anywhere else or are too small to introduce a separate
844 * function for each one. So we have this function to handle
845 * them all during reset and complete card's initialization.
846 */
847static void
848ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
849 struct ieee80211_channel *channel)
850{
851 if (ah->ah_version == AR5K_AR5212 &&
852 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
853
854 /* Setup ADC control */
855 ath5k_hw_reg_write(ah,
856 (AR5K_REG_SM(2,
857 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
858 AR5K_REG_SM(2,
859 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
860 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
861 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
862 AR5K_PHY_ADC_CTL);
863
864
865
866 /* Disable barker RSSI threshold */
867 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
868 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
869
870 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
871 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
872
873 /* Set the mute mask */
874 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
875 }
876
877 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
878 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
879 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
880
881 /* Enable DCU double buffering */
882 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
883 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
884 AR5K_TXCFG_DCU_DBL_BUF_DIS);
885
886 /* Set fast ADC */
887 if ((ah->ah_radio == AR5K_RF5413) ||
888 (ah->ah_radio == AR5K_RF2317) ||
889 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
890 u32 fast_adc = true;
891
892 if (channel->center_freq == 2462 ||
893 channel->center_freq == 2467)
894 fast_adc = 0;
895
896 /* Only update if needed */
897 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
898 ath5k_hw_reg_write(ah, fast_adc,
899 AR5K_PHY_FAST_ADC);
900 }
901
902 /* Fix for first revision of the RF5112 RF chipset */
903 if (ah->ah_radio == AR5K_RF5112 &&
904 ah->ah_radio_5ghz_revision <
905 AR5K_SREV_RAD_5112A) {
906 u32 data;
907 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
908 AR5K_PHY_CCKTXCTL);
909 if (channel->band == NL80211_BAND_5GHZ)
910 data = 0xffb81020;
911 else
912 data = 0xffb80d20;
913 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
914 }
915
916 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
917 /* Clear QCU/DCU clock gating register */
918 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
919 /* Set DAC/ADC delays */
920 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
921 AR5K_PHY_SCAL);
922 /* Enable PCU FIFO corruption ECO */
923 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
924 AR5K_DIAG_SW_ECO_ENABLE);
925 }
926
927 if (ah->ah_bwmode) {
928 /* Increase PHY switch and AGC settling time
929 * on turbo mode (ath5k_hw_commit_eeprom_settings
930 * will override settling time if available) */
931 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
932
933 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
934 AR5K_PHY_SETTLING_AGC,
935 AR5K_AGC_SETTLING_TURBO);
936
937 /* XXX: Initvals indicate we only increase
938 * switch time on AR5212, 5211 and 5210
939 * only change agc time (bug?) */
940 if (ah->ah_version == AR5K_AR5212)
941 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
942 AR5K_PHY_SETTLING_SWITCH,
943 AR5K_SWITCH_SETTLING_TURBO);
944
945 if (ah->ah_version == AR5K_AR5210) {
946 /* Set Frame Control Register */
947 ath5k_hw_reg_write(ah,
948 (AR5K_PHY_FRAME_CTL_INI |
949 AR5K_PHY_TURBO_MODE |
950 AR5K_PHY_TURBO_SHORT | 0x2020),
951 AR5K_PHY_FRAME_CTL_5210);
952 }
953 /* On 5413 PHY force window length for half/quarter rate*/
954 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
955 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
956 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
957 AR5K_PHY_FRAME_CTL_WIN_LEN,
958 3);
959 }
960 } else if (ah->ah_version == AR5K_AR5210) {
961 /* Set Frame Control Register for normal operation */
962 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
963 AR5K_PHY_FRAME_CTL_5210);
964 }
965}
966
967/**
968 * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
969 * @ah: The &struct ath5k_hw
970 * @channel: The &struct ieee80211_channel
971 *
972 * Use settings stored on EEPROM to properly initialize the card
973 * based on various infos and per-mode calibration data.
974 */
975static void
976ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
977 struct ieee80211_channel *channel)
978{
979 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
980 s16 cck_ofdm_pwr_delta;
981 u8 ee_mode;
982
983 /* TODO: Add support for AR5210 EEPROM */
984 if (ah->ah_version == AR5K_AR5210)
985 return;
986
987 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);
988
989 /* Adjust power delta for channel 14 */
990 if (channel->center_freq == 2484)
991 cck_ofdm_pwr_delta =
992 ((ee->ee_cck_ofdm_power_delta -
993 ee->ee_scaled_cck_delta) * 2) / 10;
994 else
995 cck_ofdm_pwr_delta =
996 (ee->ee_cck_ofdm_power_delta * 2) / 10;
997
998 /* Set CCK to OFDM power delta on tx power
999 * adjustment register */
1000 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
1001 if (channel->hw_value == AR5K_MODE_11G)
1002 ath5k_hw_reg_write(ah,
1003 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
1004 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
1005 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
1006 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
1007 AR5K_PHY_TX_PWR_ADJ);
1008 else
1009 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
1010 } else {
1011 /* For older revs we scale power on sw during tx power
1012 * setup */
1013 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
1014 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
1015 ee->ee_cck_ofdm_gain_delta;
1016 }
1017
1018 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
1019 * too */
1020 ath5k_hw_set_antenna_switch(ah, ee_mode);
1021
1022 /* Noise floor threshold */
1023 ath5k_hw_reg_write(ah,
1024 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
1025 AR5K_PHY_NFTHRES);
1026
1027 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
1028 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
1029 /* Switch settling time (Turbo) */
1030 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1031 AR5K_PHY_SETTLING_SWITCH,
1032 ee->ee_switch_settling_turbo[ee_mode]);
1033
1034 /* Tx/Rx attenuation (Turbo) */
1035 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1036 AR5K_PHY_GAIN_TXRX_ATTEN,
1037 ee->ee_atn_tx_rx_turbo[ee_mode]);
1038
1039 /* ADC/PGA desired size (Turbo) */
1040 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1041 AR5K_PHY_DESIRED_SIZE_ADC,
1042 ee->ee_adc_desired_size_turbo[ee_mode]);
1043
1044 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1045 AR5K_PHY_DESIRED_SIZE_PGA,
1046 ee->ee_pga_desired_size_turbo[ee_mode]);
1047
1048 /* Tx/Rx margin (Turbo) */
1049 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1050 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1051 ee->ee_margin_tx_rx_turbo[ee_mode]);
1052
1053 } else {
1054 /* Switch settling time */
1055 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1056 AR5K_PHY_SETTLING_SWITCH,
1057 ee->ee_switch_settling[ee_mode]);
1058
1059 /* Tx/Rx attenuation */
1060 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1061 AR5K_PHY_GAIN_TXRX_ATTEN,
1062 ee->ee_atn_tx_rx[ee_mode]);
1063
1064 /* ADC/PGA desired size */
1065 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1066 AR5K_PHY_DESIRED_SIZE_ADC,
1067 ee->ee_adc_desired_size[ee_mode]);
1068
1069 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1070 AR5K_PHY_DESIRED_SIZE_PGA,
1071 ee->ee_pga_desired_size[ee_mode]);
1072
1073 /* Tx/Rx margin */
1074 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1075 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1076 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1077 ee->ee_margin_tx_rx[ee_mode]);
1078 }
1079
1080 /* XPA delays */
1081 ath5k_hw_reg_write(ah,
1082 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
1083 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
1084 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
1085 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
1086
1087 /* XLNA delay */
1088 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
1089 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
1090 ee->ee_tx_end2xlna_enable[ee_mode]);
1091
1092 /* Thresh64 (ANI) */
1093 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
1094 AR5K_PHY_NF_THRESH62,
1095 ee->ee_thr_62[ee_mode]);
1096
1097 /* False detect backoff for channels
1098 * that have spur noise. Write the new
1099 * cyclic power RSSI threshold. */
1100 if (ath5k_hw_chan_has_spur_noise(ah, channel))
1101 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1102 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1103 AR5K_INIT_CYCRSSI_THR1 +
1104 ee->ee_false_detect[ee_mode]);
1105 else
1106 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1107 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1108 AR5K_INIT_CYCRSSI_THR1);
1109
1110 /* I/Q correction (set enable bit last to match HAL sources) */
1111 /* TODO: Per channel i/q infos ? */
1112 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1114 ee->ee_i_cal[ee_mode]);
1115 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1116 ee->ee_q_cal[ee_mode]);
1117 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1118 }
1119
1120 /* Heavy clipping -disable for now */
1121 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1122 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1123}
1124
1125
1126/*********************\
1127* Main reset function *
1128\*********************/
1129
1130/**
1131 * ath5k_hw_reset() - The main reset function
1132 * @ah: The &struct ath5k_hw
1133 * @op_mode: One of enum nl80211_iftype
1134 * @channel: The &struct ieee80211_channel
1135 * @fast: Enable fast channel switching
1136 * @skip_pcu: Skip pcu initialization
1137 *
1138 * This is the function we call each time we want to (re)initialize the
1139 * card and pass new settings to hw. We also call it when hw runs into
1140 * trouble to make it come back to a working state.
1141 *
1142 * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1143 * on failure.
1144 */
1145int
1146ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1147 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1148{
1149 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1150 u8 mode;
1151 int i, ret;
1152
1153 tsf_up = 0;
1154 tsf_lo = 0;
1155 mode = 0;
1156
1157 /*
1158 * Sanity check for fast flag
1159 * Fast channel change only available
1160 * on AR2413/AR5413.
1161 */
1162 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1163 (ah->ah_radio != AR5K_RF5413))
1164 fast = false;
1165
1166 /* Disable sleep clock operation
1167 * to avoid register access delay on certain
1168 * PHY registers */
1169 if (ah->ah_version == AR5K_AR5212)
1170 ath5k_hw_set_sleep_clock(ah, false);
1171
1172 mode = channel->hw_value;
1173 switch (mode) {
1174 case AR5K_MODE_11A:
1175 break;
1176 case AR5K_MODE_11G:
1177 if (ah->ah_version <= AR5K_AR5211) {
1178 ATH5K_ERR(ah,
1179 "G mode not available on 5210/5211");
1180 return -EINVAL;
1181 }
1182 break;
1183 case AR5K_MODE_11B:
1184 if (ah->ah_version < AR5K_AR5211) {
1185 ATH5K_ERR(ah,
1186 "B mode not available on 5210");
1187 return -EINVAL;
1188 }
1189 break;
1190 default:
1191 ATH5K_ERR(ah,
1192 "invalid channel: %d\n", channel->center_freq);
1193 return -EINVAL;
1194 }
1195
1196 /*
1197 * If driver requested fast channel change and DMA has stopped
1198 * go on. If it fails continue with a normal reset.
1199 */
1200 if (fast) {
1201 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1202 if (ret) {
1203 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1204 "fast chan change failed, falling back to normal reset\n");
1205 /* Non fatal, can happen eg.
1206 * on mode change */
1207 ret = 0;
1208 } else {
1209 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1210 "fast chan change successful\n");
1211 return 0;
1212 }
1213 }
1214
1215 /*
1216 * Save some registers before a reset
1217 */
1218 if (ah->ah_version != AR5K_AR5210) {
1219 /*
1220 * Save frame sequence count
1221 * For revs. after Oahu, only save
1222 * seq num for DCU 0 (Global seq num)
1223 */
1224 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1225
1226 for (i = 0; i < 10; i++)
1227 s_seq[i] = ath5k_hw_reg_read(ah,
1228 AR5K_QUEUE_DCU_SEQNUM(i));
1229
1230 } else {
1231 s_seq[0] = ath5k_hw_reg_read(ah,
1232 AR5K_QUEUE_DCU_SEQNUM(0));
1233 }
1234
1235 /* TSF accelerates on AR5211 during reset
1236 * As a workaround save it here and restore
1237 * it later so that it's back in time after
1238 * reset. This way it'll get re-synced on the
1239 * next beacon without breaking ad-hoc.
1240 *
1241 * On AR5212 TSF is almost preserved across a
1242 * reset so it stays back in time anyway and
1243 * we don't have to save/restore it.
1244 *
1245 * XXX: Since this breaks power saving we have
1246 * to disable power saving until we receive the
1247 * next beacon, so we can resync beacon timers */
1248 if (ah->ah_version == AR5K_AR5211) {
1249 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1250 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1251 }
1252 }
1253
1254
1255 /*GPIOs*/
1256 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1257 AR5K_PCICFG_LEDSTATE;
1258 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1259 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1260
1261
1262 /*
1263 * Since we are going to write rf buffer
1264 * check if we have any pending gain_F
1265 * optimization settings
1266 */
1267 if (ah->ah_version == AR5K_AR5212 &&
1268 (ah->ah_radio <= AR5K_RF5112)) {
1269 if (!fast && ah->ah_rf_banks != NULL)
1270 ath5k_hw_gainf_calibrate(ah);
1271 }
1272
1273 /* Wakeup the device */
1274 ret = ath5k_hw_nic_wakeup(ah, channel);
1275 if (ret)
1276 return ret;
1277
1278 /* PHY access enable */
1279 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1280 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1281 else
1282 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1283 AR5K_PHY(0));
1284
1285 /* Write initial settings */
1286 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1287 if (ret)
1288 return ret;
1289
1290 /* Initialize core clock settings */
1291 ath5k_hw_init_core_clock(ah);
1292
1293 /*
1294 * Tweak initval settings for revised
1295 * chipsets and add some more config
1296 * bits
1297 */
1298 ath5k_hw_tweak_initval_settings(ah, channel);
1299
1300 /* Commit values from EEPROM */
1301 ath5k_hw_commit_eeprom_settings(ah, channel);
1302
1303
1304 /*
1305 * Restore saved values
1306 */
1307
1308 /* Seqnum, TSF */
1309 if (ah->ah_version != AR5K_AR5210) {
1310 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1311 for (i = 0; i < 10; i++)
1312 ath5k_hw_reg_write(ah, s_seq[i],
1313 AR5K_QUEUE_DCU_SEQNUM(i));
1314 } else {
1315 ath5k_hw_reg_write(ah, s_seq[0],
1316 AR5K_QUEUE_DCU_SEQNUM(0));
1317 }
1318
1319 if (ah->ah_version == AR5K_AR5211) {
1320 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1321 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1322 }
1323 }
1324
1325 /* Ledstate */
1326 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1327
1328 /* Gpio settings */
1329 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1330 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1331
1332 /*
1333 * Initialize PCU
1334 */
1335 ath5k_hw_pcu_init(ah, op_mode);
1336
1337 /*
1338 * Initialize PHY
1339 */
1340 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1341 if (ret) {
1342 ATH5K_ERR(ah,
1343 "failed to initialize PHY (%i) !\n", ret);
1344 return ret;
1345 }
1346
1347 /*
1348 * Configure QCUs/DCUs
1349 */
1350 ret = ath5k_hw_init_queues(ah);
1351 if (ret)
1352 return ret;
1353
1354
1355 /*
1356 * Initialize DMA/Interrupts
1357 */
1358 ath5k_hw_dma_init(ah);
1359
1360
1361 /*
1362 * Enable 32KHz clock function for AR5212+ chips
1363 * Set clocks to 32KHz operation and use an
1364 * external 32KHz crystal when sleeping if one
1365 * exists.
1366 * Disabled by default because it is also disabled in
1367 * other drivers and it is known to cause stability
1368 * issues on some devices
1369 */
1370 if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1371 op_mode != NL80211_IFTYPE_AP)
1372 ath5k_hw_set_sleep_clock(ah, true);
1373
1374 /*
1375 * Disable beacons and reset the TSF
1376 */
1377 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1378 ath5k_hw_reset_tsf(ah);
1379 return 0;
1380}
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22/*****************************\
23 Reset functions and helpers
24\*****************************/
25
26#include <asm/unaligned.h>
27
28#include <linux/pci.h> /* To determine if a card is pci-e */
29#include <linux/log2.h>
30#include <linux/platform_device.h>
31#include "ath5k.h"
32#include "reg.h"
33#include "base.h"
34#include "debug.h"
35
36
37/******************\
38* Helper functions *
39\******************/
40
41/*
42 * Check if a register write has been completed
43 */
44int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
45 bool is_set)
46{
47 int i;
48 u32 data;
49
50 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
51 data = ath5k_hw_reg_read(ah, reg);
52 if (is_set && (data & flag))
53 break;
54 else if ((data & flag) == val)
55 break;
56 udelay(15);
57 }
58
59 return (i <= 0) ? -EAGAIN : 0;
60}
61
62
63/*************************\
64* Clock related functions *
65\*************************/
66
67/**
68 * ath5k_hw_htoclock - Translate usec to hw clock units
69 *
70 * @ah: The &struct ath5k_hw
71 * @usec: value in microseconds
72 */
73unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
74{
75 struct ath_common *common = ath5k_hw_common(ah);
76 return usec * common->clockrate;
77}
78
79/**
80 * ath5k_hw_clocktoh - Translate hw clock units to usec
81 * @clock: value in hw clock units
82 */
83unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
84{
85 struct ath_common *common = ath5k_hw_common(ah);
86 return clock / common->clockrate;
87}
88
89/**
90 * ath5k_hw_init_core_clock - Initialize core clock
91 *
92 * @ah The &struct ath5k_hw
93 *
94 * Initialize core clock parameters (usec, usec32, latencies etc).
95 */
96static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
97{
98 struct ieee80211_channel *channel = ah->ah_current_channel;
99 struct ath_common *common = ath5k_hw_common(ah);
100 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
101
102 /*
103 * Set core clock frequency
104 */
105 if (channel->hw_value & CHANNEL_5GHZ)
106 clock = 40; /* 802.11a */
107 else if (channel->hw_value & CHANNEL_CCK)
108 clock = 22; /* 802.11b */
109 else
110 clock = 44; /* 802.11g */
111
112 /* Use clock multiplier for non-default
113 * bwmode */
114 switch (ah->ah_bwmode) {
115 case AR5K_BWMODE_40MHZ:
116 clock *= 2;
117 break;
118 case AR5K_BWMODE_10MHZ:
119 clock /= 2;
120 break;
121 case AR5K_BWMODE_5MHZ:
122 clock /= 4;
123 break;
124 default:
125 break;
126 }
127
128 common->clockrate = clock;
129
130 /*
131 * Set USEC parameters
132 */
133 /* Set USEC counter on PCU*/
134 usec = clock - 1;
135 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
136
137 /* Set usec duration on DCU */
138 if (ah->ah_version != AR5K_AR5210)
139 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
140 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
141 clock);
142
143 /* Set 32MHz USEC counter */
144 if ((ah->ah_radio == AR5K_RF5112) ||
145 (ah->ah_radio == AR5K_RF2413) ||
146 (ah->ah_radio == AR5K_RF5413) ||
147 (ah->ah_radio == AR5K_RF2316) ||
148 (ah->ah_radio == AR5K_RF2317))
149 /* Remain on 40MHz clock ? */
150 sclock = 40 - 1;
151 else
152 sclock = 32 - 1;
153 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
154
155 /*
156 * Set tx/rx latencies
157 */
158 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
159 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
160 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
161
162 /*
163 * Set default Tx frame to Tx data start delay
164 */
165 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
166
167 /*
168 * 5210 initvals don't include usec settings
169 * so we need to use magic values here for
170 * tx/rx latencies
171 */
172 if (ah->ah_version == AR5K_AR5210) {
173 /* same for turbo */
174 txlat = AR5K_INIT_TX_LATENCY_5210;
175 rxlat = AR5K_INIT_RX_LATENCY_5210;
176 }
177
178 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
179 /* 5311 has different tx/rx latency masks
180 * from 5211, since we deal 5311 the same
181 * as 5211 when setting initvals, shift
182 * values here to their proper locations
183 *
184 * Note: Initvals indicate tx/rx/ latencies
185 * are the same for turbo mode */
186 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
187 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
188 } else
189 switch (ah->ah_bwmode) {
190 case AR5K_BWMODE_10MHZ:
191 txlat = AR5K_REG_SM(txlat * 2,
192 AR5K_USEC_TX_LATENCY_5211);
193 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
194 AR5K_USEC_RX_LATENCY_5211);
195 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
196 break;
197 case AR5K_BWMODE_5MHZ:
198 txlat = AR5K_REG_SM(txlat * 4,
199 AR5K_USEC_TX_LATENCY_5211);
200 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
201 AR5K_USEC_RX_LATENCY_5211);
202 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
203 break;
204 case AR5K_BWMODE_40MHZ:
205 txlat = AR5K_INIT_TX_LAT_MIN;
206 rxlat = AR5K_REG_SM(rxlat / 2,
207 AR5K_USEC_RX_LATENCY_5211);
208 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
209 break;
210 default:
211 break;
212 }
213
214 usec_reg = (usec | sclock | txlat | rxlat);
215 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
216
217 /* On 5112 set tx frame to tx data start delay */
218 if (ah->ah_radio == AR5K_RF5112) {
219 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
220 AR5K_PHY_RF_CTL2_TXF2TXD_START,
221 txf2txs);
222 }
223}
224
225/*
226 * If there is an external 32KHz crystal available, use it
227 * as ref. clock instead of 32/40MHz clock and baseband clocks
228 * to save power during sleep or restore normal 32/40MHz
229 * operation.
230 *
231 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
232 * 123 - 127) require delay on access.
233 */
234static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
235{
236 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
237 u32 scal, spending, sclock;
238
239 /* Only set 32KHz settings if we have an external
240 * 32KHz crystal present */
241 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
242 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
243 enable) {
244
245 /* 1 usec/cycle */
246 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
247 /* Set up tsf increment on each cycle */
248 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
249
250 /* Set baseband sleep control registers
251 * and sleep control rate */
252 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
253
254 if ((ah->ah_radio == AR5K_RF5112) ||
255 (ah->ah_radio == AR5K_RF5413) ||
256 (ah->ah_radio == AR5K_RF2316) ||
257 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
258 spending = 0x14;
259 else
260 spending = 0x18;
261 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
262
263 if ((ah->ah_radio == AR5K_RF5112) ||
264 (ah->ah_radio == AR5K_RF5413) ||
265 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
266 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
267 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
268 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
269 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
270 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
271 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
272 } else {
273 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
274 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
275 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
276 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
277 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
278 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
279 }
280
281 /* Enable sleep clock operation */
282 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
283 AR5K_PCICFG_SLEEP_CLOCK_EN);
284
285 } else {
286
287 /* Disable sleep clock operation and
288 * restore default parameters */
289 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
290 AR5K_PCICFG_SLEEP_CLOCK_EN);
291
292 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
293 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
294
295 /* Set DAC/ADC delays */
296 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
297 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
298
299 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
300 scal = AR5K_PHY_SCAL_32MHZ_2417;
301 else if (ee->ee_is_hb63)
302 scal = AR5K_PHY_SCAL_32MHZ_HB63;
303 else
304 scal = AR5K_PHY_SCAL_32MHZ;
305 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
306
307 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
308 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
309
310 if ((ah->ah_radio == AR5K_RF5112) ||
311 (ah->ah_radio == AR5K_RF5413) ||
312 (ah->ah_radio == AR5K_RF2316) ||
313 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
314 spending = 0x14;
315 else
316 spending = 0x18;
317 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
318
319 /* Set up tsf increment on each cycle */
320 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
321
322 if ((ah->ah_radio == AR5K_RF5112) ||
323 (ah->ah_radio == AR5K_RF5413) ||
324 (ah->ah_radio == AR5K_RF2316) ||
325 (ah->ah_radio == AR5K_RF2317))
326 sclock = 40 - 1;
327 else
328 sclock = 32 - 1;
329 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
330 }
331}
332
333
334/*********************\
335* Reset/Sleep control *
336\*********************/
337
338/*
339 * Reset chipset
340 */
341static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
342{
343 int ret;
344 u32 mask = val ? val : ~0U;
345
346 /* Read-and-clear RX Descriptor Pointer*/
347 ath5k_hw_reg_read(ah, AR5K_RXDP);
348
349 /*
350 * Reset the device and wait until success
351 */
352 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
353
354 /* Wait at least 128 PCI clocks */
355 udelay(15);
356
357 if (ah->ah_version == AR5K_AR5210) {
358 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
359 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
360 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
361 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
362 } else {
363 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
364 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
365 }
366
367 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
368
369 /*
370 * Reset configuration register (for hw byte-swap). Note that this
371 * is only set for big endian. We do the necessary magic in
372 * AR5K_INIT_CFG.
373 */
374 if ((val & AR5K_RESET_CTL_PCU) == 0)
375 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
376
377 return ret;
378}
379
380/*
381 * Reset AHB chipset
382 * AR5K_RESET_CTL_PCU flag resets WMAC
383 * AR5K_RESET_CTL_BASEBAND flag resets WBB
384 */
385static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
386{
387 u32 mask = flags ? flags : ~0U;
388 u32 __iomem *reg;
389 u32 regval;
390 u32 val = 0;
391
392 /* ah->ah_mac_srev is not available at this point yet */
393 if (ah->devid >= AR5K_SREV_AR2315_R6) {
394 reg = (u32 __iomem *) AR5K_AR2315_RESET;
395 if (mask & AR5K_RESET_CTL_PCU)
396 val |= AR5K_AR2315_RESET_WMAC;
397 if (mask & AR5K_RESET_CTL_BASEBAND)
398 val |= AR5K_AR2315_RESET_BB_WARM;
399 } else {
400 reg = (u32 __iomem *) AR5K_AR5312_RESET;
401 if (to_platform_device(ah->dev)->id == 0) {
402 if (mask & AR5K_RESET_CTL_PCU)
403 val |= AR5K_AR5312_RESET_WMAC0;
404 if (mask & AR5K_RESET_CTL_BASEBAND)
405 val |= AR5K_AR5312_RESET_BB0_COLD |
406 AR5K_AR5312_RESET_BB0_WARM;
407 } else {
408 if (mask & AR5K_RESET_CTL_PCU)
409 val |= AR5K_AR5312_RESET_WMAC1;
410 if (mask & AR5K_RESET_CTL_BASEBAND)
411 val |= AR5K_AR5312_RESET_BB1_COLD |
412 AR5K_AR5312_RESET_BB1_WARM;
413 }
414 }
415
416 /* Put BB/MAC into reset */
417 regval = __raw_readl(reg);
418 __raw_writel(regval | val, reg);
419 regval = __raw_readl(reg);
420 udelay(100);
421
422 /* Bring BB/MAC out of reset */
423 __raw_writel(regval & ~val, reg);
424 regval = __raw_readl(reg);
425
426 /*
427 * Reset configuration register (for hw byte-swap). Note that this
428 * is only set for big endian. We do the necessary magic in
429 * AR5K_INIT_CFG.
430 */
431 if ((flags & AR5K_RESET_CTL_PCU) == 0)
432 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
433
434 return 0;
435}
436
437
438/*
439 * Sleep control
440 */
441static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
442 bool set_chip, u16 sleep_duration)
443{
444 unsigned int i;
445 u32 staid, data;
446
447 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
448
449 switch (mode) {
450 case AR5K_PM_AUTO:
451 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
452 /* fallthrough */
453 case AR5K_PM_NETWORK_SLEEP:
454 if (set_chip)
455 ath5k_hw_reg_write(ah,
456 AR5K_SLEEP_CTL_SLE_ALLOW |
457 sleep_duration,
458 AR5K_SLEEP_CTL);
459
460 staid |= AR5K_STA_ID1_PWR_SV;
461 break;
462
463 case AR5K_PM_FULL_SLEEP:
464 if (set_chip)
465 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
466 AR5K_SLEEP_CTL);
467
468 staid |= AR5K_STA_ID1_PWR_SV;
469 break;
470
471 case AR5K_PM_AWAKE:
472
473 staid &= ~AR5K_STA_ID1_PWR_SV;
474
475 if (!set_chip)
476 goto commit;
477
478 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
479
480 /* If card is down we 'll get 0xffff... so we
481 * need to clean this up before we write the register
482 */
483 if (data & 0xffc00000)
484 data = 0;
485 else
486 /* Preserve sleep duration etc */
487 data = data & ~AR5K_SLEEP_CTL_SLE;
488
489 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
490 AR5K_SLEEP_CTL);
491 udelay(15);
492
493 for (i = 200; i > 0; i--) {
494 /* Check if the chip did wake up */
495 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
496 AR5K_PCICFG_SPWR_DN) == 0)
497 break;
498
499 /* Wait a bit and retry */
500 udelay(50);
501 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
502 AR5K_SLEEP_CTL);
503 }
504
505 /* Fail if the chip didn't wake up */
506 if (i == 0)
507 return -EIO;
508
509 break;
510
511 default:
512 return -EINVAL;
513 }
514
515commit:
516 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
517
518 return 0;
519}
520
521/*
522 * Put device on hold
523 *
524 * Put MAC and Baseband on warm reset and
525 * keep that state (don't clean sleep control
526 * register). After this MAC and Baseband are
527 * disabled and a full reset is needed to come
528 * back. This way we save as much power as possible
529 * without putting the card on full sleep.
530 */
531int ath5k_hw_on_hold(struct ath5k_hw *ah)
532{
533 struct pci_dev *pdev = ah->pdev;
534 u32 bus_flags;
535 int ret;
536
537 if (ath5k_get_bus_type(ah) == ATH_AHB)
538 return 0;
539
540 /* Make sure device is awake */
541 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
542 if (ret) {
543 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
544 return ret;
545 }
546
547 /*
548 * Put chipset on warm reset...
549 *
550 * Note: putting PCI core on warm reset on PCI-E cards
551 * results card to hang and always return 0xffff... so
552 * we ignore that flag for PCI-E cards. On PCI cards
553 * this flag gets cleared after 64 PCI clocks.
554 */
555 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
556
557 if (ah->ah_version == AR5K_AR5210) {
558 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
559 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
560 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
561 mdelay(2);
562 } else {
563 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
564 AR5K_RESET_CTL_BASEBAND | bus_flags);
565 }
566
567 if (ret) {
568 ATH5K_ERR(ah, "failed to put device on warm reset\n");
569 return -EIO;
570 }
571
572 /* ...wakeup again!*/
573 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
574 if (ret) {
575 ATH5K_ERR(ah, "failed to put device on hold\n");
576 return ret;
577 }
578
579 return ret;
580}
581
582/*
583 * Bring up MAC + PHY Chips and program PLL
584 */
585int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
586{
587 struct pci_dev *pdev = ah->pdev;
588 u32 turbo, mode, clock, bus_flags;
589 int ret;
590
591 turbo = 0;
592 mode = 0;
593 clock = 0;
594
595 if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
596 /* Wakeup the device */
597 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
598 if (ret) {
599 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
600 return ret;
601 }
602 }
603
604 /*
605 * Put chipset on warm reset...
606 *
607 * Note: putting PCI core on warm reset on PCI-E cards
608 * results card to hang and always return 0xffff... so
609 * we ignore that flag for PCI-E cards. On PCI cards
610 * this flag gets cleared after 64 PCI clocks.
611 */
612 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
613
614 if (ah->ah_version == AR5K_AR5210) {
615 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
616 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
617 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
618 mdelay(2);
619 } else {
620 if (ath5k_get_bus_type(ah) == ATH_AHB)
621 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
622 AR5K_RESET_CTL_BASEBAND);
623 else
624 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
625 AR5K_RESET_CTL_BASEBAND | bus_flags);
626 }
627
628 if (ret) {
629 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
630 return -EIO;
631 }
632
633 /* ...wakeup again!...*/
634 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
635 if (ret) {
636 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
637 return ret;
638 }
639
640 /* ...reset configuration register on Wisoc ...
641 * ...clear reset control register and pull device out of
642 * warm reset on others */
643 if (ath5k_get_bus_type(ah) == ATH_AHB)
644 ret = ath5k_hw_wisoc_reset(ah, 0);
645 else
646 ret = ath5k_hw_nic_reset(ah, 0);
647
648 if (ret) {
649 ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
650 return -EIO;
651 }
652
653 /* On initialization skip PLL programming since we don't have
654 * a channel / mode set yet */
655 if (initial)
656 return 0;
657
658 if (ah->ah_version != AR5K_AR5210) {
659 /*
660 * Get channel mode flags
661 */
662
663 if (ah->ah_radio >= AR5K_RF5112) {
664 mode = AR5K_PHY_MODE_RAD_RF5112;
665 clock = AR5K_PHY_PLL_RF5112;
666 } else {
667 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
668 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
669 }
670
671 if (flags & CHANNEL_2GHZ) {
672 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
673 clock |= AR5K_PHY_PLL_44MHZ;
674
675 if (flags & CHANNEL_CCK) {
676 mode |= AR5K_PHY_MODE_MOD_CCK;
677 } else if (flags & CHANNEL_OFDM) {
678 /* XXX Dynamic OFDM/CCK is not supported by the
679 * AR5211 so we set MOD_OFDM for plain g (no
680 * CCK headers) operation. We need to test
681 * this, 5211 might support ofdm-only g after
682 * all, there are also initial register values
683 * in the code for g mode (see initvals.c).
684 */
685 if (ah->ah_version == AR5K_AR5211)
686 mode |= AR5K_PHY_MODE_MOD_OFDM;
687 else
688 mode |= AR5K_PHY_MODE_MOD_DYN;
689 } else {
690 ATH5K_ERR(ah,
691 "invalid radio modulation mode\n");
692 return -EINVAL;
693 }
694 } else if (flags & CHANNEL_5GHZ) {
695 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
696
697 /* Different PLL setting for 5413 */
698 if (ah->ah_radio == AR5K_RF5413)
699 clock = AR5K_PHY_PLL_40MHZ_5413;
700 else
701 clock |= AR5K_PHY_PLL_40MHZ;
702
703 if (flags & CHANNEL_OFDM)
704 mode |= AR5K_PHY_MODE_MOD_OFDM;
705 else {
706 ATH5K_ERR(ah,
707 "invalid radio modulation mode\n");
708 return -EINVAL;
709 }
710 } else {
711 ATH5K_ERR(ah, "invalid radio frequency mode\n");
712 return -EINVAL;
713 }
714
715 /*XXX: Can bwmode be used with dynamic mode ?
716 * (I don't think it supports 44MHz) */
717 /* On 2425 initvals TURBO_SHORT is not present */
718 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
719 turbo = AR5K_PHY_TURBO_MODE |
720 (ah->ah_radio == AR5K_RF2425) ? 0 :
721 AR5K_PHY_TURBO_SHORT;
722 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
723 if (ah->ah_radio == AR5K_RF5413) {
724 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
725 AR5K_PHY_MODE_HALF_RATE :
726 AR5K_PHY_MODE_QUARTER_RATE;
727 } else if (ah->ah_version == AR5K_AR5212) {
728 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
729 AR5K_PHY_PLL_HALF_RATE :
730 AR5K_PHY_PLL_QUARTER_RATE;
731 }
732 }
733
734 } else { /* Reset the device */
735
736 /* ...enable Atheros turbo mode if requested */
737 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
738 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
739 AR5K_PHY_TURBO);
740 }
741
742 if (ah->ah_version != AR5K_AR5210) {
743
744 /* ...update PLL if needed */
745 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
746 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
747 udelay(300);
748 }
749
750 /* ...set the PHY operating mode */
751 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
752 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
753 }
754
755 return 0;
756}
757
758
759/**************************************\
760* Post-initvals register modifications *
761\**************************************/
762
763/* TODO: Half/Quarter rate */
764static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
765 struct ieee80211_channel *channel)
766{
767 if (ah->ah_version == AR5K_AR5212 &&
768 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
769
770 /* Setup ADC control */
771 ath5k_hw_reg_write(ah,
772 (AR5K_REG_SM(2,
773 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
774 AR5K_REG_SM(2,
775 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
776 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
777 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
778 AR5K_PHY_ADC_CTL);
779
780
781
782 /* Disable barker RSSI threshold */
783 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
784 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
785
786 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
787 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
788
789 /* Set the mute mask */
790 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
791 }
792
793 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
794 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
795 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
796
797 /* Enable DCU double buffering */
798 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
799 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
800 AR5K_TXCFG_DCU_DBL_BUF_DIS);
801
802 /* Set fast ADC */
803 if ((ah->ah_radio == AR5K_RF5413) ||
804 (ah->ah_radio == AR5K_RF2317) ||
805 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
806 u32 fast_adc = true;
807
808 if (channel->center_freq == 2462 ||
809 channel->center_freq == 2467)
810 fast_adc = 0;
811
812 /* Only update if needed */
813 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
814 ath5k_hw_reg_write(ah, fast_adc,
815 AR5K_PHY_FAST_ADC);
816 }
817
818 /* Fix for first revision of the RF5112 RF chipset */
819 if (ah->ah_radio == AR5K_RF5112 &&
820 ah->ah_radio_5ghz_revision <
821 AR5K_SREV_RAD_5112A) {
822 u32 data;
823 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
824 AR5K_PHY_CCKTXCTL);
825 if (channel->hw_value & CHANNEL_5GHZ)
826 data = 0xffb81020;
827 else
828 data = 0xffb80d20;
829 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
830 }
831
832 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
833 /* Clear QCU/DCU clock gating register */
834 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
835 /* Set DAC/ADC delays */
836 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
837 AR5K_PHY_SCAL);
838 /* Enable PCU FIFO corruption ECO */
839 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
840 AR5K_DIAG_SW_ECO_ENABLE);
841 }
842
843 if (ah->ah_bwmode) {
844 /* Increase PHY switch and AGC settling time
845 * on turbo mode (ath5k_hw_commit_eeprom_settings
846 * will override settling time if available) */
847 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
848
849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
850 AR5K_PHY_SETTLING_AGC,
851 AR5K_AGC_SETTLING_TURBO);
852
853 /* XXX: Initvals indicate we only increase
854 * switch time on AR5212, 5211 and 5210
855 * only change agc time (bug?) */
856 if (ah->ah_version == AR5K_AR5212)
857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
858 AR5K_PHY_SETTLING_SWITCH,
859 AR5K_SWITCH_SETTLING_TURBO);
860
861 if (ah->ah_version == AR5K_AR5210) {
862 /* Set Frame Control Register */
863 ath5k_hw_reg_write(ah,
864 (AR5K_PHY_FRAME_CTL_INI |
865 AR5K_PHY_TURBO_MODE |
866 AR5K_PHY_TURBO_SHORT | 0x2020),
867 AR5K_PHY_FRAME_CTL_5210);
868 }
869 /* On 5413 PHY force window length for half/quarter rate*/
870 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
871 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
872 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
873 AR5K_PHY_FRAME_CTL_WIN_LEN,
874 3);
875 }
876 } else if (ah->ah_version == AR5K_AR5210) {
877 /* Set Frame Control Register for normal operation */
878 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
879 AR5K_PHY_FRAME_CTL_5210);
880 }
881}
882
883static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
884 struct ieee80211_channel *channel)
885{
886 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
887 s16 cck_ofdm_pwr_delta;
888 u8 ee_mode;
889
890 /* TODO: Add support for AR5210 EEPROM */
891 if (ah->ah_version == AR5K_AR5210)
892 return;
893
894 ee_mode = ath5k_eeprom_mode_from_channel(channel);
895
896 /* Adjust power delta for channel 14 */
897 if (channel->center_freq == 2484)
898 cck_ofdm_pwr_delta =
899 ((ee->ee_cck_ofdm_power_delta -
900 ee->ee_scaled_cck_delta) * 2) / 10;
901 else
902 cck_ofdm_pwr_delta =
903 (ee->ee_cck_ofdm_power_delta * 2) / 10;
904
905 /* Set CCK to OFDM power delta on tx power
906 * adjustment register */
907 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
908 if (channel->hw_value == CHANNEL_G)
909 ath5k_hw_reg_write(ah,
910 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
911 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
912 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
913 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
914 AR5K_PHY_TX_PWR_ADJ);
915 else
916 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
917 } else {
918 /* For older revs we scale power on sw during tx power
919 * setup */
920 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
921 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
922 ee->ee_cck_ofdm_gain_delta;
923 }
924
925 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
926 * too */
927 ath5k_hw_set_antenna_switch(ah, ee_mode);
928
929 /* Noise floor threshold */
930 ath5k_hw_reg_write(ah,
931 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
932 AR5K_PHY_NFTHRES);
933
934 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
935 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
936 /* Switch settling time (Turbo) */
937 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
938 AR5K_PHY_SETTLING_SWITCH,
939 ee->ee_switch_settling_turbo[ee_mode]);
940
941 /* Tx/Rx attenuation (Turbo) */
942 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
943 AR5K_PHY_GAIN_TXRX_ATTEN,
944 ee->ee_atn_tx_rx_turbo[ee_mode]);
945
946 /* ADC/PGA desired size (Turbo) */
947 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
948 AR5K_PHY_DESIRED_SIZE_ADC,
949 ee->ee_adc_desired_size_turbo[ee_mode]);
950
951 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
952 AR5K_PHY_DESIRED_SIZE_PGA,
953 ee->ee_pga_desired_size_turbo[ee_mode]);
954
955 /* Tx/Rx margin (Turbo) */
956 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
957 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
958 ee->ee_margin_tx_rx_turbo[ee_mode]);
959
960 } else {
961 /* Switch settling time */
962 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
963 AR5K_PHY_SETTLING_SWITCH,
964 ee->ee_switch_settling[ee_mode]);
965
966 /* Tx/Rx attenuation */
967 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
968 AR5K_PHY_GAIN_TXRX_ATTEN,
969 ee->ee_atn_tx_rx[ee_mode]);
970
971 /* ADC/PGA desired size */
972 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
973 AR5K_PHY_DESIRED_SIZE_ADC,
974 ee->ee_adc_desired_size[ee_mode]);
975
976 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
977 AR5K_PHY_DESIRED_SIZE_PGA,
978 ee->ee_pga_desired_size[ee_mode]);
979
980 /* Tx/Rx margin */
981 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
982 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
983 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
984 ee->ee_margin_tx_rx[ee_mode]);
985 }
986
987 /* XPA delays */
988 ath5k_hw_reg_write(ah,
989 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
990 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
991 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
992 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
993
994 /* XLNA delay */
995 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
996 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
997 ee->ee_tx_end2xlna_enable[ee_mode]);
998
999 /* Thresh64 (ANI) */
1000 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
1001 AR5K_PHY_NF_THRESH62,
1002 ee->ee_thr_62[ee_mode]);
1003
1004 /* False detect backoff for channels
1005 * that have spur noise. Write the new
1006 * cyclic power RSSI threshold. */
1007 if (ath5k_hw_chan_has_spur_noise(ah, channel))
1008 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1009 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1010 AR5K_INIT_CYCRSSI_THR1 +
1011 ee->ee_false_detect[ee_mode]);
1012 else
1013 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1014 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1015 AR5K_INIT_CYCRSSI_THR1);
1016
1017 /* I/Q correction (set enable bit last to match HAL sources) */
1018 /* TODO: Per channel i/q infos ? */
1019 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1020 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1021 ee->ee_i_cal[ee_mode]);
1022 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1023 ee->ee_q_cal[ee_mode]);
1024 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1025 }
1026
1027 /* Heavy clipping -disable for now */
1028 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1029 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1030}
1031
1032
1033/*********************\
1034* Main reset function *
1035\*********************/
1036
1037int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1038 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1039{
1040 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1041 u8 mode;
1042 int i, ret;
1043
1044 tsf_up = 0;
1045 tsf_lo = 0;
1046 mode = 0;
1047
1048 /*
1049 * Sanity check for fast flag
1050 * Fast channel change only available
1051 * on AR2413/AR5413.
1052 */
1053 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1054 (ah->ah_radio != AR5K_RF5413))
1055 fast = 0;
1056
1057 /* Disable sleep clock operation
1058 * to avoid register access delay on certain
1059 * PHY registers */
1060 if (ah->ah_version == AR5K_AR5212)
1061 ath5k_hw_set_sleep_clock(ah, false);
1062
1063 /*
1064 * Stop PCU
1065 */
1066 ath5k_hw_stop_rx_pcu(ah);
1067
1068 /*
1069 * Stop DMA
1070 *
1071 * Note: If DMA didn't stop continue
1072 * since only a reset will fix it.
1073 */
1074 ret = ath5k_hw_dma_stop(ah);
1075
1076 /* RF Bus grant won't work if we have pending
1077 * frames */
1078 if (ret && fast) {
1079 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1080 "DMA didn't stop, falling back to normal reset\n");
1081 fast = 0;
1082 /* Non fatal, just continue with
1083 * normal reset */
1084 ret = 0;
1085 }
1086
1087 switch (channel->hw_value & CHANNEL_MODES) {
1088 case CHANNEL_A:
1089 mode = AR5K_MODE_11A;
1090 break;
1091 case CHANNEL_G:
1092
1093 if (ah->ah_version <= AR5K_AR5211) {
1094 ATH5K_ERR(ah,
1095 "G mode not available on 5210/5211");
1096 return -EINVAL;
1097 }
1098
1099 mode = AR5K_MODE_11G;
1100 break;
1101 case CHANNEL_B:
1102
1103 if (ah->ah_version < AR5K_AR5211) {
1104 ATH5K_ERR(ah,
1105 "B mode not available on 5210");
1106 return -EINVAL;
1107 }
1108
1109 mode = AR5K_MODE_11B;
1110 break;
1111 case CHANNEL_XR:
1112 if (ah->ah_version == AR5K_AR5211) {
1113 ATH5K_ERR(ah,
1114 "XR mode not available on 5211");
1115 return -EINVAL;
1116 }
1117 mode = AR5K_MODE_XR;
1118 break;
1119 default:
1120 ATH5K_ERR(ah,
1121 "invalid channel: %d\n", channel->center_freq);
1122 return -EINVAL;
1123 }
1124
1125 /*
1126 * If driver requested fast channel change and DMA has stopped
1127 * go on. If it fails continue with a normal reset.
1128 */
1129 if (fast) {
1130 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1131 if (ret) {
1132 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1133 "fast chan change failed, falling back to normal reset\n");
1134 /* Non fatal, can happen eg.
1135 * on mode change */
1136 ret = 0;
1137 } else {
1138 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1139 "fast chan change successful\n");
1140 return 0;
1141 }
1142 }
1143
1144 /*
1145 * Save some registers before a reset
1146 */
1147 if (ah->ah_version != AR5K_AR5210) {
1148 /*
1149 * Save frame sequence count
1150 * For revs. after Oahu, only save
1151 * seq num for DCU 0 (Global seq num)
1152 */
1153 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1154
1155 for (i = 0; i < 10; i++)
1156 s_seq[i] = ath5k_hw_reg_read(ah,
1157 AR5K_QUEUE_DCU_SEQNUM(i));
1158
1159 } else {
1160 s_seq[0] = ath5k_hw_reg_read(ah,
1161 AR5K_QUEUE_DCU_SEQNUM(0));
1162 }
1163
1164 /* TSF accelerates on AR5211 during reset
1165 * As a workaround save it here and restore
1166 * it later so that it's back in time after
1167 * reset. This way it'll get re-synced on the
1168 * next beacon without breaking ad-hoc.
1169 *
1170 * On AR5212 TSF is almost preserved across a
1171 * reset so it stays back in time anyway and
1172 * we don't have to save/restore it.
1173 *
1174 * XXX: Since this breaks power saving we have
1175 * to disable power saving until we receive the
1176 * next beacon, so we can resync beacon timers */
1177 if (ah->ah_version == AR5K_AR5211) {
1178 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1179 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1180 }
1181 }
1182
1183
1184 /*GPIOs*/
1185 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1186 AR5K_PCICFG_LEDSTATE;
1187 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1188 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1189
1190
1191 /*
1192 * Since we are going to write rf buffer
1193 * check if we have any pending gain_F
1194 * optimization settings
1195 */
1196 if (ah->ah_version == AR5K_AR5212 &&
1197 (ah->ah_radio <= AR5K_RF5112)) {
1198 if (!fast && ah->ah_rf_banks != NULL)
1199 ath5k_hw_gainf_calibrate(ah);
1200 }
1201
1202 /* Wakeup the device */
1203 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1204 if (ret)
1205 return ret;
1206
1207 /* PHY access enable */
1208 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1209 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1210 else
1211 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1212 AR5K_PHY(0));
1213
1214 /* Write initial settings */
1215 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1216 if (ret)
1217 return ret;
1218
1219 /* Initialize core clock settings */
1220 ath5k_hw_init_core_clock(ah);
1221
1222 /*
1223 * Tweak initval settings for revised
1224 * chipsets and add some more config
1225 * bits
1226 */
1227 ath5k_hw_tweak_initval_settings(ah, channel);
1228
1229 /* Commit values from EEPROM */
1230 ath5k_hw_commit_eeprom_settings(ah, channel);
1231
1232
1233 /*
1234 * Restore saved values
1235 */
1236
1237 /* Seqnum, TSF */
1238 if (ah->ah_version != AR5K_AR5210) {
1239 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1240 for (i = 0; i < 10; i++)
1241 ath5k_hw_reg_write(ah, s_seq[i],
1242 AR5K_QUEUE_DCU_SEQNUM(i));
1243 } else {
1244 ath5k_hw_reg_write(ah, s_seq[0],
1245 AR5K_QUEUE_DCU_SEQNUM(0));
1246 }
1247
1248 if (ah->ah_version == AR5K_AR5211) {
1249 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1250 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1251 }
1252 }
1253
1254 /* Ledstate */
1255 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1256
1257 /* Gpio settings */
1258 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1259 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1260
1261 /*
1262 * Initialize PCU
1263 */
1264 ath5k_hw_pcu_init(ah, op_mode, mode);
1265
1266 /*
1267 * Initialize PHY
1268 */
1269 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1270 if (ret) {
1271 ATH5K_ERR(ah,
1272 "failed to initialize PHY (%i) !\n", ret);
1273 return ret;
1274 }
1275
1276 /*
1277 * Configure QCUs/DCUs
1278 */
1279 ret = ath5k_hw_init_queues(ah);
1280 if (ret)
1281 return ret;
1282
1283
1284 /*
1285 * Initialize DMA/Interrupts
1286 */
1287 ath5k_hw_dma_init(ah);
1288
1289
1290 /*
1291 * Enable 32KHz clock function for AR5212+ chips
1292 * Set clocks to 32KHz operation and use an
1293 * external 32KHz crystal when sleeping if one
1294 * exists.
1295 * Disabled by default because it is also disabled in
1296 * other drivers and it is known to cause stability
1297 * issues on some devices
1298 */
1299 if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1300 op_mode != NL80211_IFTYPE_AP)
1301 ath5k_hw_set_sleep_clock(ah, true);
1302
1303 /*
1304 * Disable beacons and reset the TSF
1305 */
1306 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1307 ath5k_hw_reset_tsf(ah);
1308 return 0;
1309}