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1/*
2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions.
3 *
4 * Author: Ivan Passos <ivan@cyclades.com>
5 *
6 * Copyright: (c) 1999-2002 Cyclades Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * $Log: pc300.h,v $
14 * Revision 3.12 2002/03/07 14:17:09 henrique
15 * License data fixed
16 *
17 * Revision 3.11 2002/01/28 21:09:39 daniela
18 * Included ';' after pc300hw.bus.
19 *
20 * Revision 3.10 2002/01/17 17:58:52 ivan
21 * Support for PC300-TE/M (PMC).
22 *
23 * Revision 3.9 2001/09/28 13:30:53 daniela
24 * Renamed dma_start routine to rx_dma_start.
25 *
26 * Revision 3.8 2001/09/24 13:03:45 daniela
27 * Fixed BOF interrupt treatment. Created dma_start routine.
28 *
29 * Revision 3.7 2001/08/10 17:19:58 daniela
30 * Fixed IOCTLs defines.
31 *
32 * Revision 3.6 2001/07/18 19:24:42 daniela
33 * Included kernel version.
34 *
35 * Revision 3.5 2001/07/05 18:38:08 daniela
36 * DMA transmission bug fix.
37 *
38 * Revision 3.4 2001/06/26 17:10:40 daniela
39 * New configuration parameters (line code, CRC calculation and clock).
40 *
41 * Revision 3.3 2001/06/22 13:13:02 regina
42 * MLPPP implementation
43 *
44 * Revision 3.2 2001/06/18 17:56:09 daniela
45 * Increased DEF_MTU and TX_QUEUE_LEN.
46 *
47 * Revision 3.1 2001/06/15 12:41:10 regina
48 * upping major version number
49 *
50 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela
51 * PC300 initial CVS version (3.4.0-pre1)
52 *
53 * Revision 2.3 2001/03/05 daniela
54 * Created struct pc300conf, to provide the hardware information to pc300util.
55 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
56 *
57 * Revision 2.2 2000/12/22 daniela
58 * Structures and defines to support pc300util: statistics, status,
59 * loopback tests, trace.
60 *
61 * Revision 2.1 2000/09/28 ivan
62 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
63 * allow release of I/O region at module unload.
64 * Changed location of include files.
65 *
66 * Revision 2.0 2000/03/27 ivan
67 * Added support for the PC300/TE cards.
68 *
69 * Revision 1.1 2000/01/31 ivan
70 * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
71 *
72 * Revision 1.0 1999/12/16 ivan
73 * First official release.
74 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
75 * number of ports per card.
76 * Inclusion of 'if_ptr' field on structure 'pc300dev'.
77 *
78 * Revision 0.6 1999/11/17 ivan
79 * Changed X.25-specific function names to comply with adopted convention.
80 *
81 * Revision 0.5 1999/11/16 Daniela Squassoni
82 * X.25 support.
83 *
84 * Revision 0.4 1999/11/15 ivan
85 * Inclusion of 'clock' field on structure 'pc300hw'.
86 *
87 * Revision 0.3 1999/11/10 ivan
88 * IOCTL name changing.
89 * Inclusion of driver function prototypes.
90 *
91 * Revision 0.2 1999/11/03 ivan
92 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
93 *
94 * Revision 0.1 1999/01/15 ivan
95 * Initial version.
96 *
97 */
98
99#ifndef _PC300_H
100#define _PC300_H
101
102#include <linux/hdlc.h>
103#include "hd64572.h"
104#include "pc300-falc-lh.h"
105
106#define PC300_PROTO_MLPPP 1
107
108#define PC300_MAXCHAN 2 /* Number of channels per card */
109
110#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
111#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
112
113#define PC300_OSC_CLOCK 24576000
114#define PC300_PCI_CLOCK 33000000
115
116#define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
117#define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
118#define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
119
120#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
121#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
122
123/* DMA Buffer Offsets */
124#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
125 PC300_MAXCHAN * sizeof(pcsca_bd_t))
126#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
127
128/* DMA Descriptor Offsets */
129#define DMA_TX_BD_BASE 0x0000
130#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
131 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
132
133/* DMA Descriptor Macros */
134#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
135 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
136#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
137 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
138
139/* Macro to access the FALC registers (TE only) */
140#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
141
142/***************************************
143 * Memory access functions/macros *
144 * (required to support Alpha systems) *
145 ***************************************/
146#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
147#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
148#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
149
150#define cpc_readb(port) readb(port)
151#define cpc_readw(port) readw(port)
152#define cpc_readl(port) readl(port)
153
154/****** Data Structures *****************************************************/
155
156/*
157 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
158 * registers. This structure can be used to access the 9050 registers
159 * (memory mapped).
160 */
161struct RUNTIME_9050 {
162 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
163 u32 loc_rom_range; /* 10h : Local ROM Range */
164 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
165 u32 loc_rom_base; /* 24h : Local ROM Base */
166 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
167 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
168 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
169 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
170 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
171};
172
173#define PLX_9050_LINT1_ENABLE 0x01
174#define PLX_9050_LINT1_POL 0x02
175#define PLX_9050_LINT1_STATUS 0x04
176#define PLX_9050_LINT2_ENABLE 0x08
177#define PLX_9050_LINT2_POL 0x10
178#define PLX_9050_LINT2_STATUS 0x20
179#define PLX_9050_INTR_ENABLE 0x40
180#define PLX_9050_SW_INTR 0x80
181
182/* Masks to access the init_ctrl PLX register */
183#define PC300_CLKSEL_MASK (0x00000004UL)
184#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
185#define PC300_CTYPE_MASK (0x00000800UL)
186
187/* CPLD Registers (base addr = falcbase, TE only) */
188/* CPLD v. 0 */
189#define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
190#define CPLD_REG2 0x144 /* Clock enable , LED control */
191/* CPLD v. 2 or higher */
192#define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
193#define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
194#define CPLD_ID_REG 0x108 /* CPLD version */
195
196/* CPLD Register bit description: for the FALC bits, they should always be
197 set based on the channel (use (bit<<(2*ch)) to access the correct bit for
198 that channel) */
199#define CPLD_REG1_FALC_RESET 0x01
200#define CPLD_REG1_SCA_RESET 0x02
201#define CPLD_REG1_GLOBAL_CLK 0x08
202#define CPLD_REG1_FALC_DCD 0x10
203#define CPLD_REG1_FALC_CTS 0x20
204
205#define CPLD_REG2_FALC_TX_CLK 0x01
206#define CPLD_REG2_FALC_RX_CLK 0x02
207#define CPLD_REG2_FALC_LED1 0x10
208#define CPLD_REG2_FALC_LED2 0x20
209
210/* Structure with FALC-related fields (TE only) */
211#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
212
213typedef struct falc {
214 u8 sync; /* If true FALC is synchronized */
215 u8 active; /* if TRUE then already active */
216 u8 loop_active; /* if TRUE a line loopback UP was received */
217 u8 loop_gen; /* if TRUE a line loopback UP was issued */
218
219 u8 num_channels;
220 u8 offset; /* 1 for T1, 0 for E1 */
221 u8 full_bandwidth;
222
223 u8 xmb_cause;
224 u8 multiframe_mode;
225
226 /* Statistics */
227 u16 pden; /* Pulse Density violation count */
228 u16 los; /* Loss of Signal count */
229 u16 losr; /* Loss of Signal recovery count */
230 u16 lfa; /* Loss of frame alignment count */
231 u16 farec; /* Frame Alignment Recovery count */
232 u16 lmfa; /* Loss of multiframe alignment count */
233 u16 ais; /* Remote Alarm indication Signal count */
234 u16 sec; /* One-second timer */
235 u16 es; /* Errored second */
236 u16 rai; /* remote alarm received */
237 u16 bec;
238 u16 fec;
239 u16 cvc;
240 u16 cec;
241 u16 ebc;
242
243 /* Status */
244 u8 red_alarm;
245 u8 blue_alarm;
246 u8 loss_fa;
247 u8 yellow_alarm;
248 u8 loss_mfa;
249 u8 prbs;
250} falc_t;
251
252typedef struct falc_status {
253 u8 sync; /* If true FALC is synchronized */
254 u8 red_alarm;
255 u8 blue_alarm;
256 u8 loss_fa;
257 u8 yellow_alarm;
258 u8 loss_mfa;
259 u8 prbs;
260} falc_status_t;
261
262typedef struct rsv_x21_status {
263 u8 dcd;
264 u8 dsr;
265 u8 cts;
266 u8 rts;
267 u8 dtr;
268} rsv_x21_status_t;
269
270typedef struct pc300stats {
271 int hw_type;
272 u32 line_on;
273 u32 line_off;
274 struct net_device_stats gen_stats;
275 falc_t te_stats;
276} pc300stats_t;
277
278typedef struct pc300status {
279 int hw_type;
280 rsv_x21_status_t gen_status;
281 falc_status_t te_status;
282} pc300status_t;
283
284typedef struct pc300loopback {
285 char loop_type;
286 char loop_on;
287} pc300loopback_t;
288
289typedef struct pc300patterntst {
290 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
291 u16 num_errors;
292} pc300patterntst_t;
293
294typedef struct pc300dev {
295 struct pc300ch *chan;
296 u8 trace_on;
297 u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
298 u32 line_off;
299 char name[16];
300 struct net_device *dev;
301#ifdef CONFIG_PC300_MLPPP
302 void *cpc_tty; /* information to PC300 TTY driver */
303#endif
304}pc300dev_t;
305
306typedef struct pc300hw {
307 int type; /* RSV, X21, etc. */
308 int bus; /* Bus (PCI, PMC, etc.) */
309 int nchan; /* number of channels */
310 int irq; /* interrupt request level */
311 u32 clock; /* Board clock */
312 u8 cpld_id; /* CPLD ID (TE only) */
313 u16 cpld_reg1; /* CPLD reg 1 (TE only) */
314 u16 cpld_reg2; /* CPLD reg 2 (TE only) */
315 u16 gpioc_reg; /* PLX GPIOC reg */
316 u16 intctl_reg; /* PLX Int Ctrl/Status reg */
317 u32 iophys; /* PLX registers I/O base */
318 u32 iosize; /* PLX registers I/O size */
319 u32 plxphys; /* PLX registers MMIO base (physical) */
320 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
321 u32 plxsize; /* PLX registers MMIO size */
322 u32 scaphys; /* SCA registers MMIO base (physical) */
323 void __iomem * scabase; /* SCA registers MMIO base (virtual) */
324 u32 scasize; /* SCA registers MMIO size */
325 u32 ramphys; /* On-board RAM MMIO base (physical) */
326 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
327 u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
328 u32 ramsize; /* On-board RAM MMIO size */
329 u32 falcphys; /* FALC registers MMIO base (physical) */
330 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
331 u32 falcsize; /* FALC registers MMIO size */
332} pc300hw_t;
333
334typedef struct pc300chconf {
335 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
336 loopback mode */
337 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
338 u32 media; /* HW media (RS232, V.35, etc.) */
339 u32 proto; /* Protocol (PPP, X.25, etc.) */
340
341 /* TE-specific parameters */
342 u8 lcode; /* Line Code (AMI, B8ZS, etc.) */
343 u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */
344 u8 lbo; /* Line Build Out */
345 u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */
346 u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
347} pc300chconf_t;
348
349typedef struct pc300ch {
350 struct pc300 *card;
351 int channel;
352 pc300dev_t d;
353 pc300chconf_t conf;
354 u8 tx_first_bd; /* First TX DMA block descr. w/ data */
355 u8 tx_next_bd; /* Next free TX DMA block descriptor */
356 u8 rx_first_bd; /* First free RX DMA block descriptor */
357 u8 rx_last_bd; /* Last free RX DMA block descriptor */
358 u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */
359 falc_t falc; /* FALC structure (TE only) */
360} pc300ch_t;
361
362typedef struct pc300 {
363 pc300hw_t hw; /* hardware config. */
364 pc300ch_t chan[PC300_MAXCHAN];
365 spinlock_t card_lock;
366} pc300_t;
367
368typedef struct pc300conf {
369 pc300hw_t hw;
370 pc300chconf_t conf;
371} pc300conf_t;
372
373/* DEV ioctl() commands */
374#define N_SPPP_IOCTLS 2
375
376enum pc300_ioctl_cmds {
377 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
378 SIOCGPC300CONF,
379 SIOCSPC300CONF,
380 SIOCGPC300STATUS,
381 SIOCGPC300FALCSTATUS,
382 SIOCGPC300UTILSTATS,
383 SIOCGPC300UTILSTATUS,
384 SIOCSPC300TRACE,
385 SIOCSPC300LOOPBACK,
386 SIOCSPC300PATTERNTEST,
387};
388
389/* Loopback types - PC300/TE boards */
390enum pc300_loopback_cmds {
391 PC300LOCLOOP = 1,
392 PC300REMLOOP,
393 PC300PAYLOADLOOP,
394 PC300GENLOOPUP,
395 PC300GENLOOPDOWN,
396};
397
398/* Control Constant Definitions */
399#define PC300_RSV 0x01
400#define PC300_X21 0x02
401#define PC300_TE 0x03
402
403#define PC300_PCI 0x00
404#define PC300_PMC 0x01
405
406#define PC300_LC_AMI 0x01
407#define PC300_LC_B8ZS 0x02
408#define PC300_LC_NRZ 0x03
409#define PC300_LC_HDB3 0x04
410
411/* Framing (T1) */
412#define PC300_FR_ESF 0x01
413#define PC300_FR_D4 0x02
414#define PC300_FR_ESF_JAPAN 0x03
415
416/* Framing (E1) */
417#define PC300_FR_MF_CRC4 0x04
418#define PC300_FR_MF_NON_CRC4 0x05
419#define PC300_FR_UNFRAMED 0x06
420
421#define PC300_LBO_0_DB 0x00
422#define PC300_LBO_7_5_DB 0x01
423#define PC300_LBO_15_DB 0x02
424#define PC300_LBO_22_5_DB 0x03
425
426#define PC300_RX_SENS_SH 0x01
427#define PC300_RX_SENS_LH 0x02
428
429#define PC300_TX_TIMEOUT (2*HZ)
430#define PC300_TX_QUEUE_LEN 100
431#define PC300_DEF_MTU 1600
432
433/* Function Prototypes */
434int cpc_open(struct net_device *dev);
435
436#endif /* _PC300_H */