Loading...
Note: File does not exist in v6.8.
1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 *
6 * Description:
7 * Internal header file for UCC Gigabit Ethernet unit routines.
8 *
9 * Changelog:
10 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11 * - Rearrange code and style fixes
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef __UCC_GETH_H__
19#define __UCC_GETH_H__
20
21#include <linux/kernel.h>
22#include <linux/list.h>
23
24#include <asm/immap_qe.h>
25#include <asm/qe.h>
26
27#include <asm/ucc.h>
28#include <asm/ucc_fast.h>
29
30#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
31#define DRV_NAME "ucc_geth"
32#define DRV_VERSION "1.1"
33
34#define NUM_TX_QUEUES 8
35#define NUM_RX_QUEUES 8
36#define NUM_BDS_IN_PREFETCHED_BDS 4
37#define TX_IP_OFFSET_ENTRY_MAX 8
38#define NUM_OF_PADDRS 4
39#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
40#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
41
42struct ucc_geth {
43 struct ucc_fast uccf;
44 u8 res0[0x100 - sizeof(struct ucc_fast)];
45
46 u32 maccfg1; /* mac configuration reg. 1 */
47 u32 maccfg2; /* mac configuration reg. 2 */
48 u32 ipgifg; /* interframe gap reg. */
49 u32 hafdup; /* half-duplex reg. */
50 u8 res1[0x10];
51 u8 miimng[0x18]; /* MII management structure moved to _mii.h */
52 u32 ifctl; /* interface control reg */
53 u32 ifstat; /* interface statux reg */
54 u32 macstnaddr1; /* mac station address part 1 reg */
55 u32 macstnaddr2; /* mac station address part 2 reg */
56 u8 res2[0x8];
57 u32 uempr; /* UCC Ethernet Mac parameter reg */
58 u32 utbipar; /* UCC tbi address reg */
59 u16 uescr; /* UCC Ethernet statistics control reg */
60 u8 res3[0x180 - 0x15A];
61 u32 tx64; /* Total number of frames (including bad
62 frames) transmitted that were exactly of the
63 minimal length (64 for un tagged, 68 for
64 tagged, or with length exactly equal to the
65 parameter MINLength */
66 u32 tx127; /* Total number of frames (including bad
67 frames) transmitted that were between
68 MINLength (Including FCS length==4) and 127
69 octets */
70 u32 tx255; /* Total number of frames (including bad
71 frames) transmitted that were between 128
72 (Including FCS length==4) and 255 octets */
73 u32 rx64; /* Total number of frames received including
74 bad frames that were exactly of the mninimal
75 length (64 bytes) */
76 u32 rx127; /* Total number of frames (including bad
77 frames) received that were between MINLength
78 (Including FCS length==4) and 127 octets */
79 u32 rx255; /* Total number of frames (including bad
80 frames) received that were between 128
81 (Including FCS length==4) and 255 octets */
82 u32 txok; /* Total number of octets residing in frames
83 that where involved in successful
84 transmission */
85 u16 txcf; /* Total number of PAUSE control frames
86 transmitted by this MAC */
87 u8 res4[0x2];
88 u32 tmca; /* Total number of frames that were transmitted
89 successfully with the group address bit set
90 that are not broadcast frames */
91 u32 tbca; /* Total number of frames transmitted
92 successfully that had destination address
93 field equal to the broadcast address */
94 u32 rxfok; /* Total number of frames received OK */
95 u32 rxbok; /* Total number of octets received OK */
96 u32 rbyt; /* Total number of octets received including
97 octets in bad frames. Must be implemented in
98 HW because it includes octets in frames that
99 never even reach the UCC */
100 u32 rmca; /* Total number of frames that were received
101 successfully with the group address bit set
102 that are not broadcast frames */
103 u32 rbca; /* Total number of frames received successfully
104 that had destination address equal to the
105 broadcast address */
106 u32 scar; /* Statistics carry register */
107 u32 scam; /* Statistics caryy mask register */
108 u8 res5[0x200 - 0x1c4];
109} __packed;
110
111/* UCC GETH TEMODR Register */
112#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
113 */
114#define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */
115#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4
116 checksums */
117#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance
118 optimization
119 enhancement (mode1) */
120#define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics
121 */
122#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
123 shift */
124
125/* UCC GETH TEMODR Register */
126#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx
127 statistics */
128#define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable
129 extended
130 features */
131#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
132 tagged << shift */
133#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
134 tagged << shift */
135#define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
136 */
137#define REMODER_RMON_STATISTICS 0x00001000 /* enable rx
138 statistics */
139#define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended
140 filtering
141 vs.
142 mpc82xx-like
143 filtering */
144#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
145 shift */
146#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable
147 dynamic max
148 frame length
149 */
150#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable
151 dynamic min
152 frame length
153 */
154#define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4
155 checksums */
156#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip
157 address to
158 4-byte
159 boundary */
160
161/* UCC GETH Event Register */
162#define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
163 UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
164 UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
165 UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
166
167#define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
168 UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
169 UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
170 UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
171
172#define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
173 UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
174 UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
175 UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
176
177#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
178 UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
179 UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
180
181#define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY)
182#define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE)
183
184/* TBI defines */
185#define ENET_TBI_MII_CR 0x00 /* Control */
186#define ENET_TBI_MII_SR 0x01 /* Status */
187#define ENET_TBI_MII_ANA 0x04 /* AN advertisement */
188#define ENET_TBI_MII_ANLPBPA 0x05 /* AN link partner base page ability */
189#define ENET_TBI_MII_ANEX 0x06 /* AN expansion */
190#define ENET_TBI_MII_ANNPT 0x07 /* AN next page transmit */
191#define ENET_TBI_MII_ANLPANP 0x08 /* AN link partner ability next page */
192#define ENET_TBI_MII_EXST 0x0F /* Extended status */
193#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
194#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
195
196/* TBI MDIO register bit fields*/
197#define TBISR_LSTATUS 0x0004
198#define TBICON_CLK_SELECT 0x0020
199#define TBIANA_ASYMMETRIC_PAUSE 0x0100
200#define TBIANA_SYMMETRIC_PAUSE 0x0080
201#define TBIANA_HALF_DUPLEX 0x0040
202#define TBIANA_FULL_DUPLEX 0x0020
203#define TBICR_PHY_RESET 0x8000
204#define TBICR_ANEG_ENABLE 0x1000
205#define TBICR_RESTART_ANEG 0x0200
206#define TBICR_FULL_DUPLEX 0x0100
207#define TBICR_SPEED1_SET 0x0040
208
209#define TBIANA_SETTINGS ( \
210 TBIANA_ASYMMETRIC_PAUSE \
211 | TBIANA_SYMMETRIC_PAUSE \
212 | TBIANA_FULL_DUPLEX \
213 )
214#define TBICR_SETTINGS ( \
215 TBICR_PHY_RESET \
216 | TBICR_ANEG_ENABLE \
217 | TBICR_FULL_DUPLEX \
218 | TBICR_SPEED1_SET \
219 )
220
221/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
222#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
223 Rx */
224#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control
225 Tx */
226#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable
227 synchronized
228 to Rx stream
229 */
230#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
231#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable
232 synchronized
233 to Tx stream
234 */
235#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
236
237/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
238#define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
239 Length <<
240 shift */
241#define MACCFG2_PREL_MASK 0x0000f000 /* Preamble
242 Length mask */
243#define MACCFG2_SRP 0x00000080 /* Soft Receive
244 Preamble */
245#define MACCFG2_STP 0x00000040 /* Soft
246 Transmit
247 Preamble */
248#define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
249 must be set
250 to 1 */
251#define MACCFG2_LC 0x00000010 /* Length Check
252 */
253#define MACCFG2_MPE 0x00000008 /* Magic packet
254 detect */
255#define MACCFG2_FDX 0x00000001 /* Full Duplex */
256#define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex
257 mask */
258#define MACCFG2_PAD_CRC 0x00000004
259#define MACCFG2_CRC_EN 0x00000002
260#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither
261 Padding
262 short frames
263 nor CRC */
264#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC
265 only */
266#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
267#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode
268 (MII/RMII/RGMII
269 10/100bps) */
270#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode
271 (GMII/TBI/RTB/RGMII
272 1000bps ) */
273#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask
274 covering all
275 relevant
276 bits */
277
278/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
279#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
280 back-to-back
281 inter frame
282 gap part 1.
283 << shift */
284#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
285 back-to-back
286 inter frame
287 gap part 2.
288 << shift */
289#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
290 Enforcement
291 << shift */
292#define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
293 inter frame
294 gap << shift
295 */
296#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
297 inter frame gap part
298 1. max val */
299#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
300 inter frame gap part
301 2. max val */
302#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG
303 Enforcement max val */
304#define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
305 frame gap max val */
306#define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000
307#define IPGIFG_NBTB_IPG_MASK 0x007F0000
308#define IPGIFG_MIN_IFG_MASK 0x0000FF00
309#define IPGIFG_BTB_IPG_MASK 0x0000007F
310
311/* UCC GETH HAFDUP (Half Duplex Register) */
312#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
313 Binary
314 Exponential
315 Backoff
316 Truncation
317 << shift */
318#define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary
319 Exponential Backoff
320 Truncation max val */
321#define HALFDUP_ALT_BEB 0x00080000 /* Alternate
322 Binary
323 Exponential
324 Backoff */
325#define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back
326 pressure no
327 backoff */
328#define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */
329#define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive
330 Defer */
331#define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
332 Retransmission
333 << shift */
334#define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum
335 Retransmission max
336 val */
337#define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
338 Window <<
339 shift */
340#define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max
341 val */
342#define HALFDUP_ALT_BEB_TR_MASK 0x00F00000
343#define HALFDUP_RETRANS_MASK 0x0000F000
344#define HALFDUP_COL_WINDOW_MASK 0x0000003F
345
346/* UCC GETH UCCS (Ethernet Status Register) */
347#define UCCS_BPR 0x02 /* Back pressure (in
348 half duplex mode) */
349#define UCCS_PAU 0x02 /* Pause state (in full
350 duplex mode) */
351#define UCCS_MPD 0x01 /* Magic Packet
352 Detected */
353
354/* UCC GETH IFSTAT (Interface Status Register) */
355#define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive
356 transmission
357 defer */
358
359/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
360#define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
361 address 6th
362 octet <<
363 shift */
364#define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
365 address 5th
366 octet <<
367 shift */
368#define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
369 address 4th
370 octet <<
371 shift */
372#define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
373 address 3rd
374 octet <<
375 shift */
376
377/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
378#define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
379 address 2nd
380 octet <<
381 shift */
382#define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
383 address 1st
384 octet <<
385 shift */
386
387/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
388#define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
389 value <<
390 shift */
391#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
392 pause time
393 value <<
394 shift */
395
396/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
397#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
398 << shift */
399#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address
400 mask */
401
402/* UCC GETH UESCR (Ethernet Statistics Control Register) */
403#define UESCR_AUTOZ 0x8000 /* Automatically zero
404 addressed
405 statistical counter
406 values */
407#define UESCR_CLRCNT 0x4000 /* Clear all statistics
408 counters */
409#define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
410 Coalescing
411 Value <<
412 shift */
413#define UESCR_SCOV_SHIFT (15 - 15) /* Status
414 Coalescing
415 Value <<
416 shift */
417
418/* UCC GETH UDSR (Data Synchronization Register) */
419#define UDSR_MAGIC 0x067E
420
421struct ucc_geth_thread_data_tx {
422 u8 res0[104];
423} __packed;
424
425struct ucc_geth_thread_data_rx {
426 u8 res0[40];
427} __packed;
428
429/* Send Queue Queue-Descriptor */
430struct ucc_geth_send_queue_qd {
431 u32 bd_ring_base; /* pointer to BD ring base address */
432 u8 res0[0x8];
433 u32 last_bd_completed_address;/* initialize to last entry in BD ring */
434 u8 res1[0x30];
435} __packed;
436
437struct ucc_geth_send_queue_mem_region {
438 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
439} __packed;
440
441struct ucc_geth_thread_tx_pram {
442 u8 res0[64];
443} __packed;
444
445struct ucc_geth_thread_rx_pram {
446 u8 res0[128];
447} __packed;
448
449#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
450#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
451#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
452
453struct ucc_geth_scheduler {
454 u16 cpucount0; /* CPU packet counter */
455 u16 cpucount1; /* CPU packet counter */
456 u16 cecount0; /* QE packet counter */
457 u16 cecount1; /* QE packet counter */
458 u16 cpucount2; /* CPU packet counter */
459 u16 cpucount3; /* CPU packet counter */
460 u16 cecount2; /* QE packet counter */
461 u16 cecount3; /* QE packet counter */
462 u16 cpucount4; /* CPU packet counter */
463 u16 cpucount5; /* CPU packet counter */
464 u16 cecount4; /* QE packet counter */
465 u16 cecount5; /* QE packet counter */
466 u16 cpucount6; /* CPU packet counter */
467 u16 cpucount7; /* CPU packet counter */
468 u16 cecount6; /* QE packet counter */
469 u16 cecount7; /* QE packet counter */
470 u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */
471 u32 rtsrshadow; /* temporary variable handled by QE */
472 u32 time; /* temporary variable handled by QE */
473 u32 ttl; /* temporary variable handled by QE */
474 u32 mblinterval; /* max burst length interval */
475 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
476 u8 fracsiz; /* radix 2 log value of denom. of
477 NorTSRByteTime */
478 u8 res0[1];
479 u8 strictpriorityq; /* Strict Priority Mask register */
480 u8 txasap; /* Transmit ASAP register */
481 u8 extrabw; /* Extra BandWidth register */
482 u8 oldwfqmask; /* temporary variable handled by QE */
483 u8 weightfactor[NUM_TX_QUEUES];
484 /**< weight factor for queues */
485 u32 minw; /* temporary variable handled by QE */
486 u8 res1[0x70 - 0x64];
487} __packed;
488
489struct ucc_geth_tx_firmware_statistics_pram {
490 u32 sicoltx; /* single collision */
491 u32 mulcoltx; /* multiple collision */
492 u32 latecoltxfr; /* late collision */
493 u32 frabortduecol; /* frames aborted due to transmit collision */
494 u32 frlostinmactxer; /* frames lost due to internal MAC error
495 transmission that are not counted on any
496 other counter */
497 u32 carriersenseertx; /* carrier sense error */
498 u32 frtxok; /* frames transmitted OK */
499 u32 txfrexcessivedefer; /* frames with defferal time greater than
500 specified threshold */
501 u32 txpkts256; /* total packets (including bad) between 256
502 and 511 octets */
503 u32 txpkts512; /* total packets (including bad) between 512
504 and 1023 octets */
505 u32 txpkts1024; /* total packets (including bad) between 1024
506 and 1518 octets */
507 u32 txpktsjumbo; /* total packets (including bad) between 1024
508 and MAXLength octets */
509} __packed;
510
511struct ucc_geth_rx_firmware_statistics_pram {
512 u32 frrxfcser; /* frames with crc error */
513 u32 fraligner; /* frames with alignment error */
514 u32 inrangelenrxer; /* in range length error */
515 u32 outrangelenrxer; /* out of range length error */
516 u32 frtoolong; /* frame too long */
517 u32 runt; /* runt */
518 u32 verylongevent; /* very long event */
519 u32 symbolerror; /* symbol error */
520 u32 dropbsy; /* drop because of BD not ready */
521 u8 res0[0x8];
522 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
523 or type mismatch) */
524 u32 underpkts; /* total frames less than 64 octets */
525 u32 pkts256; /* total frames (including bad) between 256 and
526 511 octets */
527 u32 pkts512; /* total frames (including bad) between 512 and
528 1023 octets */
529 u32 pkts1024; /* total frames (including bad) between 1024
530 and 1518 octets */
531 u32 pktsjumbo; /* total frames (including bad) between 1024
532 and MAXLength octets */
533 u32 frlossinmacer; /* frames lost because of internal MAC error
534 that is not counted in any other counter */
535 u32 pausefr; /* pause frames */
536 u8 res1[0x4];
537 u32 removevlan; /* total frames that had their VLAN tag removed
538 */
539 u32 replacevlan; /* total frames that had their VLAN tag
540 replaced */
541 u32 insertvlan; /* total frames that had their VLAN tag
542 inserted */
543} __packed;
544
545struct ucc_geth_rx_interrupt_coalescing_entry {
546 u32 interruptcoalescingmaxvalue; /* interrupt coalescing max
547 value */
548 u32 interruptcoalescingcounter; /* interrupt coalescing counter,
549 initialize to
550 interruptcoalescingmaxvalue */
551} __packed;
552
553struct ucc_geth_rx_interrupt_coalescing_table {
554 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
555 /**< interrupt coalescing entry */
556} __packed;
557
558struct ucc_geth_rx_prefetched_bds {
559 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
560} __packed;
561
562struct ucc_geth_rx_bd_queues_entry {
563 u32 bdbaseptr; /* BD base pointer */
564 u32 bdptr; /* BD pointer */
565 u32 externalbdbaseptr; /* external BD base pointer */
566 u32 externalbdptr; /* external BD pointer */
567} __packed;
568
569struct ucc_geth_tx_global_pram {
570 u16 temoder;
571 u8 res0[0x38 - 0x02];
572 u32 sqptr; /* a base pointer to send queue memory region */
573 u32 schedulerbasepointer; /* a base pointer to scheduler memory
574 region */
575 u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */
576 u32 tstate; /* tx internal state. High byte contains
577 function code */
578 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
579 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
580 u32 tqptr; /* a base pointer to the Tx Queues Memory
581 Region */
582 u8 res2[0x80 - 0x74];
583} __packed;
584
585/* structure representing Extended Filtering Global Parameters in PRAM */
586struct ucc_geth_exf_global_pram {
587 u32 l2pcdptr; /* individual address filter, high */
588 u8 res0[0x10 - 0x04];
589} __packed;
590
591struct ucc_geth_rx_global_pram {
592 u32 remoder; /* ethernet mode reg. */
593 u32 rqptr; /* base pointer to the Rx Queues Memory Region*/
594 u32 res0[0x1];
595 u8 res1[0x20 - 0xC];
596 u16 typeorlen; /* cutoff point less than which, type/len field
597 is considered length */
598 u8 res2[0x1];
599 u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/
600 u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */
601 u8 res3[0x30 - 0x28];
602 u32 intcoalescingptr; /* Interrupt coalescing table pointer */
603 u8 res4[0x36 - 0x34];
604 u8 rstate; /* rx internal state. High byte contains
605 function code */
606 u8 res5[0x46 - 0x37];
607 u16 mrblr; /* max receive buffer length reg. */
608 u32 rbdqptr; /* base pointer to RxBD parameter table
609 description */
610 u16 mflr; /* max frame length reg. */
611 u16 minflr; /* min frame length reg. */
612 u16 maxd1; /* max dma1 length reg. */
613 u16 maxd2; /* max dma2 length reg. */
614 u32 ecamptr; /* external CAM address */
615 u32 l2qt; /* VLAN priority mapping table. */
616 u32 l3qt[0x8]; /* IP priority mapping table. */
617 u16 vlantype; /* vlan type */
618 u16 vlantci; /* default vlan tci */
619 u8 addressfiltering[64]; /* address filtering data structure */
620 u32 exfGlobalParam; /* base address for extended filtering global
621 parameters */
622 u8 res6[0x100 - 0xC4]; /* Initialize to zero */
623} __packed;
624
625#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
626
627/* structure representing InitEnet command */
628struct ucc_geth_init_pram {
629 u8 resinit1;
630 u8 resinit2;
631 u8 resinit3;
632 u8 resinit4;
633 u16 resinit5;
634 u8 res1[0x1];
635 u8 largestexternallookupkeysize;
636 u32 rgftgfrxglobal;
637 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */
638 u8 res2[0x38 - 0x30];
639 u32 txglobal; /* tx global */
640 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */
641 u8 res3[0x1];
642} __packed;
643
644#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
645#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
646
647#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
648#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
649#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
650#define ENET_INIT_PARAM_SNUM_SHIFT 24
651
652#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06
653#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30
654#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff
655#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00
656#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
657
658/* structure representing 82xx Address Filtering Enet Address in PRAM */
659struct ucc_geth_82xx_enet_address {
660 u8 res1[0x2];
661 u16 h; /* address (MSB) */
662 u16 m; /* address */
663 u16 l; /* address (LSB) */
664} __packed;
665
666/* structure representing 82xx Address Filtering PRAM */
667struct ucc_geth_82xx_address_filtering_pram {
668 u32 iaddr_h; /* individual address filter, high */
669 u32 iaddr_l; /* individual address filter, low */
670 u32 gaddr_h; /* group address filter, high */
671 u32 gaddr_l; /* group address filter, low */
672 struct ucc_geth_82xx_enet_address __iomem taddr;
673 struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
674 u8 res0[0x40 - 0x38];
675} __packed;
676
677/* GETH Tx firmware statistics structure, used when calling
678 UCC_GETH_GetStatistics. */
679struct ucc_geth_tx_firmware_statistics {
680 u32 sicoltx; /* single collision */
681 u32 mulcoltx; /* multiple collision */
682 u32 latecoltxfr; /* late collision */
683 u32 frabortduecol; /* frames aborted due to transmit collision */
684 u32 frlostinmactxer; /* frames lost due to internal MAC error
685 transmission that are not counted on any
686 other counter */
687 u32 carriersenseertx; /* carrier sense error */
688 u32 frtxok; /* frames transmitted OK */
689 u32 txfrexcessivedefer; /* frames with defferal time greater than
690 specified threshold */
691 u32 txpkts256; /* total packets (including bad) between 256
692 and 511 octets */
693 u32 txpkts512; /* total packets (including bad) between 512
694 and 1023 octets */
695 u32 txpkts1024; /* total packets (including bad) between 1024
696 and 1518 octets */
697 u32 txpktsjumbo; /* total packets (including bad) between 1024
698 and MAXLength octets */
699} __packed;
700
701/* GETH Rx firmware statistics structure, used when calling
702 UCC_GETH_GetStatistics. */
703struct ucc_geth_rx_firmware_statistics {
704 u32 frrxfcser; /* frames with crc error */
705 u32 fraligner; /* frames with alignment error */
706 u32 inrangelenrxer; /* in range length error */
707 u32 outrangelenrxer; /* out of range length error */
708 u32 frtoolong; /* frame too long */
709 u32 runt; /* runt */
710 u32 verylongevent; /* very long event */
711 u32 symbolerror; /* symbol error */
712 u32 dropbsy; /* drop because of BD not ready */
713 u8 res0[0x8];
714 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
715 or type mismatch) */
716 u32 underpkts; /* total frames less than 64 octets */
717 u32 pkts256; /* total frames (including bad) between 256 and
718 511 octets */
719 u32 pkts512; /* total frames (including bad) between 512 and
720 1023 octets */
721 u32 pkts1024; /* total frames (including bad) between 1024
722 and 1518 octets */
723 u32 pktsjumbo; /* total frames (including bad) between 1024
724 and MAXLength octets */
725 u32 frlossinmacer; /* frames lost because of internal MAC error
726 that is not counted in any other counter */
727 u32 pausefr; /* pause frames */
728 u8 res1[0x4];
729 u32 removevlan; /* total frames that had their VLAN tag removed
730 */
731 u32 replacevlan; /* total frames that had their VLAN tag
732 replaced */
733 u32 insertvlan; /* total frames that had their VLAN tag
734 inserted */
735} __packed;
736
737/* GETH hardware statistics structure, used when calling
738 UCC_GETH_GetStatistics. */
739struct ucc_geth_hardware_statistics {
740 u32 tx64; /* Total number of frames (including bad
741 frames) transmitted that were exactly of the
742 minimal length (64 for un tagged, 68 for
743 tagged, or with length exactly equal to the
744 parameter MINLength */
745 u32 tx127; /* Total number of frames (including bad
746 frames) transmitted that were between
747 MINLength (Including FCS length==4) and 127
748 octets */
749 u32 tx255; /* Total number of frames (including bad
750 frames) transmitted that were between 128
751 (Including FCS length==4) and 255 octets */
752 u32 rx64; /* Total number of frames received including
753 bad frames that were exactly of the mninimal
754 length (64 bytes) */
755 u32 rx127; /* Total number of frames (including bad
756 frames) received that were between MINLength
757 (Including FCS length==4) and 127 octets */
758 u32 rx255; /* Total number of frames (including bad
759 frames) received that were between 128
760 (Including FCS length==4) and 255 octets */
761 u32 txok; /* Total number of octets residing in frames
762 that where involved in successful
763 transmission */
764 u16 txcf; /* Total number of PAUSE control frames
765 transmitted by this MAC */
766 u32 tmca; /* Total number of frames that were transmitted
767 successfully with the group address bit set
768 that are not broadcast frames */
769 u32 tbca; /* Total number of frames transmitted
770 successfully that had destination address
771 field equal to the broadcast address */
772 u32 rxfok; /* Total number of frames received OK */
773 u32 rxbok; /* Total number of octets received OK */
774 u32 rbyt; /* Total number of octets received including
775 octets in bad frames. Must be implemented in
776 HW because it includes octets in frames that
777 never even reach the UCC */
778 u32 rmca; /* Total number of frames that were received
779 successfully with the group address bit set
780 that are not broadcast frames */
781 u32 rbca; /* Total number of frames received successfully
782 that had destination address equal to the
783 broadcast address */
784} __packed;
785
786/* UCC GETH Tx errors returned via TxConf callback */
787#define TX_ERRORS_DEF 0x0200
788#define TX_ERRORS_EXDEF 0x0100
789#define TX_ERRORS_LC 0x0080
790#define TX_ERRORS_RL 0x0040
791#define TX_ERRORS_RC_MASK 0x003C
792#define TX_ERRORS_RC_SHIFT 2
793#define TX_ERRORS_UN 0x0002
794#define TX_ERRORS_CSL 0x0001
795
796/* UCC GETH Rx errors returned via RxStore callback */
797#define RX_ERRORS_CMR 0x0200
798#define RX_ERRORS_M 0x0100
799#define RX_ERRORS_BC 0x0080
800#define RX_ERRORS_MC 0x0040
801
802/* Transmit BD. These are in addition to values defined in uccf. */
803#define T_VID 0x003c0000 /* insert VLAN id index mask. */
804#define T_DEF (((u32) TX_ERRORS_DEF ) << 16)
805#define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)
806#define T_LC (((u32) TX_ERRORS_LC ) << 16)
807#define T_RL (((u32) TX_ERRORS_RL ) << 16)
808#define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)
809#define T_UN (((u32) TX_ERRORS_UN ) << 16)
810#define T_CSL (((u32) TX_ERRORS_CSL ) << 16)
811#define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
812 | T_UN | T_CSL) /* transmit errors to report */
813
814/* Receive BD. These are in addition to values defined in uccf. */
815#define R_LG 0x00200000 /* Frame length violation. */
816#define R_NO 0x00100000 /* Non-octet aligned frame. */
817#define R_SH 0x00080000 /* Short frame. */
818#define R_CR 0x00040000 /* CRC error. */
819#define R_OV 0x00020000 /* Overrun. */
820#define R_IPCH 0x00010000 /* IP checksum check failed. */
821#define R_CMR (((u32) RX_ERRORS_CMR ) << 16)
822#define R_M (((u32) RX_ERRORS_M ) << 16)
823#define R_BC (((u32) RX_ERRORS_BC ) << 16)
824#define R_MC (((u32) RX_ERRORS_MC ) << 16)
825#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to
826 report */
827#define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
828 R_OV | R_IPCH) /* receive errors to discard */
829
830/* Alignments */
831#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256
832#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128
833#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128
834#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64
835#define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values
836 based on num of
837 threads, but always
838 using the maximum is
839 easier */
840#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
841#define UCC_GETH_SCHEDULER_ALIGNMENT 8 /* This is a guess */
842#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
843#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
844#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
845#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
846#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
847#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8 /* This
848 is a
849 guess
850 */
851#define UCC_GETH_RX_BD_RING_ALIGNMENT 32
852#define UCC_GETH_TX_BD_RING_ALIGNMENT 32
853#define UCC_GETH_MRBLR_ALIGNMENT 128
854#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4
855#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
856#define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64
857
858#define UCC_GETH_TAD_EF 0x80
859#define UCC_GETH_TAD_V 0x40
860#define UCC_GETH_TAD_REJ 0x20
861#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2
862#define UCC_GETH_TAD_VTAG_OP_SHIFT 6
863#define UCC_GETH_TAD_V_NON_VTAG_OP 0x20
864#define UCC_GETH_TAD_RQOS_SHIFT 0
865#define UCC_GETH_TAD_V_PRIORITY_SHIFT 5
866#define UCC_GETH_TAD_CFI 0x10
867
868#define UCC_GETH_VLAN_PRIORITY_MAX 8
869#define UCC_GETH_IP_PRIORITY_MAX 64
870#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8
871#define UCC_GETH_RX_BD_RING_SIZE_MIN 8
872#define UCC_GETH_TX_BD_RING_SIZE_MIN 2
873#define UCC_GETH_BD_RING_SIZE_MAX 0xffff
874
875#define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
876
877/* Driver definitions */
878#define TX_BD_RING_LEN 0x10
879#define RX_BD_RING_LEN 0x10
880
881#define TX_RING_MOD_MASK(size) (size-1)
882#define RX_RING_MOD_MASK(size) (size-1)
883
884#define ENET_NUM_OCTETS_PER_ADDRESS 6
885#define ENET_GROUP_ADDR 0x01 /* Group address mask
886 for ethernet
887 addresses */
888
889#define TX_TIMEOUT (1*HZ)
890#define SKB_ALLOC_TIMEOUT 100000
891#define PHY_INIT_TIMEOUT 100000
892#define PHY_CHANGE_TIME 2
893
894/* Fast Ethernet (10/100 Mbps) */
895#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size
896 */
897#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
898#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
899#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size
900 */
901#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
902#define UCC_GETH_UTFTT_INIT 256 /* 1/2 utfs
903 due to errata */
904/* Gigabit Ethernet (1000 Mbps) */
905#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual
906 FIFO size */
907#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
908#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
909#define UCC_GETH_UTFS_GIGA_INIT 4096/*2048*/ /* Tx virtual
910 FIFO size */
911#define UCC_GETH_UTFET_GIGA_INIT 2048/*1024*/ /* 1/2 utfs */
912#define UCC_GETH_UTFTT_GIGA_INIT 4096/*0x40*/ /* Tx virtual
913 FIFO size */
914
915#define UCC_GETH_REMODER_INIT 0 /* bits that must be
916 set */
917#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */
918
919/* Initial value for UPSMR */
920#define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1
921
922#define UCC_GETH_MACCFG1_INIT 0
923#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
924
925/* Ethernet Address Type. */
926enum enet_addr_type {
927 ENET_ADDR_TYPE_INDIVIDUAL,
928 ENET_ADDR_TYPE_GROUP,
929 ENET_ADDR_TYPE_BROADCAST
930};
931
932/* UCC GETH 82xx Ethernet Address Recognition Location */
933enum ucc_geth_enet_address_recognition_location {
934 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
935 address */
936 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
937 station
938 address
939 paddr1 */
940 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional
941 station
942 address
943 paddr2 */
944 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional
945 station
946 address
947 paddr3 */
948 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional
949 station
950 address
951 paddr4 */
952 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */
953 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
954 hash */
955};
956
957/* UCC GETH vlan operation tagged */
958enum ucc_geth_vlan_operation_tagged {
959 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
960 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
961 = 0x1, /* Tagged - replace vid portion of q tag */
962 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
963 = 0x2, /* Tagged - if vid0 replace vid with default value */
964 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
965 = 0x3 /* Tagged - extract q tag from frame */
966};
967
968/* UCC GETH vlan operation non-tagged */
969enum ucc_geth_vlan_operation_non_tagged {
970 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
971 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
972 q tag insert
973 */
974};
975
976/* UCC GETH Rx Quality of Service Mode */
977enum ucc_geth_qos_mode {
978 UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */
979 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
980 determined
981 by L2
982 criteria */
983 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue
984 determined
985 by L3
986 criteria */
987};
988
989/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
990 for combined functionality */
991enum ucc_geth_statistics_gathering_mode {
992 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No
993 statistics
994 gathering */
995 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
996 hardware
997 statistics
998 gathering
999 */
1000 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1001 firmware
1002 tx
1003 statistics
1004 gathering
1005 */
1006 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1007 firmware
1008 rx
1009 statistics
1010 gathering
1011 */
1012};
1013
1014/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1015enum ucc_geth_maccfg2_pad_and_crc_mode {
1016 UCC_GETH_PAD_AND_CRC_MODE_NONE
1017 = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding
1018 short frames
1019 nor CRC */
1020 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1021 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append
1022 CRC only */
1023 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1024 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1025};
1026
1027/* UCC GETH upsmr Flow Control Mode */
1028enum ucc_geth_flow_control_mode {
1029 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic
1030 flow control
1031 */
1032 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1033 = 0x00004000 /* Send pause frame when RxFIFO reaches its
1034 emergency threshold */
1035};
1036
1037/* UCC GETH number of threads */
1038enum ucc_geth_num_of_threads {
1039 UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */
1040 UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */
1041 UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */
1042 UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */
1043 UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1044};
1045
1046/* UCC GETH number of station addresses */
1047enum ucc_geth_num_of_station_addresses {
1048 UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */
1049 UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
1050};
1051
1052/* UCC GETH 82xx Ethernet Address Container */
1053struct enet_addr_container {
1054 u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1055 enum ucc_geth_enet_address_recognition_location location; /* location in
1056 82xx address
1057 recognition
1058 hardware */
1059 struct list_head node;
1060};
1061
1062#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1063
1064/* UCC GETH Termination Action Descriptor (TAD) structure. */
1065struct ucc_geth_tad_params {
1066 int rx_non_dynamic_extended_features_mode;
1067 int reject_frame;
1068 enum ucc_geth_vlan_operation_tagged vtag_op;
1069 enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1070 enum ucc_geth_qos_mode rqos;
1071 u8 vpri;
1072 u16 vid;
1073};
1074
1075/* GETH protocol initialization structure */
1076struct ucc_geth_info {
1077 struct ucc_fast_info uf_info;
1078 u8 numQueuesTx;
1079 u8 numQueuesRx;
1080 int ipCheckSumCheck;
1081 int ipCheckSumGenerate;
1082 int rxExtendedFiltering;
1083 u32 extendedFilteringChainPointer;
1084 u16 typeorlen;
1085 int dynamicMaxFrameLength;
1086 int dynamicMinFrameLength;
1087 u8 nonBackToBackIfgPart1;
1088 u8 nonBackToBackIfgPart2;
1089 u8 miminumInterFrameGapEnforcement;
1090 u8 backToBackInterFrameGap;
1091 int ipAddressAlignment;
1092 int lengthCheckRx;
1093 u32 mblinterval;
1094 u16 nortsrbytetime;
1095 u8 fracsiz;
1096 u8 strictpriorityq;
1097 u8 txasap;
1098 u8 extrabw;
1099 int miiPreambleSupress;
1100 u8 altBebTruncation;
1101 int altBeb;
1102 int backPressureNoBackoff;
1103 int noBackoff;
1104 int excessDefer;
1105 u8 maxRetransmission;
1106 u8 collisionWindow;
1107 int pro;
1108 int cap;
1109 int rsh;
1110 int rlpb;
1111 int cam;
1112 int bro;
1113 int ecm;
1114 int receiveFlowControl;
1115 int transmitFlowControl;
1116 u8 maxGroupAddrInHash;
1117 u8 maxIndAddrInHash;
1118 u8 prel;
1119 u16 maxFrameLength;
1120 u16 minFrameLength;
1121 u16 maxD1Length;
1122 u16 maxD2Length;
1123 u16 vlantype;
1124 u16 vlantci;
1125 u32 ecamptr;
1126 u32 eventRegMask;
1127 u16 pausePeriod;
1128 u16 extensionField;
1129 struct device_node *phy_node;
1130 struct device_node *tbi_node;
1131 u8 weightfactor[NUM_TX_QUEUES];
1132 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1133 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1134 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1135 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1136 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1137 u16 bdRingLenTx[NUM_TX_QUEUES];
1138 u16 bdRingLenRx[NUM_RX_QUEUES];
1139 enum ucc_geth_num_of_station_addresses numStationAddresses;
1140 enum qe_fltr_largest_external_tbl_lookup_key_size
1141 largestexternallookupkeysize;
1142 enum ucc_geth_statistics_gathering_mode statisticsMode;
1143 enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1144 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1145 enum ucc_geth_qos_mode rxQoSMode;
1146 enum ucc_geth_flow_control_mode aufc;
1147 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1148 enum ucc_geth_num_of_threads numThreadsTx;
1149 enum ucc_geth_num_of_threads numThreadsRx;
1150 unsigned int riscTx;
1151 unsigned int riscRx;
1152};
1153
1154/* structure representing UCC GETH */
1155struct ucc_geth_private {
1156 struct ucc_geth_info *ug_info;
1157 struct ucc_fast_private *uccf;
1158 struct device *dev;
1159 struct net_device *ndev;
1160 struct napi_struct napi;
1161 struct work_struct timeout_work;
1162 struct ucc_geth __iomem *ug_regs;
1163 struct ucc_geth_init_pram *p_init_enet_param_shadow;
1164 struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1165 u32 exf_glbl_param_offset;
1166 struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1167 u32 rx_glbl_pram_offset;
1168 struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1169 u32 tx_glbl_pram_offset;
1170 struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1171 u32 send_q_mem_reg_offset;
1172 struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1173 u32 thread_dat_tx_offset;
1174 struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1175 u32 thread_dat_rx_offset;
1176 struct ucc_geth_scheduler __iomem *p_scheduler;
1177 u32 scheduler_offset;
1178 struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1179 u32 tx_fw_statistics_pram_offset;
1180 struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1181 u32 rx_fw_statistics_pram_offset;
1182 struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1183 u32 rx_irq_coalescing_tbl_offset;
1184 struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1185 u32 rx_bd_qs_tbl_offset;
1186 u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1187 u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1188 u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1189 u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1190 u8 __iomem *confBd[NUM_TX_QUEUES];
1191 u8 __iomem *txBd[NUM_TX_QUEUES];
1192 u8 __iomem *rxBd[NUM_RX_QUEUES];
1193 int badFrame[NUM_RX_QUEUES];
1194 u16 cpucount[NUM_TX_QUEUES];
1195 u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1196 int indAddrRegUsed[NUM_OF_PADDRS];
1197 u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1198 u8 numGroupAddrInHash;
1199 u8 numIndAddrInHash;
1200 u8 numIndAddrInReg;
1201 int rx_extended_features;
1202 int rx_non_dynamic_extended_features;
1203 struct list_head conf_skbs;
1204 struct list_head group_hash_q;
1205 struct list_head ind_hash_q;
1206 u32 saved_uccm;
1207 spinlock_t lock;
1208 /* pointers to arrays of skbuffs for tx and rx */
1209 struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1210 struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1211 /* indices pointing to the next free sbk in skb arrays */
1212 u16 skb_curtx[NUM_TX_QUEUES];
1213 u16 skb_currx[NUM_RX_QUEUES];
1214 /* index of the first skb which hasn't been transmitted yet. */
1215 u16 skb_dirtytx[NUM_TX_QUEUES];
1216
1217 struct sk_buff_head rx_recycle;
1218
1219 struct ugeth_mii_info *mii_info;
1220 struct phy_device *phydev;
1221 phy_interface_t phy_interface;
1222 int max_speed;
1223 uint32_t msg_enable;
1224 int oldspeed;
1225 int oldduplex;
1226 int oldlink;
1227 int wol_en;
1228
1229 struct device_node *node;
1230};
1231
1232void uec_set_ethtool_ops(struct net_device *netdev);
1233int init_flow_control_params(u32 automatic_flow_control_mode,
1234 int rx_flow_control_enable, int tx_flow_control_enable,
1235 u16 pause_period, u16 extension_field,
1236 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1237 u32 __iomem *maccfg1_register);
1238
1239
1240#endif /* __UCC_GETH_H__ */