Loading...
Note: File does not exist in v6.8.
1/* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
2/*
3 Written 1998-2000 by Donald Becker.
4
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
8
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
15
16 The information below comes from Donald Becker's original driver:
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
26
27*/
28
29#define DRV_NAME "starfire"
30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "July 6, 2008"
32
33#include <linux/interrupt.h>
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/pci.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/crc32.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/if_vlan.h>
45#include <linux/mm.h>
46#include <linux/firmware.h>
47#include <asm/processor.h> /* Processor type for cache alignment. */
48#include <asm/uaccess.h>
49#include <asm/io.h>
50
51/*
52 * The current frame processor firmware fails to checksum a fragment
53 * of length 1. If and when this is fixed, the #define below can be removed.
54 */
55#define HAS_BROKEN_FIRMWARE
56
57/*
58 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 */
60#ifdef HAS_BROKEN_FIRMWARE
61#define PADDING_MASK 3
62#endif
63
64/*
65 * Define this if using the driver with the zero-copy patch
66 */
67#define ZEROCOPY
68
69#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
70#define VLAN_SUPPORT
71#endif
72
73/* The user-configurable values.
74 These may be modified when a driver module is loaded.*/
75
76/* Used for tuning interrupt latency vs. overhead. */
77static int intr_latency;
78static int small_frames;
79
80static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
81static int max_interrupt_work = 20;
82static int mtu;
83/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
84 The Starfire has a 512 element hash table based on the Ethernet CRC. */
85static const int multicast_filter_limit = 512;
86/* Whether to do TCP/UDP checksums in hardware */
87static int enable_hw_cksum = 1;
88
89#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
90/*
91 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
92 * Setting to > 1518 effectively disables this feature.
93 *
94 * NOTE:
95 * The ia64 doesn't allow for unaligned loads even of integers being
96 * misaligned on a 2 byte boundary. Thus always force copying of
97 * packets as the starfire doesn't allow for misaligned DMAs ;-(
98 * 23/10/2000 - Jes
99 *
100 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
101 * at least, having unaligned frames leads to a rather serious performance
102 * penalty. -Ion
103 */
104#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
105static int rx_copybreak = PKT_BUF_SZ;
106#else
107static int rx_copybreak /* = 0 */;
108#endif
109
110/* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
111#ifdef __sparc__
112#define DMA_BURST_SIZE 64
113#else
114#define DMA_BURST_SIZE 128
115#endif
116
117/* Used to pass the media type, etc.
118 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
119 The media type is usually passed in 'options[]'.
120 These variables are deprecated, use ethtool instead. -Ion
121*/
122#define MAX_UNITS 8 /* More are supported, limit only on options */
123static int options[MAX_UNITS] = {0, };
124static int full_duplex[MAX_UNITS] = {0, };
125
126/* Operational parameters that are set at compile time. */
127
128/* The "native" ring sizes are either 256 or 2048.
129 However in some modes a descriptor may be marked to wrap the ring earlier.
130*/
131#define RX_RING_SIZE 256
132#define TX_RING_SIZE 32
133/* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
134#define DONE_Q_SIZE 1024
135/* All queues must be aligned on a 256-byte boundary */
136#define QUEUE_ALIGN 256
137
138#if RX_RING_SIZE > 256
139#define RX_Q_ENTRIES Rx2048QEntries
140#else
141#define RX_Q_ENTRIES Rx256QEntries
142#endif
143
144/* Operational parameters that usually are not changed. */
145/* Time in jiffies before concluding the transmitter is hung. */
146#define TX_TIMEOUT (2 * HZ)
147
148#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
149/* 64-bit dma_addr_t */
150#define ADDR_64BITS /* This chip uses 64 bit addresses. */
151#define netdrv_addr_t __le64
152#define cpu_to_dma(x) cpu_to_le64(x)
153#define dma_to_cpu(x) le64_to_cpu(x)
154#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
155#define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
156#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
157#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
158#define RX_DESC_ADDR_SIZE RxDescAddr64bit
159#else /* 32-bit dma_addr_t */
160#define netdrv_addr_t __le32
161#define cpu_to_dma(x) cpu_to_le32(x)
162#define dma_to_cpu(x) le32_to_cpu(x)
163#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
164#define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
165#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
166#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
167#define RX_DESC_ADDR_SIZE RxDescAddr32bit
168#endif
169
170#define skb_first_frag_len(skb) skb_headlen(skb)
171#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
172
173/* Firmware names */
174#define FIRMWARE_RX "adaptec/starfire_rx.bin"
175#define FIRMWARE_TX "adaptec/starfire_tx.bin"
176
177/* These identify the driver base version and may not be removed. */
178static const char version[] __devinitconst =
179KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
180" (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
181
182MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
183MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
184MODULE_LICENSE("GPL");
185MODULE_VERSION(DRV_VERSION);
186MODULE_FIRMWARE(FIRMWARE_RX);
187MODULE_FIRMWARE(FIRMWARE_TX);
188
189module_param(max_interrupt_work, int, 0);
190module_param(mtu, int, 0);
191module_param(debug, int, 0);
192module_param(rx_copybreak, int, 0);
193module_param(intr_latency, int, 0);
194module_param(small_frames, int, 0);
195module_param_array(options, int, NULL, 0);
196module_param_array(full_duplex, int, NULL, 0);
197module_param(enable_hw_cksum, int, 0);
198MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
199MODULE_PARM_DESC(mtu, "MTU (all boards)");
200MODULE_PARM_DESC(debug, "Debug level (0-6)");
201MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
202MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
203MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
204MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
205MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
206MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
207
208/*
209 Theory of Operation
210
211I. Board Compatibility
212
213This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
214
215II. Board-specific settings
216
217III. Driver operation
218
219IIIa. Ring buffers
220
221The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
222ring sizes are set fixed by the hardware, but may optionally be wrapped
223earlier by the END bit in the descriptor.
224This driver uses that hardware queue size for the Rx ring, where a large
225number of entries has no ill effect beyond increases the potential backlog.
226The Tx ring is wrapped with the END bit, since a large hardware Tx queue
227disables the queue layer priority ordering and we have no mechanism to
228utilize the hardware two-level priority queue. When modifying the
229RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
230levels.
231
232IIIb/c. Transmit/Receive Structure
233
234See the Adaptec manual for the many possible structures, and options for
235each structure. There are far too many to document all of them here.
236
237For transmit this driver uses type 0/1 transmit descriptors (depending
238on the 32/64 bitness of the architecture), and relies on automatic
239minimum-length padding. It does not use the completion queue
240consumer index, but instead checks for non-zero status entries.
241
242For receive this driver uses type 2/3 receive descriptors. The driver
243allocates full frame size skbuffs for the Rx ring buffers, so all frames
244should fit in a single descriptor. The driver does not use the completion
245queue consumer index, but instead checks for non-zero status entries.
246
247When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
248is allocated and the frame is copied to the new skbuff. When the incoming
249frame is larger, the skbuff is passed directly up the protocol stack.
250Buffers consumed this way are replaced by newly allocated skbuffs in a later
251phase of receive.
252
253A notable aspect of operation is that unaligned buffers are not permitted by
254the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
255isn't longword aligned, which may cause problems on some machine
256e.g. Alphas and IA64. For these architectures, the driver is forced to copy
257the frame into a new skbuff unconditionally. Copied frames are put into the
258skbuff at an offset of "+2", thus 16-byte aligning the IP header.
259
260IIId. Synchronization
261
262The driver runs as two independent, single-threaded flows of control. One
263is the send-packet routine, which enforces single-threaded use by the
264dev->tbusy flag. The other thread is the interrupt handler, which is single
265threaded by the hardware and interrupt handling software.
266
267The send packet thread has partial control over the Tx ring and the netif_queue
268status. If the number of free Tx slots in the ring falls below a certain number
269(currently hardcoded to 4), it signals the upper layer to stop the queue.
270
271The interrupt handler has exclusive control over the Rx ring and records stats
272from the Tx ring. After reaping the stats, it marks the Tx queue entry as
273empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
274number of free Tx slow is above the threshold, it signals the upper layer to
275restart the queue.
276
277IV. Notes
278
279IVb. References
280
281The Adaptec Starfire manuals, available only from Adaptec.
282http://www.scyld.com/expert/100mbps.html
283http://www.scyld.com/expert/NWay.html
284
285IVc. Errata
286
287- StopOnPerr is broken, don't enable
288- Hardware ethernet padding exposes random data, perform software padding
289 instead (unverified -- works correctly for all the hardware I have)
290
291*/
292
293
294
295enum chip_capability_flags {CanHaveMII=1, };
296
297enum chipset {
298 CH_6915 = 0,
299};
300
301static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
302 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
303 { 0, }
304};
305MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
306
307/* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
308static const struct chip_info {
309 const char *name;
310 int drv_flags;
311} netdrv_tbl[] __devinitdata = {
312 { "Adaptec Starfire 6915", CanHaveMII },
313};
314
315
316/* Offsets to the device registers.
317 Unlike software-only systems, device drivers interact with complex hardware.
318 It's not useful to define symbolic names for every register bit in the
319 device. The name can only partially document the semantics and make
320 the driver longer and more difficult to read.
321 In general, only the important configuration values or bits changed
322 multiple times should be defined symbolically.
323*/
324enum register_offsets {
325 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
326 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
327 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
328 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
329 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
330 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
331 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
332 TxThreshold=0x500B0,
333 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
334 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
335 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
336 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
337 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
338 TxMode=0x55000, VlanType=0x55064,
339 PerfFilterTable=0x56000, HashTable=0x56100,
340 TxGfpMem=0x58000, RxGfpMem=0x5a000,
341};
342
343/*
344 * Bits in the interrupt status/mask registers.
345 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
346 * enables all the interrupt sources that are or'ed into those status bits.
347 */
348enum intr_status_bits {
349 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
350 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
351 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
352 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
353 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
354 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
355 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
356 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
357 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
358 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
359 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
360 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
361 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
362 IntrTxGfp=0x02, IntrPCIPad=0x01,
363 /* not quite bits */
364 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
365 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
366 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
367};
368
369/* Bits in the RxFilterMode register. */
370enum rx_mode_bits {
371 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
372 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
373 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
374 WakeupOnGFP=0x0800,
375};
376
377/* Bits in the TxMode register */
378enum tx_mode_bits {
379 MiiSoftReset=0x8000, MIILoopback=0x4000,
380 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
381 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
382};
383
384/* Bits in the TxDescCtrl register. */
385enum tx_ctrl_bits {
386 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
387 TxDescSpace128=0x30, TxDescSpace256=0x40,
388 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
389 TxDescType3=0x03, TxDescType4=0x04,
390 TxNoDMACompletion=0x08,
391 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
392 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
393 TxDMABurstSizeShift=8,
394};
395
396/* Bits in the RxDescQCtrl register. */
397enum rx_ctrl_bits {
398 RxBufferLenShift=16, RxMinDescrThreshShift=0,
399 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
400 Rx2048QEntries=0x4000, Rx256QEntries=0,
401 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
402 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
403 RxDescSpace4=0x000, RxDescSpace8=0x100,
404 RxDescSpace16=0x200, RxDescSpace32=0x300,
405 RxDescSpace64=0x400, RxDescSpace128=0x500,
406 RxConsumerWrEn=0x80,
407};
408
409/* Bits in the RxDMACtrl register. */
410enum rx_dmactrl_bits {
411 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
412 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
413 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
414 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
415 RxChecksumRejectTCPOnly=0x01000000,
416 RxCompletionQ2Enable=0x800000,
417 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
418 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
419 RxDMAQ2NonIP=0x400000,
420 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
421 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
422 RxBurstSizeShift=0,
423};
424
425/* Bits in the RxCompletionAddr register */
426enum rx_compl_bits {
427 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
428 RxComplProducerWrEn=0x40,
429 RxComplType0=0x00, RxComplType1=0x10,
430 RxComplType2=0x20, RxComplType3=0x30,
431 RxComplThreshShift=0,
432};
433
434/* Bits in the TxCompletionAddr register */
435enum tx_compl_bits {
436 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
437 TxComplProducerWrEn=0x40,
438 TxComplIntrStatus=0x20,
439 CommonQueueMode=0x10,
440 TxComplThreshShift=0,
441};
442
443/* Bits in the GenCtrl register */
444enum gen_ctrl_bits {
445 RxEnable=0x05, TxEnable=0x0a,
446 RxGFPEnable=0x10, TxGFPEnable=0x20,
447};
448
449/* Bits in the IntrTimerCtrl register */
450enum intr_ctrl_bits {
451 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
452 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
453 IntrLatencyMask=0x1f,
454};
455
456/* The Rx and Tx buffer descriptors. */
457struct starfire_rx_desc {
458 netdrv_addr_t rxaddr;
459};
460enum rx_desc_bits {
461 RxDescValid=1, RxDescEndRing=2,
462};
463
464/* Completion queue entry. */
465struct short_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
467};
468struct basic_rx_done_desc {
469 __le32 status; /* Low 16 bits is length. */
470 __le16 vlanid;
471 __le16 status2;
472};
473struct csum_rx_done_desc {
474 __le32 status; /* Low 16 bits is length. */
475 __le16 csum; /* Partial checksum */
476 __le16 status2;
477};
478struct full_rx_done_desc {
479 __le32 status; /* Low 16 bits is length. */
480 __le16 status3;
481 __le16 status2;
482 __le16 vlanid;
483 __le16 csum; /* partial checksum */
484 __le32 timestamp;
485};
486/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
487#ifdef VLAN_SUPPORT
488typedef struct full_rx_done_desc rx_done_desc;
489#define RxComplType RxComplType3
490#else /* not VLAN_SUPPORT */
491typedef struct csum_rx_done_desc rx_done_desc;
492#define RxComplType RxComplType2
493#endif /* not VLAN_SUPPORT */
494
495enum rx_done_bits {
496 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
497};
498
499/* Type 1 Tx descriptor. */
500struct starfire_tx_desc_1 {
501 __le32 status; /* Upper bits are status, lower 16 length. */
502 __le32 addr;
503};
504
505/* Type 2 Tx descriptor. */
506struct starfire_tx_desc_2 {
507 __le32 status; /* Upper bits are status, lower 16 length. */
508 __le32 reserved;
509 __le64 addr;
510};
511
512#ifdef ADDR_64BITS
513typedef struct starfire_tx_desc_2 starfire_tx_desc;
514#define TX_DESC_TYPE TxDescType2
515#else /* not ADDR_64BITS */
516typedef struct starfire_tx_desc_1 starfire_tx_desc;
517#define TX_DESC_TYPE TxDescType1
518#endif /* not ADDR_64BITS */
519#define TX_DESC_SPACING TxDescSpaceUnlim
520
521enum tx_desc_bits {
522 TxDescID=0xB0000000,
523 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
524 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
525};
526struct tx_done_desc {
527 __le32 status; /* timestamp, index. */
528#if 0
529 __le32 intrstatus; /* interrupt status */
530#endif
531};
532
533struct rx_ring_info {
534 struct sk_buff *skb;
535 dma_addr_t mapping;
536};
537struct tx_ring_info {
538 struct sk_buff *skb;
539 dma_addr_t mapping;
540 unsigned int used_slots;
541};
542
543#define PHY_CNT 2
544struct netdev_private {
545 /* Descriptor rings first for alignment. */
546 struct starfire_rx_desc *rx_ring;
547 starfire_tx_desc *tx_ring;
548 dma_addr_t rx_ring_dma;
549 dma_addr_t tx_ring_dma;
550 /* The addresses of rx/tx-in-place skbuffs. */
551 struct rx_ring_info rx_info[RX_RING_SIZE];
552 struct tx_ring_info tx_info[TX_RING_SIZE];
553 /* Pointers to completion queues (full pages). */
554 rx_done_desc *rx_done_q;
555 dma_addr_t rx_done_q_dma;
556 unsigned int rx_done;
557 struct tx_done_desc *tx_done_q;
558 dma_addr_t tx_done_q_dma;
559 unsigned int tx_done;
560 struct napi_struct napi;
561 struct net_device *dev;
562 struct pci_dev *pci_dev;
563#ifdef VLAN_SUPPORT
564 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
565#endif
566 void *queue_mem;
567 dma_addr_t queue_mem_dma;
568 size_t queue_mem_size;
569
570 /* Frequently used values: keep some adjacent for cache effect. */
571 spinlock_t lock;
572 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
573 unsigned int cur_tx, dirty_tx, reap_tx;
574 unsigned int rx_buf_sz; /* Based on MTU+slack. */
575 /* These values keep track of the transceiver/media in use. */
576 int speed100; /* Set if speed == 100MBit. */
577 u32 tx_mode;
578 u32 intr_timer_ctrl;
579 u8 tx_threshold;
580 /* MII transceiver section. */
581 struct mii_if_info mii_if; /* MII lib hooks/info */
582 int phy_cnt; /* MII device addresses. */
583 unsigned char phys[PHY_CNT]; /* MII device addresses. */
584 void __iomem *base;
585};
586
587
588static int mdio_read(struct net_device *dev, int phy_id, int location);
589static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
590static int netdev_open(struct net_device *dev);
591static void check_duplex(struct net_device *dev);
592static void tx_timeout(struct net_device *dev);
593static void init_ring(struct net_device *dev);
594static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
595static irqreturn_t intr_handler(int irq, void *dev_instance);
596static void netdev_error(struct net_device *dev, int intr_status);
597static int __netdev_rx(struct net_device *dev, int *quota);
598static int netdev_poll(struct napi_struct *napi, int budget);
599static void refill_rx_ring(struct net_device *dev);
600static void netdev_error(struct net_device *dev, int intr_status);
601static void set_rx_mode(struct net_device *dev);
602static struct net_device_stats *get_stats(struct net_device *dev);
603static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
604static int netdev_close(struct net_device *dev);
605static void netdev_media_change(struct net_device *dev);
606static const struct ethtool_ops ethtool_ops;
607
608
609#ifdef VLAN_SUPPORT
610static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
611{
612 struct netdev_private *np = netdev_priv(dev);
613
614 spin_lock(&np->lock);
615 if (debug > 1)
616 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
617 set_bit(vid, np->active_vlans);
618 set_rx_mode(dev);
619 spin_unlock(&np->lock);
620}
621
622static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
623{
624 struct netdev_private *np = netdev_priv(dev);
625
626 spin_lock(&np->lock);
627 if (debug > 1)
628 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
629 clear_bit(vid, np->active_vlans);
630 set_rx_mode(dev);
631 spin_unlock(&np->lock);
632}
633#endif /* VLAN_SUPPORT */
634
635
636static const struct net_device_ops netdev_ops = {
637 .ndo_open = netdev_open,
638 .ndo_stop = netdev_close,
639 .ndo_start_xmit = start_tx,
640 .ndo_tx_timeout = tx_timeout,
641 .ndo_get_stats = get_stats,
642 .ndo_set_multicast_list = &set_rx_mode,
643 .ndo_do_ioctl = netdev_ioctl,
644 .ndo_change_mtu = eth_change_mtu,
645 .ndo_set_mac_address = eth_mac_addr,
646 .ndo_validate_addr = eth_validate_addr,
647#ifdef VLAN_SUPPORT
648 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
649 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
650#endif
651};
652
653static int __devinit starfire_init_one(struct pci_dev *pdev,
654 const struct pci_device_id *ent)
655{
656 struct netdev_private *np;
657 int i, irq, option, chip_idx = ent->driver_data;
658 struct net_device *dev;
659 static int card_idx = -1;
660 long ioaddr;
661 void __iomem *base;
662 int drv_flags, io_size;
663 int boguscnt;
664
665/* when built into the kernel, we only print version if device is found */
666#ifndef MODULE
667 static int printed_version;
668 if (!printed_version++)
669 printk(version);
670#endif
671
672 card_idx++;
673
674 if (pci_enable_device (pdev))
675 return -EIO;
676
677 ioaddr = pci_resource_start(pdev, 0);
678 io_size = pci_resource_len(pdev, 0);
679 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
680 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
681 return -ENODEV;
682 }
683
684 dev = alloc_etherdev(sizeof(*np));
685 if (!dev) {
686 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
687 return -ENOMEM;
688 }
689 SET_NETDEV_DEV(dev, &pdev->dev);
690
691 irq = pdev->irq;
692
693 if (pci_request_regions (pdev, DRV_NAME)) {
694 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
695 goto err_out_free_netdev;
696 }
697
698 base = ioremap(ioaddr, io_size);
699 if (!base) {
700 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
701 card_idx, io_size, ioaddr);
702 goto err_out_free_res;
703 }
704
705 pci_set_master(pdev);
706
707 /* enable MWI -- it vastly improves Rx performance on sparc64 */
708 pci_try_set_mwi(pdev);
709
710#ifdef ZEROCOPY
711 /* Starfire can do TCP/UDP checksumming */
712 if (enable_hw_cksum)
713 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
714#endif /* ZEROCOPY */
715
716#ifdef VLAN_SUPPORT
717 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
718#endif /* VLAN_RX_KILL_VID */
719#ifdef ADDR_64BITS
720 dev->features |= NETIF_F_HIGHDMA;
721#endif /* ADDR_64BITS */
722
723 /* Serial EEPROM reads are hidden by the hardware. */
724 for (i = 0; i < 6; i++)
725 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
726
727#if ! defined(final_version) /* Dump the EEPROM contents during development. */
728 if (debug > 4)
729 for (i = 0; i < 0x20; i++)
730 printk("%2.2x%s",
731 (unsigned int)readb(base + EEPROMCtrl + i),
732 i % 16 != 15 ? " " : "\n");
733#endif
734
735 /* Issue soft reset */
736 writel(MiiSoftReset, base + TxMode);
737 udelay(1000);
738 writel(0, base + TxMode);
739
740 /* Reset the chip to erase previous misconfiguration. */
741 writel(1, base + PCIDeviceConfig);
742 boguscnt = 1000;
743 while (--boguscnt > 0) {
744 udelay(10);
745 if ((readl(base + PCIDeviceConfig) & 1) == 0)
746 break;
747 }
748 if (boguscnt == 0)
749 printk("%s: chipset reset never completed!\n", dev->name);
750 /* wait a little longer */
751 udelay(1000);
752
753 dev->base_addr = (unsigned long)base;
754 dev->irq = irq;
755
756 np = netdev_priv(dev);
757 np->dev = dev;
758 np->base = base;
759 spin_lock_init(&np->lock);
760 pci_set_drvdata(pdev, dev);
761
762 np->pci_dev = pdev;
763
764 np->mii_if.dev = dev;
765 np->mii_if.mdio_read = mdio_read;
766 np->mii_if.mdio_write = mdio_write;
767 np->mii_if.phy_id_mask = 0x1f;
768 np->mii_if.reg_num_mask = 0x1f;
769
770 drv_flags = netdrv_tbl[chip_idx].drv_flags;
771
772 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
773 if (dev->mem_start)
774 option = dev->mem_start;
775
776 /* The lower four bits are the media type. */
777 if (option & 0x200)
778 np->mii_if.full_duplex = 1;
779
780 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
781 np->mii_if.full_duplex = 1;
782
783 if (np->mii_if.full_duplex)
784 np->mii_if.force_media = 1;
785 else
786 np->mii_if.force_media = 0;
787 np->speed100 = 1;
788
789 /* timer resolution is 128 * 0.8us */
790 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
791 Timer10X | EnableIntrMasking;
792
793 if (small_frames > 0) {
794 np->intr_timer_ctrl |= SmallFrameBypass;
795 switch (small_frames) {
796 case 1 ... 64:
797 np->intr_timer_ctrl |= SmallFrame64;
798 break;
799 case 65 ... 128:
800 np->intr_timer_ctrl |= SmallFrame128;
801 break;
802 case 129 ... 256:
803 np->intr_timer_ctrl |= SmallFrame256;
804 break;
805 default:
806 np->intr_timer_ctrl |= SmallFrame512;
807 if (small_frames > 512)
808 printk("Adjusting small_frames down to 512\n");
809 break;
810 }
811 }
812
813 dev->netdev_ops = &netdev_ops;
814 dev->watchdog_timeo = TX_TIMEOUT;
815 SET_ETHTOOL_OPS(dev, ðtool_ops);
816
817 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
818
819 if (mtu)
820 dev->mtu = mtu;
821
822 if (register_netdev(dev))
823 goto err_out_cleardev;
824
825 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
826 dev->name, netdrv_tbl[chip_idx].name, base,
827 dev->dev_addr, irq);
828
829 if (drv_flags & CanHaveMII) {
830 int phy, phy_idx = 0;
831 int mii_status;
832 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
833 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
834 mdelay(100);
835 boguscnt = 1000;
836 while (--boguscnt > 0)
837 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
838 break;
839 if (boguscnt == 0) {
840 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
841 continue;
842 }
843 mii_status = mdio_read(dev, phy, MII_BMSR);
844 if (mii_status != 0) {
845 np->phys[phy_idx++] = phy;
846 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
847 printk(KERN_INFO "%s: MII PHY found at address %d, status "
848 "%#4.4x advertising %#4.4x.\n",
849 dev->name, phy, mii_status, np->mii_if.advertising);
850 /* there can be only one PHY on-board */
851 break;
852 }
853 }
854 np->phy_cnt = phy_idx;
855 if (np->phy_cnt > 0)
856 np->mii_if.phy_id = np->phys[0];
857 else
858 memset(&np->mii_if, 0, sizeof(np->mii_if));
859 }
860
861 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
862 dev->name, enable_hw_cksum ? "enabled" : "disabled");
863 return 0;
864
865err_out_cleardev:
866 pci_set_drvdata(pdev, NULL);
867 iounmap(base);
868err_out_free_res:
869 pci_release_regions (pdev);
870err_out_free_netdev:
871 free_netdev(dev);
872 return -ENODEV;
873}
874
875
876/* Read the MII Management Data I/O (MDIO) interfaces. */
877static int mdio_read(struct net_device *dev, int phy_id, int location)
878{
879 struct netdev_private *np = netdev_priv(dev);
880 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
881 int result, boguscnt=1000;
882 /* ??? Should we add a busy-wait here? */
883 do {
884 result = readl(mdio_addr);
885 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
886 if (boguscnt == 0)
887 return 0;
888 if ((result & 0xffff) == 0xffff)
889 return 0;
890 return result & 0xffff;
891}
892
893
894static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
895{
896 struct netdev_private *np = netdev_priv(dev);
897 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
898 writel(value, mdio_addr);
899 /* The busy-wait will occur before a read. */
900}
901
902
903static int netdev_open(struct net_device *dev)
904{
905 const struct firmware *fw_rx, *fw_tx;
906 const __be32 *fw_rx_data, *fw_tx_data;
907 struct netdev_private *np = netdev_priv(dev);
908 void __iomem *ioaddr = np->base;
909 int i, retval;
910 size_t tx_size, rx_size;
911 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
912
913 /* Do we ever need to reset the chip??? */
914
915 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
916 if (retval)
917 return retval;
918
919 /* Disable the Rx and Tx, and reset the chip. */
920 writel(0, ioaddr + GenCtrl);
921 writel(1, ioaddr + PCIDeviceConfig);
922 if (debug > 1)
923 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
924 dev->name, dev->irq);
925
926 /* Allocate the various queues. */
927 if (!np->queue_mem) {
928 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
929 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
930 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
931 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
932 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
933 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
934 if (np->queue_mem == NULL) {
935 free_irq(dev->irq, dev);
936 return -ENOMEM;
937 }
938
939 np->tx_done_q = np->queue_mem;
940 np->tx_done_q_dma = np->queue_mem_dma;
941 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
942 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
943 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
944 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
945 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
946 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
947 }
948
949 /* Start with no carrier, it gets adjusted later */
950 netif_carrier_off(dev);
951 init_ring(dev);
952 /* Set the size of the Rx buffers. */
953 writel((np->rx_buf_sz << RxBufferLenShift) |
954 (0 << RxMinDescrThreshShift) |
955 RxPrefetchMode | RxVariableQ |
956 RX_Q_ENTRIES |
957 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
958 RxDescSpace4,
959 ioaddr + RxDescQCtrl);
960
961 /* Set up the Rx DMA controller. */
962 writel(RxChecksumIgnore |
963 (0 << RxEarlyIntThreshShift) |
964 (6 << RxHighPrioThreshShift) |
965 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
966 ioaddr + RxDMACtrl);
967
968 /* Set Tx descriptor */
969 writel((2 << TxHiPriFIFOThreshShift) |
970 (0 << TxPadLenShift) |
971 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
972 TX_DESC_Q_ADDR_SIZE |
973 TX_DESC_SPACING | TX_DESC_TYPE,
974 ioaddr + TxDescCtrl);
975
976 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
977 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
978 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
979 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
980 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
981
982 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
983 writel(np->rx_done_q_dma |
984 RxComplType |
985 (0 << RxComplThreshShift),
986 ioaddr + RxCompletionAddr);
987
988 if (debug > 1)
989 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
990
991 /* Fill both the Tx SA register and the Rx perfect filter. */
992 for (i = 0; i < 6; i++)
993 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
994 /* The first entry is special because it bypasses the VLAN filter.
995 Don't use it. */
996 writew(0, ioaddr + PerfFilterTable);
997 writew(0, ioaddr + PerfFilterTable + 4);
998 writew(0, ioaddr + PerfFilterTable + 8);
999 for (i = 1; i < 16; i++) {
1000 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1001 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1002 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1003 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1004 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1005 }
1006
1007 /* Initialize other registers. */
1008 /* Configure the PCI bus bursts and FIFO thresholds. */
1009 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1010 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1011 udelay(1000);
1012 writel(np->tx_mode, ioaddr + TxMode);
1013 np->tx_threshold = 4;
1014 writel(np->tx_threshold, ioaddr + TxThreshold);
1015
1016 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1017
1018 napi_enable(&np->napi);
1019
1020 netif_start_queue(dev);
1021
1022 if (debug > 1)
1023 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1024 set_rx_mode(dev);
1025
1026 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1027 check_duplex(dev);
1028
1029 /* Enable GPIO interrupts on link change */
1030 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1031
1032 /* Set the interrupt mask */
1033 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1034 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1035 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1036 ioaddr + IntrEnable);
1037 /* Enable PCI interrupts. */
1038 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1039 ioaddr + PCIDeviceConfig);
1040
1041#ifdef VLAN_SUPPORT
1042 /* Set VLAN type to 802.1q */
1043 writel(ETH_P_8021Q, ioaddr + VlanType);
1044#endif /* VLAN_SUPPORT */
1045
1046 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1047 if (retval) {
1048 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1049 FIRMWARE_RX);
1050 goto out_init;
1051 }
1052 if (fw_rx->size % 4) {
1053 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1054 fw_rx->size, FIRMWARE_RX);
1055 retval = -EINVAL;
1056 goto out_rx;
1057 }
1058 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1059 if (retval) {
1060 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1061 FIRMWARE_TX);
1062 goto out_rx;
1063 }
1064 if (fw_tx->size % 4) {
1065 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1066 fw_tx->size, FIRMWARE_TX);
1067 retval = -EINVAL;
1068 goto out_tx;
1069 }
1070 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1071 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1072 rx_size = fw_rx->size / 4;
1073 tx_size = fw_tx->size / 4;
1074
1075 /* Load Rx/Tx firmware into the frame processors */
1076 for (i = 0; i < rx_size; i++)
1077 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1078 for (i = 0; i < tx_size; i++)
1079 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1080 if (enable_hw_cksum)
1081 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1082 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1083 else
1084 /* Enable the Rx and Tx units only. */
1085 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1086
1087 if (debug > 1)
1088 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1089 dev->name);
1090
1091out_tx:
1092 release_firmware(fw_tx);
1093out_rx:
1094 release_firmware(fw_rx);
1095out_init:
1096 if (retval)
1097 netdev_close(dev);
1098 return retval;
1099}
1100
1101
1102static void check_duplex(struct net_device *dev)
1103{
1104 struct netdev_private *np = netdev_priv(dev);
1105 u16 reg0;
1106 int silly_count = 1000;
1107
1108 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1109 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1110 udelay(500);
1111 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1112 /* do nothing */;
1113 if (!silly_count) {
1114 printk("%s: MII reset failed!\n", dev->name);
1115 return;
1116 }
1117
1118 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1119
1120 if (!np->mii_if.force_media) {
1121 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1122 } else {
1123 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1124 if (np->speed100)
1125 reg0 |= BMCR_SPEED100;
1126 if (np->mii_if.full_duplex)
1127 reg0 |= BMCR_FULLDPLX;
1128 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1129 dev->name,
1130 np->speed100 ? "100" : "10",
1131 np->mii_if.full_duplex ? "full" : "half");
1132 }
1133 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1134}
1135
1136
1137static void tx_timeout(struct net_device *dev)
1138{
1139 struct netdev_private *np = netdev_priv(dev);
1140 void __iomem *ioaddr = np->base;
1141 int old_debug;
1142
1143 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1144 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1145
1146 /* Perhaps we should reinitialize the hardware here. */
1147
1148 /*
1149 * Stop and restart the interface.
1150 * Cheat and increase the debug level temporarily.
1151 */
1152 old_debug = debug;
1153 debug = 2;
1154 netdev_close(dev);
1155 netdev_open(dev);
1156 debug = old_debug;
1157
1158 /* Trigger an immediate transmit demand. */
1159
1160 dev->trans_start = jiffies; /* prevent tx timeout */
1161 dev->stats.tx_errors++;
1162 netif_wake_queue(dev);
1163}
1164
1165
1166/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1167static void init_ring(struct net_device *dev)
1168{
1169 struct netdev_private *np = netdev_priv(dev);
1170 int i;
1171
1172 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1173 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1174
1175 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1176
1177 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1178 for (i = 0; i < RX_RING_SIZE; i++) {
1179 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1180 np->rx_info[i].skb = skb;
1181 if (skb == NULL)
1182 break;
1183 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1184 skb->dev = dev; /* Mark as being used by this device. */
1185 /* Grrr, we cannot offset to correctly align the IP header. */
1186 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1187 }
1188 writew(i - 1, np->base + RxDescQIdx);
1189 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1190
1191 /* Clear the remainder of the Rx buffer ring. */
1192 for ( ; i < RX_RING_SIZE; i++) {
1193 np->rx_ring[i].rxaddr = 0;
1194 np->rx_info[i].skb = NULL;
1195 np->rx_info[i].mapping = 0;
1196 }
1197 /* Mark the last entry as wrapping the ring. */
1198 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1199
1200 /* Clear the completion rings. */
1201 for (i = 0; i < DONE_Q_SIZE; i++) {
1202 np->rx_done_q[i].status = 0;
1203 np->tx_done_q[i].status = 0;
1204 }
1205
1206 for (i = 0; i < TX_RING_SIZE; i++)
1207 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1208}
1209
1210
1211static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1212{
1213 struct netdev_private *np = netdev_priv(dev);
1214 unsigned int entry;
1215 u32 status;
1216 int i;
1217
1218 /*
1219 * be cautious here, wrapping the queue has weird semantics
1220 * and we may not have enough slots even when it seems we do.
1221 */
1222 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1223 netif_stop_queue(dev);
1224 return NETDEV_TX_BUSY;
1225 }
1226
1227#if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1228 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1229 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1230 return NETDEV_TX_OK;
1231 }
1232#endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1233
1234 entry = np->cur_tx % TX_RING_SIZE;
1235 for (i = 0; i < skb_num_frags(skb); i++) {
1236 int wrap_ring = 0;
1237 status = TxDescID;
1238
1239 if (i == 0) {
1240 np->tx_info[entry].skb = skb;
1241 status |= TxCRCEn;
1242 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1243 status |= TxRingWrap;
1244 wrap_ring = 1;
1245 }
1246 if (np->reap_tx) {
1247 status |= TxDescIntr;
1248 np->reap_tx = 0;
1249 }
1250 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1251 status |= TxCalTCP;
1252 dev->stats.tx_compressed++;
1253 }
1254 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1255
1256 np->tx_info[entry].mapping =
1257 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1258 } else {
1259 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1260 status |= this_frag->size;
1261 np->tx_info[entry].mapping =
1262 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1263 }
1264
1265 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1266 np->tx_ring[entry].status = cpu_to_le32(status);
1267 if (debug > 3)
1268 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1269 dev->name, np->cur_tx, np->dirty_tx,
1270 entry, status);
1271 if (wrap_ring) {
1272 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1273 np->cur_tx += np->tx_info[entry].used_slots;
1274 entry = 0;
1275 } else {
1276 np->tx_info[entry].used_slots = 1;
1277 np->cur_tx += np->tx_info[entry].used_slots;
1278 entry++;
1279 }
1280 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1281 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1282 np->reap_tx = 1;
1283 }
1284
1285 /* Non-x86: explicitly flush descriptor cache lines here. */
1286 /* Ensure all descriptors are written back before the transmit is
1287 initiated. - Jes */
1288 wmb();
1289
1290 /* Update the producer index. */
1291 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1292
1293 /* 4 is arbitrary, but should be ok */
1294 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1295 netif_stop_queue(dev);
1296
1297 return NETDEV_TX_OK;
1298}
1299
1300
1301/* The interrupt handler does all of the Rx thread work and cleans up
1302 after the Tx thread. */
1303static irqreturn_t intr_handler(int irq, void *dev_instance)
1304{
1305 struct net_device *dev = dev_instance;
1306 struct netdev_private *np = netdev_priv(dev);
1307 void __iomem *ioaddr = np->base;
1308 int boguscnt = max_interrupt_work;
1309 int consumer;
1310 int tx_status;
1311 int handled = 0;
1312
1313 do {
1314 u32 intr_status = readl(ioaddr + IntrClear);
1315
1316 if (debug > 4)
1317 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1318 dev->name, intr_status);
1319
1320 if (intr_status == 0 || intr_status == (u32) -1)
1321 break;
1322
1323 handled = 1;
1324
1325 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1326 u32 enable;
1327
1328 if (likely(napi_schedule_prep(&np->napi))) {
1329 __napi_schedule(&np->napi);
1330 enable = readl(ioaddr + IntrEnable);
1331 enable &= ~(IntrRxDone | IntrRxEmpty);
1332 writel(enable, ioaddr + IntrEnable);
1333 /* flush PCI posting buffers */
1334 readl(ioaddr + IntrEnable);
1335 } else {
1336 /* Paranoia check */
1337 enable = readl(ioaddr + IntrEnable);
1338 if (enable & (IntrRxDone | IntrRxEmpty)) {
1339 printk(KERN_INFO
1340 "%s: interrupt while in poll!\n",
1341 dev->name);
1342 enable &= ~(IntrRxDone | IntrRxEmpty);
1343 writel(enable, ioaddr + IntrEnable);
1344 }
1345 }
1346 }
1347
1348 /* Scavenge the skbuff list based on the Tx-done queue.
1349 There are redundant checks here that may be cleaned up
1350 after the driver has proven to be reliable. */
1351 consumer = readl(ioaddr + TxConsumerIdx);
1352 if (debug > 3)
1353 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1354 dev->name, consumer);
1355
1356 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1357 if (debug > 3)
1358 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1359 dev->name, np->dirty_tx, np->tx_done, tx_status);
1360 if ((tx_status & 0xe0000000) == 0xa0000000) {
1361 dev->stats.tx_packets++;
1362 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1363 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1364 struct sk_buff *skb = np->tx_info[entry].skb;
1365 np->tx_info[entry].skb = NULL;
1366 pci_unmap_single(np->pci_dev,
1367 np->tx_info[entry].mapping,
1368 skb_first_frag_len(skb),
1369 PCI_DMA_TODEVICE);
1370 np->tx_info[entry].mapping = 0;
1371 np->dirty_tx += np->tx_info[entry].used_slots;
1372 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1373 {
1374 int i;
1375 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1376 pci_unmap_single(np->pci_dev,
1377 np->tx_info[entry].mapping,
1378 skb_shinfo(skb)->frags[i].size,
1379 PCI_DMA_TODEVICE);
1380 np->dirty_tx++;
1381 entry++;
1382 }
1383 }
1384
1385 dev_kfree_skb_irq(skb);
1386 }
1387 np->tx_done_q[np->tx_done].status = 0;
1388 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1389 }
1390 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1391
1392 if (netif_queue_stopped(dev) &&
1393 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1394 /* The ring is no longer full, wake the queue. */
1395 netif_wake_queue(dev);
1396 }
1397
1398 /* Stats overflow */
1399 if (intr_status & IntrStatsMax)
1400 get_stats(dev);
1401
1402 /* Media change interrupt. */
1403 if (intr_status & IntrLinkChange)
1404 netdev_media_change(dev);
1405
1406 /* Abnormal error summary/uncommon events handlers. */
1407 if (intr_status & IntrAbnormalSummary)
1408 netdev_error(dev, intr_status);
1409
1410 if (--boguscnt < 0) {
1411 if (debug > 1)
1412 printk(KERN_WARNING "%s: Too much work at interrupt, "
1413 "status=%#8.8x.\n",
1414 dev->name, intr_status);
1415 break;
1416 }
1417 } while (1);
1418
1419 if (debug > 4)
1420 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1421 dev->name, (int) readl(ioaddr + IntrStatus));
1422 return IRQ_RETVAL(handled);
1423}
1424
1425
1426/*
1427 * This routine is logically part of the interrupt/poll handler, but separated
1428 * for clarity and better register allocation.
1429 */
1430static int __netdev_rx(struct net_device *dev, int *quota)
1431{
1432 struct netdev_private *np = netdev_priv(dev);
1433 u32 desc_status;
1434 int retcode = 0;
1435
1436 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1437 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1438 struct sk_buff *skb;
1439 u16 pkt_len;
1440 int entry;
1441 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1442
1443 if (debug > 4)
1444 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1445 if (!(desc_status & RxOK)) {
1446 /* There was an error. */
1447 if (debug > 2)
1448 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1449 dev->stats.rx_errors++;
1450 if (desc_status & RxFIFOErr)
1451 dev->stats.rx_fifo_errors++;
1452 goto next_rx;
1453 }
1454
1455 if (*quota <= 0) { /* out of rx quota */
1456 retcode = 1;
1457 goto out;
1458 }
1459 (*quota)--;
1460
1461 pkt_len = desc_status; /* Implicitly Truncate */
1462 entry = (desc_status >> 16) & 0x7ff;
1463
1464 if (debug > 4)
1465 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1466 /* Check if the packet is long enough to accept without copying
1467 to a minimally-sized skbuff. */
1468 if (pkt_len < rx_copybreak &&
1469 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1470 skb_reserve(skb, 2); /* 16 byte align the IP header */
1471 pci_dma_sync_single_for_cpu(np->pci_dev,
1472 np->rx_info[entry].mapping,
1473 pkt_len, PCI_DMA_FROMDEVICE);
1474 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1475 pci_dma_sync_single_for_device(np->pci_dev,
1476 np->rx_info[entry].mapping,
1477 pkt_len, PCI_DMA_FROMDEVICE);
1478 skb_put(skb, pkt_len);
1479 } else {
1480 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1481 skb = np->rx_info[entry].skb;
1482 skb_put(skb, pkt_len);
1483 np->rx_info[entry].skb = NULL;
1484 np->rx_info[entry].mapping = 0;
1485 }
1486#ifndef final_version /* Remove after testing. */
1487 /* You will want this info for the initial debug. */
1488 if (debug > 5) {
1489 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1490 skb->data, skb->data + 6,
1491 skb->data[12], skb->data[13]);
1492 }
1493#endif
1494
1495 skb->protocol = eth_type_trans(skb, dev);
1496#ifdef VLAN_SUPPORT
1497 if (debug > 4)
1498 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1499#endif
1500 if (le16_to_cpu(desc->status2) & 0x0100) {
1501 skb->ip_summed = CHECKSUM_UNNECESSARY;
1502 dev->stats.rx_compressed++;
1503 }
1504 /*
1505 * This feature doesn't seem to be working, at least
1506 * with the two firmware versions I have. If the GFP sees
1507 * an IP fragment, it either ignores it completely, or reports
1508 * "bad checksum" on it.
1509 *
1510 * Maybe I missed something -- corrections are welcome.
1511 * Until then, the printk stays. :-) -Ion
1512 */
1513 else if (le16_to_cpu(desc->status2) & 0x0040) {
1514 skb->ip_summed = CHECKSUM_COMPLETE;
1515 skb->csum = le16_to_cpu(desc->csum);
1516 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1517 }
1518#ifdef VLAN_SUPPORT
1519 if (le16_to_cpu(desc->status2) & 0x0200) {
1520 u16 vlid = le16_to_cpu(desc->vlanid);
1521
1522 if (debug > 4) {
1523 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1524 vlid);
1525 }
1526 __vlan_hwaccel_put_tag(skb, vlid);
1527 }
1528#endif /* VLAN_SUPPORT */
1529 netif_receive_skb(skb);
1530 dev->stats.rx_packets++;
1531
1532 next_rx:
1533 np->cur_rx++;
1534 desc->status = 0;
1535 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1536 }
1537
1538 if (*quota == 0) { /* out of rx quota */
1539 retcode = 1;
1540 goto out;
1541 }
1542 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1543
1544 out:
1545 refill_rx_ring(dev);
1546 if (debug > 5)
1547 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1548 retcode, np->rx_done, desc_status);
1549 return retcode;
1550}
1551
1552static int netdev_poll(struct napi_struct *napi, int budget)
1553{
1554 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1555 struct net_device *dev = np->dev;
1556 u32 intr_status;
1557 void __iomem *ioaddr = np->base;
1558 int quota = budget;
1559
1560 do {
1561 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1562
1563 if (__netdev_rx(dev, "a))
1564 goto out;
1565
1566 intr_status = readl(ioaddr + IntrStatus);
1567 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1568
1569 napi_complete(napi);
1570 intr_status = readl(ioaddr + IntrEnable);
1571 intr_status |= IntrRxDone | IntrRxEmpty;
1572 writel(intr_status, ioaddr + IntrEnable);
1573
1574 out:
1575 if (debug > 5)
1576 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1577 budget - quota);
1578
1579 /* Restart Rx engine if stopped. */
1580 return budget - quota;
1581}
1582
1583static void refill_rx_ring(struct net_device *dev)
1584{
1585 struct netdev_private *np = netdev_priv(dev);
1586 struct sk_buff *skb;
1587 int entry = -1;
1588
1589 /* Refill the Rx ring buffers. */
1590 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1591 entry = np->dirty_rx % RX_RING_SIZE;
1592 if (np->rx_info[entry].skb == NULL) {
1593 skb = dev_alloc_skb(np->rx_buf_sz);
1594 np->rx_info[entry].skb = skb;
1595 if (skb == NULL)
1596 break; /* Better luck next round. */
1597 np->rx_info[entry].mapping =
1598 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1599 skb->dev = dev; /* Mark as being used by this device. */
1600 np->rx_ring[entry].rxaddr =
1601 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1602 }
1603 if (entry == RX_RING_SIZE - 1)
1604 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1605 }
1606 if (entry >= 0)
1607 writew(entry, np->base + RxDescQIdx);
1608}
1609
1610
1611static void netdev_media_change(struct net_device *dev)
1612{
1613 struct netdev_private *np = netdev_priv(dev);
1614 void __iomem *ioaddr = np->base;
1615 u16 reg0, reg1, reg4, reg5;
1616 u32 new_tx_mode;
1617 u32 new_intr_timer_ctrl;
1618
1619 /* reset status first */
1620 mdio_read(dev, np->phys[0], MII_BMCR);
1621 mdio_read(dev, np->phys[0], MII_BMSR);
1622
1623 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1624 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1625
1626 if (reg1 & BMSR_LSTATUS) {
1627 /* link is up */
1628 if (reg0 & BMCR_ANENABLE) {
1629 /* autonegotiation is enabled */
1630 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1631 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1632 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1633 np->speed100 = 1;
1634 np->mii_if.full_duplex = 1;
1635 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1636 np->speed100 = 1;
1637 np->mii_if.full_duplex = 0;
1638 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1639 np->speed100 = 0;
1640 np->mii_if.full_duplex = 1;
1641 } else {
1642 np->speed100 = 0;
1643 np->mii_if.full_duplex = 0;
1644 }
1645 } else {
1646 /* autonegotiation is disabled */
1647 if (reg0 & BMCR_SPEED100)
1648 np->speed100 = 1;
1649 else
1650 np->speed100 = 0;
1651 if (reg0 & BMCR_FULLDPLX)
1652 np->mii_if.full_duplex = 1;
1653 else
1654 np->mii_if.full_duplex = 0;
1655 }
1656 netif_carrier_on(dev);
1657 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1658 dev->name,
1659 np->speed100 ? "100" : "10",
1660 np->mii_if.full_duplex ? "full" : "half");
1661
1662 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1663 if (np->mii_if.full_duplex)
1664 new_tx_mode |= FullDuplex;
1665 if (np->tx_mode != new_tx_mode) {
1666 np->tx_mode = new_tx_mode;
1667 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1668 udelay(1000);
1669 writel(np->tx_mode, ioaddr + TxMode);
1670 }
1671
1672 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1673 if (np->speed100)
1674 new_intr_timer_ctrl |= Timer10X;
1675 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1676 np->intr_timer_ctrl = new_intr_timer_ctrl;
1677 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1678 }
1679 } else {
1680 netif_carrier_off(dev);
1681 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1682 }
1683}
1684
1685
1686static void netdev_error(struct net_device *dev, int intr_status)
1687{
1688 struct netdev_private *np = netdev_priv(dev);
1689
1690 /* Came close to underrunning the Tx FIFO, increase threshold. */
1691 if (intr_status & IntrTxDataLow) {
1692 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1693 writel(++np->tx_threshold, np->base + TxThreshold);
1694 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1695 dev->name, np->tx_threshold * 16);
1696 } else
1697 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1698 }
1699 if (intr_status & IntrRxGFPDead) {
1700 dev->stats.rx_fifo_errors++;
1701 dev->stats.rx_errors++;
1702 }
1703 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1704 dev->stats.tx_fifo_errors++;
1705 dev->stats.tx_errors++;
1706 }
1707 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1708 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1709 dev->name, intr_status);
1710}
1711
1712
1713static struct net_device_stats *get_stats(struct net_device *dev)
1714{
1715 struct netdev_private *np = netdev_priv(dev);
1716 void __iomem *ioaddr = np->base;
1717
1718 /* This adapter architecture needs no SMP locks. */
1719 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1720 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1721 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1722 dev->stats.tx_aborted_errors =
1723 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1724 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1725 dev->stats.collisions =
1726 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1727
1728 /* The chip only need report frame silently dropped. */
1729 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1730 writew(0, ioaddr + RxDMAStatus);
1731 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1732 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1733 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1734 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1735
1736 return &dev->stats;
1737}
1738
1739#ifdef VLAN_SUPPORT
1740static u32 set_vlan_mode(struct netdev_private *np)
1741{
1742 u32 ret = VlanMode;
1743 u16 vid;
1744 void __iomem *filter_addr = np->base + HashTable + 8;
1745 int vlan_count = 0;
1746
1747 for_each_set_bit(vid, np->active_vlans, VLAN_N_VID) {
1748 if (vlan_count == 32)
1749 break;
1750 writew(vid, filter_addr);
1751 filter_addr += 16;
1752 vlan_count++;
1753 }
1754 if (vlan_count == 32) {
1755 ret |= PerfectFilterVlan;
1756 while (vlan_count < 32) {
1757 writew(0, filter_addr);
1758 filter_addr += 16;
1759 vlan_count++;
1760 }
1761 }
1762 return ret;
1763}
1764#endif /* VLAN_SUPPORT */
1765
1766static void set_rx_mode(struct net_device *dev)
1767{
1768 struct netdev_private *np = netdev_priv(dev);
1769 void __iomem *ioaddr = np->base;
1770 u32 rx_mode = MinVLANPrio;
1771 struct netdev_hw_addr *ha;
1772 int i;
1773
1774#ifdef VLAN_SUPPORT
1775 rx_mode |= set_vlan_mode(np);
1776#endif /* VLAN_SUPPORT */
1777
1778 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1779 rx_mode |= AcceptAll;
1780 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1781 (dev->flags & IFF_ALLMULTI)) {
1782 /* Too many to match, or accept all multicasts. */
1783 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1784 } else if (netdev_mc_count(dev) <= 14) {
1785 /* Use the 16 element perfect filter, skip first two entries. */
1786 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1787 __be16 *eaddrs;
1788 netdev_for_each_mc_addr(ha, dev) {
1789 eaddrs = (__be16 *) ha->addr;
1790 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1791 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1792 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1793 }
1794 eaddrs = (__be16 *)dev->dev_addr;
1795 i = netdev_mc_count(dev) + 2;
1796 while (i++ < 16) {
1797 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1798 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1799 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1800 }
1801 rx_mode |= AcceptBroadcast|PerfectFilter;
1802 } else {
1803 /* Must use a multicast hash table. */
1804 void __iomem *filter_addr;
1805 __be16 *eaddrs;
1806 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1807
1808 memset(mc_filter, 0, sizeof(mc_filter));
1809 netdev_for_each_mc_addr(ha, dev) {
1810 /* The chip uses the upper 9 CRC bits
1811 as index into the hash table */
1812 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1813 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1814
1815 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1816 }
1817 /* Clear the perfect filter list, skip first two entries. */
1818 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1819 eaddrs = (__be16 *)dev->dev_addr;
1820 for (i = 2; i < 16; i++) {
1821 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1822 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1823 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1824 }
1825 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1826 writew(mc_filter[i], filter_addr);
1827 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1828 }
1829 writel(rx_mode, ioaddr + RxFilterMode);
1830}
1831
1832static int check_if_running(struct net_device *dev)
1833{
1834 if (!netif_running(dev))
1835 return -EINVAL;
1836 return 0;
1837}
1838
1839static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1840{
1841 struct netdev_private *np = netdev_priv(dev);
1842 strcpy(info->driver, DRV_NAME);
1843 strcpy(info->version, DRV_VERSION);
1844 strcpy(info->bus_info, pci_name(np->pci_dev));
1845}
1846
1847static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1848{
1849 struct netdev_private *np = netdev_priv(dev);
1850 spin_lock_irq(&np->lock);
1851 mii_ethtool_gset(&np->mii_if, ecmd);
1852 spin_unlock_irq(&np->lock);
1853 return 0;
1854}
1855
1856static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1857{
1858 struct netdev_private *np = netdev_priv(dev);
1859 int res;
1860 spin_lock_irq(&np->lock);
1861 res = mii_ethtool_sset(&np->mii_if, ecmd);
1862 spin_unlock_irq(&np->lock);
1863 check_duplex(dev);
1864 return res;
1865}
1866
1867static int nway_reset(struct net_device *dev)
1868{
1869 struct netdev_private *np = netdev_priv(dev);
1870 return mii_nway_restart(&np->mii_if);
1871}
1872
1873static u32 get_link(struct net_device *dev)
1874{
1875 struct netdev_private *np = netdev_priv(dev);
1876 return mii_link_ok(&np->mii_if);
1877}
1878
1879static u32 get_msglevel(struct net_device *dev)
1880{
1881 return debug;
1882}
1883
1884static void set_msglevel(struct net_device *dev, u32 val)
1885{
1886 debug = val;
1887}
1888
1889static const struct ethtool_ops ethtool_ops = {
1890 .begin = check_if_running,
1891 .get_drvinfo = get_drvinfo,
1892 .get_settings = get_settings,
1893 .set_settings = set_settings,
1894 .nway_reset = nway_reset,
1895 .get_link = get_link,
1896 .get_msglevel = get_msglevel,
1897 .set_msglevel = set_msglevel,
1898};
1899
1900static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1901{
1902 struct netdev_private *np = netdev_priv(dev);
1903 struct mii_ioctl_data *data = if_mii(rq);
1904 int rc;
1905
1906 if (!netif_running(dev))
1907 return -EINVAL;
1908
1909 spin_lock_irq(&np->lock);
1910 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1911 spin_unlock_irq(&np->lock);
1912
1913 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1914 check_duplex(dev);
1915
1916 return rc;
1917}
1918
1919static int netdev_close(struct net_device *dev)
1920{
1921 struct netdev_private *np = netdev_priv(dev);
1922 void __iomem *ioaddr = np->base;
1923 int i;
1924
1925 netif_stop_queue(dev);
1926
1927 napi_disable(&np->napi);
1928
1929 if (debug > 1) {
1930 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1931 dev->name, (int) readl(ioaddr + IntrStatus));
1932 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1933 dev->name, np->cur_tx, np->dirty_tx,
1934 np->cur_rx, np->dirty_rx);
1935 }
1936
1937 /* Disable interrupts by clearing the interrupt mask. */
1938 writel(0, ioaddr + IntrEnable);
1939
1940 /* Stop the chip's Tx and Rx processes. */
1941 writel(0, ioaddr + GenCtrl);
1942 readl(ioaddr + GenCtrl);
1943
1944 if (debug > 5) {
1945 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1946 (long long) np->tx_ring_dma);
1947 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1948 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1949 i, le32_to_cpu(np->tx_ring[i].status),
1950 (long long) dma_to_cpu(np->tx_ring[i].addr),
1951 le32_to_cpu(np->tx_done_q[i].status));
1952 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1953 (long long) np->rx_ring_dma, np->rx_done_q);
1954 if (np->rx_done_q)
1955 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1956 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1957 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1958 }
1959 }
1960
1961 free_irq(dev->irq, dev);
1962
1963 /* Free all the skbuffs in the Rx queue. */
1964 for (i = 0; i < RX_RING_SIZE; i++) {
1965 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1966 if (np->rx_info[i].skb != NULL) {
1967 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1968 dev_kfree_skb(np->rx_info[i].skb);
1969 }
1970 np->rx_info[i].skb = NULL;
1971 np->rx_info[i].mapping = 0;
1972 }
1973 for (i = 0; i < TX_RING_SIZE; i++) {
1974 struct sk_buff *skb = np->tx_info[i].skb;
1975 if (skb == NULL)
1976 continue;
1977 pci_unmap_single(np->pci_dev,
1978 np->tx_info[i].mapping,
1979 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1980 np->tx_info[i].mapping = 0;
1981 dev_kfree_skb(skb);
1982 np->tx_info[i].skb = NULL;
1983 }
1984
1985 return 0;
1986}
1987
1988#ifdef CONFIG_PM
1989static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1990{
1991 struct net_device *dev = pci_get_drvdata(pdev);
1992
1993 if (netif_running(dev)) {
1994 netif_device_detach(dev);
1995 netdev_close(dev);
1996 }
1997
1998 pci_save_state(pdev);
1999 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2000
2001 return 0;
2002}
2003
2004static int starfire_resume(struct pci_dev *pdev)
2005{
2006 struct net_device *dev = pci_get_drvdata(pdev);
2007
2008 pci_set_power_state(pdev, PCI_D0);
2009 pci_restore_state(pdev);
2010
2011 if (netif_running(dev)) {
2012 netdev_open(dev);
2013 netif_device_attach(dev);
2014 }
2015
2016 return 0;
2017}
2018#endif /* CONFIG_PM */
2019
2020
2021static void __devexit starfire_remove_one (struct pci_dev *pdev)
2022{
2023 struct net_device *dev = pci_get_drvdata(pdev);
2024 struct netdev_private *np = netdev_priv(dev);
2025
2026 BUG_ON(!dev);
2027
2028 unregister_netdev(dev);
2029
2030 if (np->queue_mem)
2031 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2032
2033
2034 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2035 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2036 pci_disable_device(pdev);
2037
2038 iounmap(np->base);
2039 pci_release_regions(pdev);
2040
2041 pci_set_drvdata(pdev, NULL);
2042 free_netdev(dev); /* Will also free np!! */
2043}
2044
2045
2046static struct pci_driver starfire_driver = {
2047 .name = DRV_NAME,
2048 .probe = starfire_init_one,
2049 .remove = __devexit_p(starfire_remove_one),
2050#ifdef CONFIG_PM
2051 .suspend = starfire_suspend,
2052 .resume = starfire_resume,
2053#endif /* CONFIG_PM */
2054 .id_table = starfire_pci_tbl,
2055};
2056
2057
2058static int __init starfire_init (void)
2059{
2060/* when a module, this is printed whether or not devices are found in probe */
2061#ifdef MODULE
2062 printk(version);
2063
2064 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2065#endif
2066
2067 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2068
2069 return pci_register_driver(&starfire_driver);
2070}
2071
2072
2073static void __exit starfire_cleanup (void)
2074{
2075 pci_unregister_driver (&starfire_driver);
2076}
2077
2078
2079module_init(starfire_init);
2080module_exit(starfire_cleanup);
2081
2082
2083/*
2084 * Local variables:
2085 * c-basic-offset: 8
2086 * tab-width: 8
2087 * End:
2088 */