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1/*
2 * Ethernet driver for S6105 on chip network device
3 * (c)2008 emlix GmbH http://www.emlix.com
4 * Authors: Oskar Schirmer <os@emlix.com>
5 * Daniel Gloeckner <dg@emlix.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/spinlock.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/if.h>
22#include <linux/stddef.h>
23#include <linux/mii.h>
24#include <linux/phy.h>
25#include <linux/platform_device.h>
26#include <variant/hardware.h>
27#include <variant/dmac.h>
28
29#define DRV_NAME "s6gmac"
30#define DRV_PRMT DRV_NAME ": "
31
32
33/* register declarations */
34
35#define S6_GMAC_MACCONF1 0x000
36#define S6_GMAC_MACCONF1_TXENA 0
37#define S6_GMAC_MACCONF1_SYNCTX 1
38#define S6_GMAC_MACCONF1_RXENA 2
39#define S6_GMAC_MACCONF1_SYNCRX 3
40#define S6_GMAC_MACCONF1_TXFLOWCTRL 4
41#define S6_GMAC_MACCONF1_RXFLOWCTRL 5
42#define S6_GMAC_MACCONF1_LOOPBACK 8
43#define S6_GMAC_MACCONF1_RESTXFUNC 16
44#define S6_GMAC_MACCONF1_RESRXFUNC 17
45#define S6_GMAC_MACCONF1_RESTXMACCTRL 18
46#define S6_GMAC_MACCONF1_RESRXMACCTRL 19
47#define S6_GMAC_MACCONF1_SIMULRES 30
48#define S6_GMAC_MACCONF1_SOFTRES 31
49#define S6_GMAC_MACCONF2 0x004
50#define S6_GMAC_MACCONF2_FULL 0
51#define S6_GMAC_MACCONF2_CRCENA 1
52#define S6_GMAC_MACCONF2_PADCRCENA 2
53#define S6_GMAC_MACCONF2_LENGTHFCHK 4
54#define S6_GMAC_MACCONF2_HUGEFRAMENA 5
55#define S6_GMAC_MACCONF2_IFMODE 8
56#define S6_GMAC_MACCONF2_IFMODE_NIBBLE 1
57#define S6_GMAC_MACCONF2_IFMODE_BYTE 2
58#define S6_GMAC_MACCONF2_IFMODE_MASK 3
59#define S6_GMAC_MACCONF2_PREAMBLELEN 12
60#define S6_GMAC_MACCONF2_PREAMBLELEN_MASK 0x0F
61#define S6_GMAC_MACIPGIFG 0x008
62#define S6_GMAC_MACIPGIFG_B2BINTERPGAP 0
63#define S6_GMAC_MACIPGIFG_B2BINTERPGAP_MASK 0x7F
64#define S6_GMAC_MACIPGIFG_MINIFGENFORCE 8
65#define S6_GMAC_MACIPGIFG_B2BINTERPGAP2 16
66#define S6_GMAC_MACIPGIFG_B2BINTERPGAP1 24
67#define S6_GMAC_MACHALFDUPLEX 0x00C
68#define S6_GMAC_MACHALFDUPLEX_COLLISWIN 0
69#define S6_GMAC_MACHALFDUPLEX_COLLISWIN_MASK 0x3F
70#define S6_GMAC_MACHALFDUPLEX_RETXMAX 12
71#define S6_GMAC_MACHALFDUPLEX_RETXMAX_MASK 0x0F
72#define S6_GMAC_MACHALFDUPLEX_EXCESSDEF 16
73#define S6_GMAC_MACHALFDUPLEX_NOBACKOFF 17
74#define S6_GMAC_MACHALFDUPLEX_BPNOBCKOF 18
75#define S6_GMAC_MACHALFDUPLEX_ALTBEBENA 19
76#define S6_GMAC_MACHALFDUPLEX_ALTBEBTRN 20
77#define S6_GMAC_MACHALFDUPLEX_ALTBEBTR_MASK 0x0F
78#define S6_GMAC_MACMAXFRAMELEN 0x010
79#define S6_GMAC_MACMIICONF 0x020
80#define S6_GMAC_MACMIICONF_CSEL 0
81#define S6_GMAC_MACMIICONF_CSEL_DIV10 0
82#define S6_GMAC_MACMIICONF_CSEL_DIV12 1
83#define S6_GMAC_MACMIICONF_CSEL_DIV14 2
84#define S6_GMAC_MACMIICONF_CSEL_DIV18 3
85#define S6_GMAC_MACMIICONF_CSEL_DIV24 4
86#define S6_GMAC_MACMIICONF_CSEL_DIV34 5
87#define S6_GMAC_MACMIICONF_CSEL_DIV68 6
88#define S6_GMAC_MACMIICONF_CSEL_DIV168 7
89#define S6_GMAC_MACMIICONF_CSEL_MASK 7
90#define S6_GMAC_MACMIICONF_PREAMBLESUPR 4
91#define S6_GMAC_MACMIICONF_SCANAUTOINCR 5
92#define S6_GMAC_MACMIICMD 0x024
93#define S6_GMAC_MACMIICMD_READ 0
94#define S6_GMAC_MACMIICMD_SCAN 1
95#define S6_GMAC_MACMIIADDR 0x028
96#define S6_GMAC_MACMIIADDR_REG 0
97#define S6_GMAC_MACMIIADDR_REG_MASK 0x1F
98#define S6_GMAC_MACMIIADDR_PHY 8
99#define S6_GMAC_MACMIIADDR_PHY_MASK 0x1F
100#define S6_GMAC_MACMIICTRL 0x02C
101#define S6_GMAC_MACMIISTAT 0x030
102#define S6_GMAC_MACMIIINDI 0x034
103#define S6_GMAC_MACMIIINDI_BUSY 0
104#define S6_GMAC_MACMIIINDI_SCAN 1
105#define S6_GMAC_MACMIIINDI_INVAL 2
106#define S6_GMAC_MACINTERFSTAT 0x03C
107#define S6_GMAC_MACINTERFSTAT_LINKFAIL 3
108#define S6_GMAC_MACINTERFSTAT_EXCESSDEF 9
109#define S6_GMAC_MACSTATADDR1 0x040
110#define S6_GMAC_MACSTATADDR2 0x044
111
112#define S6_GMAC_FIFOCONF0 0x048
113#define S6_GMAC_FIFOCONF0_HSTRSTWT 0
114#define S6_GMAC_FIFOCONF0_HSTRSTSR 1
115#define S6_GMAC_FIFOCONF0_HSTRSTFR 2
116#define S6_GMAC_FIFOCONF0_HSTRSTST 3
117#define S6_GMAC_FIFOCONF0_HSTRSTFT 4
118#define S6_GMAC_FIFOCONF0_WTMENREQ 8
119#define S6_GMAC_FIFOCONF0_SRFENREQ 9
120#define S6_GMAC_FIFOCONF0_FRFENREQ 10
121#define S6_GMAC_FIFOCONF0_STFENREQ 11
122#define S6_GMAC_FIFOCONF0_FTFENREQ 12
123#define S6_GMAC_FIFOCONF0_WTMENRPLY 16
124#define S6_GMAC_FIFOCONF0_SRFENRPLY 17
125#define S6_GMAC_FIFOCONF0_FRFENRPLY 18
126#define S6_GMAC_FIFOCONF0_STFENRPLY 19
127#define S6_GMAC_FIFOCONF0_FTFENRPLY 20
128#define S6_GMAC_FIFOCONF1 0x04C
129#define S6_GMAC_FIFOCONF2 0x050
130#define S6_GMAC_FIFOCONF2_CFGLWM 0
131#define S6_GMAC_FIFOCONF2_CFGHWM 16
132#define S6_GMAC_FIFOCONF3 0x054
133#define S6_GMAC_FIFOCONF3_CFGFTTH 0
134#define S6_GMAC_FIFOCONF3_CFGHWMFT 16
135#define S6_GMAC_FIFOCONF4 0x058
136#define S6_GMAC_FIFOCONF_RSV_PREVDROP 0
137#define S6_GMAC_FIFOCONF_RSV_RUNT 1
138#define S6_GMAC_FIFOCONF_RSV_FALSECAR 2
139#define S6_GMAC_FIFOCONF_RSV_CODEERR 3
140#define S6_GMAC_FIFOCONF_RSV_CRCERR 4
141#define S6_GMAC_FIFOCONF_RSV_LENGTHERR 5
142#define S6_GMAC_FIFOCONF_RSV_LENRANGE 6
143#define S6_GMAC_FIFOCONF_RSV_OK 7
144#define S6_GMAC_FIFOCONF_RSV_MULTICAST 8
145#define S6_GMAC_FIFOCONF_RSV_BROADCAST 9
146#define S6_GMAC_FIFOCONF_RSV_DRIBBLE 10
147#define S6_GMAC_FIFOCONF_RSV_CTRLFRAME 11
148#define S6_GMAC_FIFOCONF_RSV_PAUSECTRL 12
149#define S6_GMAC_FIFOCONF_RSV_UNOPCODE 13
150#define S6_GMAC_FIFOCONF_RSV_VLANTAG 14
151#define S6_GMAC_FIFOCONF_RSV_LONGEVENT 15
152#define S6_GMAC_FIFOCONF_RSV_TRUNCATED 16
153#define S6_GMAC_FIFOCONF_RSV_MASK 0x3FFFF
154#define S6_GMAC_FIFOCONF5 0x05C
155#define S6_GMAC_FIFOCONF5_DROPLT64 18
156#define S6_GMAC_FIFOCONF5_CFGBYTM 19
157#define S6_GMAC_FIFOCONF5_RXDROPSIZE 20
158#define S6_GMAC_FIFOCONF5_RXDROPSIZE_MASK 0xF
159
160#define S6_GMAC_STAT_REGS 0x080
161#define S6_GMAC_STAT_SIZE_MIN 12
162#define S6_GMAC_STATTR64 0x080
163#define S6_GMAC_STATTR64_SIZE 18
164#define S6_GMAC_STATTR127 0x084
165#define S6_GMAC_STATTR127_SIZE 18
166#define S6_GMAC_STATTR255 0x088
167#define S6_GMAC_STATTR255_SIZE 18
168#define S6_GMAC_STATTR511 0x08C
169#define S6_GMAC_STATTR511_SIZE 18
170#define S6_GMAC_STATTR1K 0x090
171#define S6_GMAC_STATTR1K_SIZE 18
172#define S6_GMAC_STATTRMAX 0x094
173#define S6_GMAC_STATTRMAX_SIZE 18
174#define S6_GMAC_STATTRMGV 0x098
175#define S6_GMAC_STATTRMGV_SIZE 18
176#define S6_GMAC_STATRBYT 0x09C
177#define S6_GMAC_STATRBYT_SIZE 24
178#define S6_GMAC_STATRPKT 0x0A0
179#define S6_GMAC_STATRPKT_SIZE 18
180#define S6_GMAC_STATRFCS 0x0A4
181#define S6_GMAC_STATRFCS_SIZE 12
182#define S6_GMAC_STATRMCA 0x0A8
183#define S6_GMAC_STATRMCA_SIZE 18
184#define S6_GMAC_STATRBCA 0x0AC
185#define S6_GMAC_STATRBCA_SIZE 22
186#define S6_GMAC_STATRXCF 0x0B0
187#define S6_GMAC_STATRXCF_SIZE 18
188#define S6_GMAC_STATRXPF 0x0B4
189#define S6_GMAC_STATRXPF_SIZE 12
190#define S6_GMAC_STATRXUO 0x0B8
191#define S6_GMAC_STATRXUO_SIZE 12
192#define S6_GMAC_STATRALN 0x0BC
193#define S6_GMAC_STATRALN_SIZE 12
194#define S6_GMAC_STATRFLR 0x0C0
195#define S6_GMAC_STATRFLR_SIZE 16
196#define S6_GMAC_STATRCDE 0x0C4
197#define S6_GMAC_STATRCDE_SIZE 12
198#define S6_GMAC_STATRCSE 0x0C8
199#define S6_GMAC_STATRCSE_SIZE 12
200#define S6_GMAC_STATRUND 0x0CC
201#define S6_GMAC_STATRUND_SIZE 12
202#define S6_GMAC_STATROVR 0x0D0
203#define S6_GMAC_STATROVR_SIZE 12
204#define S6_GMAC_STATRFRG 0x0D4
205#define S6_GMAC_STATRFRG_SIZE 12
206#define S6_GMAC_STATRJBR 0x0D8
207#define S6_GMAC_STATRJBR_SIZE 12
208#define S6_GMAC_STATRDRP 0x0DC
209#define S6_GMAC_STATRDRP_SIZE 12
210#define S6_GMAC_STATTBYT 0x0E0
211#define S6_GMAC_STATTBYT_SIZE 24
212#define S6_GMAC_STATTPKT 0x0E4
213#define S6_GMAC_STATTPKT_SIZE 18
214#define S6_GMAC_STATTMCA 0x0E8
215#define S6_GMAC_STATTMCA_SIZE 18
216#define S6_GMAC_STATTBCA 0x0EC
217#define S6_GMAC_STATTBCA_SIZE 18
218#define S6_GMAC_STATTXPF 0x0F0
219#define S6_GMAC_STATTXPF_SIZE 12
220#define S6_GMAC_STATTDFR 0x0F4
221#define S6_GMAC_STATTDFR_SIZE 12
222#define S6_GMAC_STATTEDF 0x0F8
223#define S6_GMAC_STATTEDF_SIZE 12
224#define S6_GMAC_STATTSCL 0x0FC
225#define S6_GMAC_STATTSCL_SIZE 12
226#define S6_GMAC_STATTMCL 0x100
227#define S6_GMAC_STATTMCL_SIZE 12
228#define S6_GMAC_STATTLCL 0x104
229#define S6_GMAC_STATTLCL_SIZE 12
230#define S6_GMAC_STATTXCL 0x108
231#define S6_GMAC_STATTXCL_SIZE 12
232#define S6_GMAC_STATTNCL 0x10C
233#define S6_GMAC_STATTNCL_SIZE 13
234#define S6_GMAC_STATTPFH 0x110
235#define S6_GMAC_STATTPFH_SIZE 12
236#define S6_GMAC_STATTDRP 0x114
237#define S6_GMAC_STATTDRP_SIZE 12
238#define S6_GMAC_STATTJBR 0x118
239#define S6_GMAC_STATTJBR_SIZE 12
240#define S6_GMAC_STATTFCS 0x11C
241#define S6_GMAC_STATTFCS_SIZE 12
242#define S6_GMAC_STATTXCF 0x120
243#define S6_GMAC_STATTXCF_SIZE 12
244#define S6_GMAC_STATTOVR 0x124
245#define S6_GMAC_STATTOVR_SIZE 12
246#define S6_GMAC_STATTUND 0x128
247#define S6_GMAC_STATTUND_SIZE 12
248#define S6_GMAC_STATTFRG 0x12C
249#define S6_GMAC_STATTFRG_SIZE 12
250#define S6_GMAC_STATCARRY(n) (0x130 + 4*(n))
251#define S6_GMAC_STATCARRYMSK(n) (0x138 + 4*(n))
252#define S6_GMAC_STATCARRY1_RDRP 0
253#define S6_GMAC_STATCARRY1_RJBR 1
254#define S6_GMAC_STATCARRY1_RFRG 2
255#define S6_GMAC_STATCARRY1_ROVR 3
256#define S6_GMAC_STATCARRY1_RUND 4
257#define S6_GMAC_STATCARRY1_RCSE 5
258#define S6_GMAC_STATCARRY1_RCDE 6
259#define S6_GMAC_STATCARRY1_RFLR 7
260#define S6_GMAC_STATCARRY1_RALN 8
261#define S6_GMAC_STATCARRY1_RXUO 9
262#define S6_GMAC_STATCARRY1_RXPF 10
263#define S6_GMAC_STATCARRY1_RXCF 11
264#define S6_GMAC_STATCARRY1_RBCA 12
265#define S6_GMAC_STATCARRY1_RMCA 13
266#define S6_GMAC_STATCARRY1_RFCS 14
267#define S6_GMAC_STATCARRY1_RPKT 15
268#define S6_GMAC_STATCARRY1_RBYT 16
269#define S6_GMAC_STATCARRY1_TRMGV 25
270#define S6_GMAC_STATCARRY1_TRMAX 26
271#define S6_GMAC_STATCARRY1_TR1K 27
272#define S6_GMAC_STATCARRY1_TR511 28
273#define S6_GMAC_STATCARRY1_TR255 29
274#define S6_GMAC_STATCARRY1_TR127 30
275#define S6_GMAC_STATCARRY1_TR64 31
276#define S6_GMAC_STATCARRY2_TDRP 0
277#define S6_GMAC_STATCARRY2_TPFH 1
278#define S6_GMAC_STATCARRY2_TNCL 2
279#define S6_GMAC_STATCARRY2_TXCL 3
280#define S6_GMAC_STATCARRY2_TLCL 4
281#define S6_GMAC_STATCARRY2_TMCL 5
282#define S6_GMAC_STATCARRY2_TSCL 6
283#define S6_GMAC_STATCARRY2_TEDF 7
284#define S6_GMAC_STATCARRY2_TDFR 8
285#define S6_GMAC_STATCARRY2_TXPF 9
286#define S6_GMAC_STATCARRY2_TBCA 10
287#define S6_GMAC_STATCARRY2_TMCA 11
288#define S6_GMAC_STATCARRY2_TPKT 12
289#define S6_GMAC_STATCARRY2_TBYT 13
290#define S6_GMAC_STATCARRY2_TFRG 14
291#define S6_GMAC_STATCARRY2_TUND 15
292#define S6_GMAC_STATCARRY2_TOVR 16
293#define S6_GMAC_STATCARRY2_TXCF 17
294#define S6_GMAC_STATCARRY2_TFCS 18
295#define S6_GMAC_STATCARRY2_TJBR 19
296
297#define S6_GMAC_HOST_PBLKCTRL 0x140
298#define S6_GMAC_HOST_PBLKCTRL_TXENA 0
299#define S6_GMAC_HOST_PBLKCTRL_RXENA 1
300#define S6_GMAC_HOST_PBLKCTRL_TXSRES 2
301#define S6_GMAC_HOST_PBLKCTRL_RXSRES 3
302#define S6_GMAC_HOST_PBLKCTRL_TXBSIZ 8
303#define S6_GMAC_HOST_PBLKCTRL_RXBSIZ 12
304#define S6_GMAC_HOST_PBLKCTRL_SIZ_16 4
305#define S6_GMAC_HOST_PBLKCTRL_SIZ_32 5
306#define S6_GMAC_HOST_PBLKCTRL_SIZ_64 6
307#define S6_GMAC_HOST_PBLKCTRL_SIZ_128 7
308#define S6_GMAC_HOST_PBLKCTRL_SIZ_MASK 0xF
309#define S6_GMAC_HOST_PBLKCTRL_STATENA 16
310#define S6_GMAC_HOST_PBLKCTRL_STATAUTOZ 17
311#define S6_GMAC_HOST_PBLKCTRL_STATCLEAR 18
312#define S6_GMAC_HOST_PBLKCTRL_RGMII 19
313#define S6_GMAC_HOST_INTMASK 0x144
314#define S6_GMAC_HOST_INTSTAT 0x148
315#define S6_GMAC_HOST_INT_TXBURSTOVER 3
316#define S6_GMAC_HOST_INT_TXPREWOVER 4
317#define S6_GMAC_HOST_INT_RXBURSTUNDER 5
318#define S6_GMAC_HOST_INT_RXPOSTRFULL 6
319#define S6_GMAC_HOST_INT_RXPOSTRUNDER 7
320#define S6_GMAC_HOST_RXFIFOHWM 0x14C
321#define S6_GMAC_HOST_CTRLFRAMXP 0x150
322#define S6_GMAC_HOST_DSTADDRLO(n) (0x160 + 8*(n))
323#define S6_GMAC_HOST_DSTADDRHI(n) (0x164 + 8*(n))
324#define S6_GMAC_HOST_DSTMASKLO(n) (0x180 + 8*(n))
325#define S6_GMAC_HOST_DSTMASKHI(n) (0x184 + 8*(n))
326
327#define S6_GMAC_BURST_PREWR 0x1B0
328#define S6_GMAC_BURST_PREWR_LEN 0
329#define S6_GMAC_BURST_PREWR_LEN_MASK ((1 << 20) - 1)
330#define S6_GMAC_BURST_PREWR_CFE 20
331#define S6_GMAC_BURST_PREWR_PPE 21
332#define S6_GMAC_BURST_PREWR_FCS 22
333#define S6_GMAC_BURST_PREWR_PAD 23
334#define S6_GMAC_BURST_POSTRD 0x1D0
335#define S6_GMAC_BURST_POSTRD_LEN 0
336#define S6_GMAC_BURST_POSTRD_LEN_MASK ((1 << 20) - 1)
337#define S6_GMAC_BURST_POSTRD_DROP 20
338
339
340/* data handling */
341
342#define S6_NUM_TX_SKB 8 /* must be larger than TX fifo size */
343#define S6_NUM_RX_SKB 16
344#define S6_MAX_FRLEN 1536
345
346struct s6gmac {
347 u32 reg;
348 u32 tx_dma;
349 u32 rx_dma;
350 u32 io;
351 u8 tx_chan;
352 u8 rx_chan;
353 spinlock_t lock;
354 u8 tx_skb_i, tx_skb_o;
355 u8 rx_skb_i, rx_skb_o;
356 struct sk_buff *tx_skb[S6_NUM_TX_SKB];
357 struct sk_buff *rx_skb[S6_NUM_RX_SKB];
358 unsigned long carry[sizeof(struct net_device_stats) / sizeof(long)];
359 unsigned long stats[sizeof(struct net_device_stats) / sizeof(long)];
360 struct phy_device *phydev;
361 struct {
362 struct mii_bus *bus;
363 int irq[PHY_MAX_ADDR];
364 } mii;
365 struct {
366 unsigned int mbit;
367 u8 giga;
368 u8 isup;
369 u8 full;
370 } link;
371};
372
373static void s6gmac_rx_fillfifo(struct s6gmac *pd)
374{
375 struct sk_buff *skb;
376 while ((((u8)(pd->rx_skb_i - pd->rx_skb_o)) < S6_NUM_RX_SKB) &&
377 (!s6dmac_fifo_full(pd->rx_dma, pd->rx_chan)) &&
378 (skb = dev_alloc_skb(S6_MAX_FRLEN + 2))) {
379 pd->rx_skb[(pd->rx_skb_i++) % S6_NUM_RX_SKB] = skb;
380 s6dmac_put_fifo_cache(pd->rx_dma, pd->rx_chan,
381 pd->io, (u32)skb->data, S6_MAX_FRLEN);
382 }
383}
384
385static void s6gmac_rx_interrupt(struct net_device *dev)
386{
387 struct s6gmac *pd = netdev_priv(dev);
388 u32 pfx;
389 struct sk_buff *skb;
390 while (((u8)(pd->rx_skb_i - pd->rx_skb_o)) >
391 s6dmac_pending_count(pd->rx_dma, pd->rx_chan)) {
392 skb = pd->rx_skb[(pd->rx_skb_o++) % S6_NUM_RX_SKB];
393 pfx = readl(pd->reg + S6_GMAC_BURST_POSTRD);
394 if (pfx & (1 << S6_GMAC_BURST_POSTRD_DROP)) {
395 dev_kfree_skb_irq(skb);
396 } else {
397 skb_put(skb, (pfx >> S6_GMAC_BURST_POSTRD_LEN)
398 & S6_GMAC_BURST_POSTRD_LEN_MASK);
399 skb->protocol = eth_type_trans(skb, dev);
400 skb->ip_summed = CHECKSUM_UNNECESSARY;
401 netif_rx(skb);
402 }
403 }
404}
405
406static void s6gmac_tx_interrupt(struct net_device *dev)
407{
408 struct s6gmac *pd = netdev_priv(dev);
409 while (((u8)(pd->tx_skb_i - pd->tx_skb_o)) >
410 s6dmac_pending_count(pd->tx_dma, pd->tx_chan)) {
411 dev_kfree_skb_irq(pd->tx_skb[(pd->tx_skb_o++) % S6_NUM_TX_SKB]);
412 }
413 if (!s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
414 netif_wake_queue(dev);
415}
416
417struct s6gmac_statinf {
418 unsigned reg_size : 4; /* 0: unused */
419 unsigned reg_off : 6;
420 unsigned net_index : 6;
421};
422
423#define S6_STATS_B (8 * sizeof(u32))
424#define S6_STATS_C(b, r, f) [b] = { \
425 BUILD_BUG_ON_ZERO(r##_SIZE < S6_GMAC_STAT_SIZE_MIN) + \
426 BUILD_BUG_ON_ZERO((r##_SIZE - (S6_GMAC_STAT_SIZE_MIN - 1)) \
427 >= (1<<4)) + \
428 r##_SIZE - (S6_GMAC_STAT_SIZE_MIN - 1), \
429 BUILD_BUG_ON_ZERO(((unsigned)((r - S6_GMAC_STAT_REGS) / sizeof(u32))) \
430 >= ((1<<6)-1)) + \
431 (r - S6_GMAC_STAT_REGS) / sizeof(u32), \
432 BUILD_BUG_ON_ZERO((offsetof(struct net_device_stats, f)) \
433 % sizeof(unsigned long)) + \
434 BUILD_BUG_ON_ZERO((((unsigned)(offsetof(struct net_device_stats, f)) \
435 / sizeof(unsigned long)) >= (1<<6))) + \
436 BUILD_BUG_ON_ZERO((sizeof(((struct net_device_stats *)0)->f) \
437 != sizeof(unsigned long))) + \
438 (offsetof(struct net_device_stats, f)) / sizeof(unsigned long)},
439
440static const struct s6gmac_statinf statinf[2][S6_STATS_B] = { {
441 S6_STATS_C(S6_GMAC_STATCARRY1_RBYT, S6_GMAC_STATRBYT, rx_bytes)
442 S6_STATS_C(S6_GMAC_STATCARRY1_RPKT, S6_GMAC_STATRPKT, rx_packets)
443 S6_STATS_C(S6_GMAC_STATCARRY1_RFCS, S6_GMAC_STATRFCS, rx_crc_errors)
444 S6_STATS_C(S6_GMAC_STATCARRY1_RMCA, S6_GMAC_STATRMCA, multicast)
445 S6_STATS_C(S6_GMAC_STATCARRY1_RALN, S6_GMAC_STATRALN, rx_frame_errors)
446 S6_STATS_C(S6_GMAC_STATCARRY1_RFLR, S6_GMAC_STATRFLR, rx_length_errors)
447 S6_STATS_C(S6_GMAC_STATCARRY1_RCDE, S6_GMAC_STATRCDE, rx_missed_errors)
448 S6_STATS_C(S6_GMAC_STATCARRY1_RUND, S6_GMAC_STATRUND, rx_length_errors)
449 S6_STATS_C(S6_GMAC_STATCARRY1_ROVR, S6_GMAC_STATROVR, rx_length_errors)
450 S6_STATS_C(S6_GMAC_STATCARRY1_RFRG, S6_GMAC_STATRFRG, rx_crc_errors)
451 S6_STATS_C(S6_GMAC_STATCARRY1_RJBR, S6_GMAC_STATRJBR, rx_crc_errors)
452 S6_STATS_C(S6_GMAC_STATCARRY1_RDRP, S6_GMAC_STATRDRP, rx_dropped)
453}, {
454 S6_STATS_C(S6_GMAC_STATCARRY2_TBYT, S6_GMAC_STATTBYT, tx_bytes)
455 S6_STATS_C(S6_GMAC_STATCARRY2_TPKT, S6_GMAC_STATTPKT, tx_packets)
456 S6_STATS_C(S6_GMAC_STATCARRY2_TEDF, S6_GMAC_STATTEDF, tx_aborted_errors)
457 S6_STATS_C(S6_GMAC_STATCARRY2_TXCL, S6_GMAC_STATTXCL, tx_aborted_errors)
458 S6_STATS_C(S6_GMAC_STATCARRY2_TNCL, S6_GMAC_STATTNCL, collisions)
459 S6_STATS_C(S6_GMAC_STATCARRY2_TDRP, S6_GMAC_STATTDRP, tx_dropped)
460 S6_STATS_C(S6_GMAC_STATCARRY2_TJBR, S6_GMAC_STATTJBR, tx_errors)
461 S6_STATS_C(S6_GMAC_STATCARRY2_TFCS, S6_GMAC_STATTFCS, tx_errors)
462 S6_STATS_C(S6_GMAC_STATCARRY2_TOVR, S6_GMAC_STATTOVR, tx_errors)
463 S6_STATS_C(S6_GMAC_STATCARRY2_TUND, S6_GMAC_STATTUND, tx_errors)
464 S6_STATS_C(S6_GMAC_STATCARRY2_TFRG, S6_GMAC_STATTFRG, tx_errors)
465} };
466
467static void s6gmac_stats_collect(struct s6gmac *pd,
468 const struct s6gmac_statinf *inf)
469{
470 int b;
471 for (b = 0; b < S6_STATS_B; b++) {
472 if (inf[b].reg_size) {
473 pd->stats[inf[b].net_index] +=
474 readl(pd->reg + S6_GMAC_STAT_REGS
475 + sizeof(u32) * inf[b].reg_off);
476 }
477 }
478}
479
480static void s6gmac_stats_carry(struct s6gmac *pd,
481 const struct s6gmac_statinf *inf, u32 mask)
482{
483 int b;
484 while (mask) {
485 b = fls(mask) - 1;
486 mask &= ~(1 << b);
487 pd->carry[inf[b].net_index] += (1 << inf[b].reg_size);
488 }
489}
490
491static inline u32 s6gmac_stats_pending(struct s6gmac *pd, int carry)
492{
493 int r = readl(pd->reg + S6_GMAC_STATCARRY(carry)) &
494 ~readl(pd->reg + S6_GMAC_STATCARRYMSK(carry));
495 return r;
496}
497
498static inline void s6gmac_stats_interrupt(struct s6gmac *pd, int carry)
499{
500 u32 mask;
501 mask = s6gmac_stats_pending(pd, carry);
502 if (mask) {
503 writel(mask, pd->reg + S6_GMAC_STATCARRY(carry));
504 s6gmac_stats_carry(pd, &statinf[carry][0], mask);
505 }
506}
507
508static irqreturn_t s6gmac_interrupt(int irq, void *dev_id)
509{
510 struct net_device *dev = (struct net_device *)dev_id;
511 struct s6gmac *pd = netdev_priv(dev);
512 if (!dev)
513 return IRQ_NONE;
514 spin_lock(&pd->lock);
515 if (s6dmac_termcnt_irq(pd->rx_dma, pd->rx_chan))
516 s6gmac_rx_interrupt(dev);
517 s6gmac_rx_fillfifo(pd);
518 if (s6dmac_termcnt_irq(pd->tx_dma, pd->tx_chan))
519 s6gmac_tx_interrupt(dev);
520 s6gmac_stats_interrupt(pd, 0);
521 s6gmac_stats_interrupt(pd, 1);
522 spin_unlock(&pd->lock);
523 return IRQ_HANDLED;
524}
525
526static inline void s6gmac_set_dstaddr(struct s6gmac *pd, int n,
527 u32 addrlo, u32 addrhi, u32 masklo, u32 maskhi)
528{
529 writel(addrlo, pd->reg + S6_GMAC_HOST_DSTADDRLO(n));
530 writel(addrhi, pd->reg + S6_GMAC_HOST_DSTADDRHI(n));
531 writel(masklo, pd->reg + S6_GMAC_HOST_DSTMASKLO(n));
532 writel(maskhi, pd->reg + S6_GMAC_HOST_DSTMASKHI(n));
533}
534
535static inline void s6gmac_stop_device(struct net_device *dev)
536{
537 struct s6gmac *pd = netdev_priv(dev);
538 writel(0, pd->reg + S6_GMAC_MACCONF1);
539}
540
541static inline void s6gmac_init_device(struct net_device *dev)
542{
543 struct s6gmac *pd = netdev_priv(dev);
544 int is_rgmii = !!(pd->phydev->supported
545 & (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half));
546#if 0
547 writel(1 << S6_GMAC_MACCONF1_SYNCTX |
548 1 << S6_GMAC_MACCONF1_SYNCRX |
549 1 << S6_GMAC_MACCONF1_TXFLOWCTRL |
550 1 << S6_GMAC_MACCONF1_RXFLOWCTRL |
551 1 << S6_GMAC_MACCONF1_RESTXFUNC |
552 1 << S6_GMAC_MACCONF1_RESRXFUNC |
553 1 << S6_GMAC_MACCONF1_RESTXMACCTRL |
554 1 << S6_GMAC_MACCONF1_RESRXMACCTRL,
555 pd->reg + S6_GMAC_MACCONF1);
556#endif
557 writel(1 << S6_GMAC_MACCONF1_SOFTRES, pd->reg + S6_GMAC_MACCONF1);
558 udelay(1000);
559 writel(1 << S6_GMAC_MACCONF1_TXENA | 1 << S6_GMAC_MACCONF1_RXENA,
560 pd->reg + S6_GMAC_MACCONF1);
561 writel(1 << S6_GMAC_HOST_PBLKCTRL_TXSRES |
562 1 << S6_GMAC_HOST_PBLKCTRL_RXSRES,
563 pd->reg + S6_GMAC_HOST_PBLKCTRL);
564 writel(S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_TXBSIZ |
565 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_RXBSIZ |
566 1 << S6_GMAC_HOST_PBLKCTRL_STATENA |
567 1 << S6_GMAC_HOST_PBLKCTRL_STATCLEAR |
568 is_rgmii << S6_GMAC_HOST_PBLKCTRL_RGMII,
569 pd->reg + S6_GMAC_HOST_PBLKCTRL);
570 writel(1 << S6_GMAC_MACCONF1_TXENA |
571 1 << S6_GMAC_MACCONF1_RXENA |
572 (dev->flags & IFF_LOOPBACK ? 1 : 0)
573 << S6_GMAC_MACCONF1_LOOPBACK,
574 pd->reg + S6_GMAC_MACCONF1);
575 writel(dev->mtu && (dev->mtu < (S6_MAX_FRLEN - ETH_HLEN-ETH_FCS_LEN)) ?
576 dev->mtu+ETH_HLEN+ETH_FCS_LEN : S6_MAX_FRLEN,
577 pd->reg + S6_GMAC_MACMAXFRAMELEN);
578 writel((pd->link.full ? 1 : 0) << S6_GMAC_MACCONF2_FULL |
579 1 << S6_GMAC_MACCONF2_PADCRCENA |
580 1 << S6_GMAC_MACCONF2_LENGTHFCHK |
581 (pd->link.giga ?
582 S6_GMAC_MACCONF2_IFMODE_BYTE :
583 S6_GMAC_MACCONF2_IFMODE_NIBBLE)
584 << S6_GMAC_MACCONF2_IFMODE |
585 7 << S6_GMAC_MACCONF2_PREAMBLELEN,
586 pd->reg + S6_GMAC_MACCONF2);
587 writel(0, pd->reg + S6_GMAC_MACSTATADDR1);
588 writel(0, pd->reg + S6_GMAC_MACSTATADDR2);
589 writel(1 << S6_GMAC_FIFOCONF0_WTMENREQ |
590 1 << S6_GMAC_FIFOCONF0_SRFENREQ |
591 1 << S6_GMAC_FIFOCONF0_FRFENREQ |
592 1 << S6_GMAC_FIFOCONF0_STFENREQ |
593 1 << S6_GMAC_FIFOCONF0_FTFENREQ,
594 pd->reg + S6_GMAC_FIFOCONF0);
595 writel(128 << S6_GMAC_FIFOCONF3_CFGFTTH |
596 128 << S6_GMAC_FIFOCONF3_CFGHWMFT,
597 pd->reg + S6_GMAC_FIFOCONF3);
598 writel((S6_GMAC_FIFOCONF_RSV_MASK & ~(
599 1 << S6_GMAC_FIFOCONF_RSV_RUNT |
600 1 << S6_GMAC_FIFOCONF_RSV_CRCERR |
601 1 << S6_GMAC_FIFOCONF_RSV_OK |
602 1 << S6_GMAC_FIFOCONF_RSV_DRIBBLE |
603 1 << S6_GMAC_FIFOCONF_RSV_CTRLFRAME |
604 1 << S6_GMAC_FIFOCONF_RSV_PAUSECTRL |
605 1 << S6_GMAC_FIFOCONF_RSV_UNOPCODE |
606 1 << S6_GMAC_FIFOCONF_RSV_TRUNCATED)) |
607 1 << S6_GMAC_FIFOCONF5_DROPLT64 |
608 pd->link.giga << S6_GMAC_FIFOCONF5_CFGBYTM |
609 1 << S6_GMAC_FIFOCONF5_RXDROPSIZE,
610 pd->reg + S6_GMAC_FIFOCONF5);
611 writel(1 << S6_GMAC_FIFOCONF_RSV_RUNT |
612 1 << S6_GMAC_FIFOCONF_RSV_CRCERR |
613 1 << S6_GMAC_FIFOCONF_RSV_DRIBBLE |
614 1 << S6_GMAC_FIFOCONF_RSV_CTRLFRAME |
615 1 << S6_GMAC_FIFOCONF_RSV_PAUSECTRL |
616 1 << S6_GMAC_FIFOCONF_RSV_UNOPCODE |
617 1 << S6_GMAC_FIFOCONF_RSV_TRUNCATED,
618 pd->reg + S6_GMAC_FIFOCONF4);
619 s6gmac_set_dstaddr(pd, 0,
620 0xFFFFFFFF, 0x0000FFFF, 0xFFFFFFFF, 0x0000FFFF);
621 s6gmac_set_dstaddr(pd, 1,
622 dev->dev_addr[5] |
623 dev->dev_addr[4] << 8 |
624 dev->dev_addr[3] << 16 |
625 dev->dev_addr[2] << 24,
626 dev->dev_addr[1] |
627 dev->dev_addr[0] << 8,
628 0xFFFFFFFF, 0x0000FFFF);
629 s6gmac_set_dstaddr(pd, 2,
630 0x00000000, 0x00000100, 0x00000000, 0x00000100);
631 s6gmac_set_dstaddr(pd, 3,
632 0x00000000, 0x00000000, 0x00000000, 0x00000000);
633 writel(1 << S6_GMAC_HOST_PBLKCTRL_TXENA |
634 1 << S6_GMAC_HOST_PBLKCTRL_RXENA |
635 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_TXBSIZ |
636 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_RXBSIZ |
637 1 << S6_GMAC_HOST_PBLKCTRL_STATENA |
638 1 << S6_GMAC_HOST_PBLKCTRL_STATCLEAR |
639 is_rgmii << S6_GMAC_HOST_PBLKCTRL_RGMII,
640 pd->reg + S6_GMAC_HOST_PBLKCTRL);
641}
642
643static void s6mii_enable(struct s6gmac *pd)
644{
645 writel(readl(pd->reg + S6_GMAC_MACCONF1) &
646 ~(1 << S6_GMAC_MACCONF1_SOFTRES),
647 pd->reg + S6_GMAC_MACCONF1);
648 writel((readl(pd->reg + S6_GMAC_MACMIICONF)
649 & ~(S6_GMAC_MACMIICONF_CSEL_MASK << S6_GMAC_MACMIICONF_CSEL))
650 | (S6_GMAC_MACMIICONF_CSEL_DIV168 << S6_GMAC_MACMIICONF_CSEL),
651 pd->reg + S6_GMAC_MACMIICONF);
652}
653
654static int s6mii_busy(struct s6gmac *pd, int tmo)
655{
656 while (readl(pd->reg + S6_GMAC_MACMIIINDI)) {
657 if (--tmo == 0)
658 return -ETIME;
659 udelay(64);
660 }
661 return 0;
662}
663
664static int s6mii_read(struct mii_bus *bus, int phy_addr, int regnum)
665{
666 struct s6gmac *pd = bus->priv;
667 s6mii_enable(pd);
668 if (s6mii_busy(pd, 256))
669 return -ETIME;
670 writel(phy_addr << S6_GMAC_MACMIIADDR_PHY |
671 regnum << S6_GMAC_MACMIIADDR_REG,
672 pd->reg + S6_GMAC_MACMIIADDR);
673 writel(1 << S6_GMAC_MACMIICMD_READ, pd->reg + S6_GMAC_MACMIICMD);
674 writel(0, pd->reg + S6_GMAC_MACMIICMD);
675 if (s6mii_busy(pd, 256))
676 return -ETIME;
677 return (u16)readl(pd->reg + S6_GMAC_MACMIISTAT);
678}
679
680static int s6mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
681{
682 struct s6gmac *pd = bus->priv;
683 s6mii_enable(pd);
684 if (s6mii_busy(pd, 256))
685 return -ETIME;
686 writel(phy_addr << S6_GMAC_MACMIIADDR_PHY |
687 regnum << S6_GMAC_MACMIIADDR_REG,
688 pd->reg + S6_GMAC_MACMIIADDR);
689 writel(value, pd->reg + S6_GMAC_MACMIICTRL);
690 if (s6mii_busy(pd, 256))
691 return -ETIME;
692 return 0;
693}
694
695static int s6mii_reset(struct mii_bus *bus)
696{
697 struct s6gmac *pd = bus->priv;
698 s6mii_enable(pd);
699 if (s6mii_busy(pd, PHY_INIT_TIMEOUT))
700 return -ETIME;
701 return 0;
702}
703
704static void s6gmac_set_rgmii_txclock(struct s6gmac *pd)
705{
706 u32 pllsel = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
707 pllsel &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC);
708 switch (pd->link.mbit) {
709 case 10:
710 pllsel |= S6_GREG1_PLLSEL_GMAC_2500KHZ << S6_GREG1_PLLSEL_GMAC;
711 break;
712 case 100:
713 pllsel |= S6_GREG1_PLLSEL_GMAC_25MHZ << S6_GREG1_PLLSEL_GMAC;
714 break;
715 case 1000:
716 pllsel |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC;
717 break;
718 default:
719 return;
720 }
721 writel(pllsel, S6_REG_GREG1 + S6_GREG1_PLLSEL);
722}
723
724static inline void s6gmac_linkisup(struct net_device *dev, int isup)
725{
726 struct s6gmac *pd = netdev_priv(dev);
727 struct phy_device *phydev = pd->phydev;
728
729 pd->link.full = phydev->duplex;
730 pd->link.giga = (phydev->speed == 1000);
731 if (pd->link.mbit != phydev->speed) {
732 pd->link.mbit = phydev->speed;
733 s6gmac_set_rgmii_txclock(pd);
734 }
735 pd->link.isup = isup;
736 if (isup)
737 netif_carrier_on(dev);
738 phy_print_status(phydev);
739}
740
741static void s6gmac_adjust_link(struct net_device *dev)
742{
743 struct s6gmac *pd = netdev_priv(dev);
744 struct phy_device *phydev = pd->phydev;
745 if (pd->link.isup &&
746 (!phydev->link ||
747 (pd->link.mbit != phydev->speed) ||
748 (pd->link.full != phydev->duplex))) {
749 pd->link.isup = 0;
750 netif_tx_disable(dev);
751 if (!phydev->link) {
752 netif_carrier_off(dev);
753 phy_print_status(phydev);
754 }
755 }
756 if (!pd->link.isup && phydev->link) {
757 if (pd->link.full != phydev->duplex) {
758 u32 maccfg = readl(pd->reg + S6_GMAC_MACCONF2);
759 if (phydev->duplex)
760 maccfg |= 1 << S6_GMAC_MACCONF2_FULL;
761 else
762 maccfg &= ~(1 << S6_GMAC_MACCONF2_FULL);
763 writel(maccfg, pd->reg + S6_GMAC_MACCONF2);
764 }
765
766 if (pd->link.giga != (phydev->speed == 1000)) {
767 u32 fifocfg = readl(pd->reg + S6_GMAC_FIFOCONF5);
768 u32 maccfg = readl(pd->reg + S6_GMAC_MACCONF2);
769 maccfg &= ~(S6_GMAC_MACCONF2_IFMODE_MASK
770 << S6_GMAC_MACCONF2_IFMODE);
771 if (phydev->speed == 1000) {
772 fifocfg |= 1 << S6_GMAC_FIFOCONF5_CFGBYTM;
773 maccfg |= S6_GMAC_MACCONF2_IFMODE_BYTE
774 << S6_GMAC_MACCONF2_IFMODE;
775 } else {
776 fifocfg &= ~(1 << S6_GMAC_FIFOCONF5_CFGBYTM);
777 maccfg |= S6_GMAC_MACCONF2_IFMODE_NIBBLE
778 << S6_GMAC_MACCONF2_IFMODE;
779 }
780 writel(fifocfg, pd->reg + S6_GMAC_FIFOCONF5);
781 writel(maccfg, pd->reg + S6_GMAC_MACCONF2);
782 }
783
784 if (!s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
785 netif_wake_queue(dev);
786 s6gmac_linkisup(dev, 1);
787 }
788}
789
790static inline int s6gmac_phy_start(struct net_device *dev)
791{
792 struct s6gmac *pd = netdev_priv(dev);
793 int i = 0;
794 struct phy_device *p = NULL;
795 while ((i < PHY_MAX_ADDR) && (!(p = pd->mii.bus->phy_map[i])))
796 i++;
797 p = phy_connect(dev, dev_name(&p->dev), &s6gmac_adjust_link, 0,
798 PHY_INTERFACE_MODE_RGMII);
799 if (IS_ERR(p)) {
800 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
801 return PTR_ERR(p);
802 }
803 p->supported &= PHY_GBIT_FEATURES;
804 p->advertising = p->supported;
805 pd->phydev = p;
806 return 0;
807}
808
809static inline void s6gmac_init_stats(struct net_device *dev)
810{
811 struct s6gmac *pd = netdev_priv(dev);
812 u32 mask;
813 mask = 1 << S6_GMAC_STATCARRY1_RDRP |
814 1 << S6_GMAC_STATCARRY1_RJBR |
815 1 << S6_GMAC_STATCARRY1_RFRG |
816 1 << S6_GMAC_STATCARRY1_ROVR |
817 1 << S6_GMAC_STATCARRY1_RUND |
818 1 << S6_GMAC_STATCARRY1_RCDE |
819 1 << S6_GMAC_STATCARRY1_RFLR |
820 1 << S6_GMAC_STATCARRY1_RALN |
821 1 << S6_GMAC_STATCARRY1_RMCA |
822 1 << S6_GMAC_STATCARRY1_RFCS |
823 1 << S6_GMAC_STATCARRY1_RPKT |
824 1 << S6_GMAC_STATCARRY1_RBYT;
825 writel(mask, pd->reg + S6_GMAC_STATCARRY(0));
826 writel(~mask, pd->reg + S6_GMAC_STATCARRYMSK(0));
827 mask = 1 << S6_GMAC_STATCARRY2_TDRP |
828 1 << S6_GMAC_STATCARRY2_TNCL |
829 1 << S6_GMAC_STATCARRY2_TXCL |
830 1 << S6_GMAC_STATCARRY2_TEDF |
831 1 << S6_GMAC_STATCARRY2_TPKT |
832 1 << S6_GMAC_STATCARRY2_TBYT |
833 1 << S6_GMAC_STATCARRY2_TFRG |
834 1 << S6_GMAC_STATCARRY2_TUND |
835 1 << S6_GMAC_STATCARRY2_TOVR |
836 1 << S6_GMAC_STATCARRY2_TFCS |
837 1 << S6_GMAC_STATCARRY2_TJBR;
838 writel(mask, pd->reg + S6_GMAC_STATCARRY(1));
839 writel(~mask, pd->reg + S6_GMAC_STATCARRYMSK(1));
840}
841
842static inline void s6gmac_init_dmac(struct net_device *dev)
843{
844 struct s6gmac *pd = netdev_priv(dev);
845 s6dmac_disable_chan(pd->tx_dma, pd->tx_chan);
846 s6dmac_disable_chan(pd->rx_dma, pd->rx_chan);
847 s6dmac_disable_error_irqs(pd->tx_dma, 1 << S6_HIFDMA_GMACTX);
848 s6dmac_disable_error_irqs(pd->rx_dma, 1 << S6_HIFDMA_GMACRX);
849}
850
851static int s6gmac_tx(struct sk_buff *skb, struct net_device *dev)
852{
853 struct s6gmac *pd = netdev_priv(dev);
854 unsigned long flags;
855
856 spin_lock_irqsave(&pd->lock, flags);
857 writel(skb->len << S6_GMAC_BURST_PREWR_LEN |
858 0 << S6_GMAC_BURST_PREWR_CFE |
859 1 << S6_GMAC_BURST_PREWR_PPE |
860 1 << S6_GMAC_BURST_PREWR_FCS |
861 ((skb->len < ETH_ZLEN) ? 1 : 0) << S6_GMAC_BURST_PREWR_PAD,
862 pd->reg + S6_GMAC_BURST_PREWR);
863 s6dmac_put_fifo_cache(pd->tx_dma, pd->tx_chan,
864 (u32)skb->data, pd->io, skb->len);
865 if (s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
866 netif_stop_queue(dev);
867 if (((u8)(pd->tx_skb_i - pd->tx_skb_o)) >= S6_NUM_TX_SKB) {
868 printk(KERN_ERR "GMAC BUG: skb tx ring overflow [%x, %x]\n",
869 pd->tx_skb_o, pd->tx_skb_i);
870 BUG();
871 }
872 pd->tx_skb[(pd->tx_skb_i++) % S6_NUM_TX_SKB] = skb;
873 spin_unlock_irqrestore(&pd->lock, flags);
874 return 0;
875}
876
877static void s6gmac_tx_timeout(struct net_device *dev)
878{
879 struct s6gmac *pd = netdev_priv(dev);
880 unsigned long flags;
881 spin_lock_irqsave(&pd->lock, flags);
882 s6gmac_tx_interrupt(dev);
883 spin_unlock_irqrestore(&pd->lock, flags);
884}
885
886static int s6gmac_open(struct net_device *dev)
887{
888 struct s6gmac *pd = netdev_priv(dev);
889 unsigned long flags;
890 phy_read_status(pd->phydev);
891 spin_lock_irqsave(&pd->lock, flags);
892 pd->link.mbit = 0;
893 s6gmac_linkisup(dev, pd->phydev->link);
894 s6gmac_init_device(dev);
895 s6gmac_init_stats(dev);
896 s6gmac_init_dmac(dev);
897 s6gmac_rx_fillfifo(pd);
898 s6dmac_enable_chan(pd->rx_dma, pd->rx_chan,
899 2, 1, 0, 1, 0, 0, 0, 7, -1, 2, 0, 1);
900 s6dmac_enable_chan(pd->tx_dma, pd->tx_chan,
901 2, 0, 1, 0, 0, 0, 0, 7, -1, 2, 0, 1);
902 writel(0 << S6_GMAC_HOST_INT_TXBURSTOVER |
903 0 << S6_GMAC_HOST_INT_TXPREWOVER |
904 0 << S6_GMAC_HOST_INT_RXBURSTUNDER |
905 0 << S6_GMAC_HOST_INT_RXPOSTRFULL |
906 0 << S6_GMAC_HOST_INT_RXPOSTRUNDER,
907 pd->reg + S6_GMAC_HOST_INTMASK);
908 spin_unlock_irqrestore(&pd->lock, flags);
909 phy_start(pd->phydev);
910 netif_start_queue(dev);
911 return 0;
912}
913
914static int s6gmac_stop(struct net_device *dev)
915{
916 struct s6gmac *pd = netdev_priv(dev);
917 unsigned long flags;
918 netif_stop_queue(dev);
919 phy_stop(pd->phydev);
920 spin_lock_irqsave(&pd->lock, flags);
921 s6gmac_init_dmac(dev);
922 s6gmac_stop_device(dev);
923 while (pd->tx_skb_i != pd->tx_skb_o)
924 dev_kfree_skb(pd->tx_skb[(pd->tx_skb_o++) % S6_NUM_TX_SKB]);
925 while (pd->rx_skb_i != pd->rx_skb_o)
926 dev_kfree_skb(pd->rx_skb[(pd->rx_skb_o++) % S6_NUM_RX_SKB]);
927 spin_unlock_irqrestore(&pd->lock, flags);
928 return 0;
929}
930
931static struct net_device_stats *s6gmac_stats(struct net_device *dev)
932{
933 struct s6gmac *pd = netdev_priv(dev);
934 struct net_device_stats *st = (struct net_device_stats *)&pd->stats;
935 int i;
936 do {
937 unsigned long flags;
938 spin_lock_irqsave(&pd->lock, flags);
939 for (i = 0; i < sizeof(pd->stats) / sizeof(unsigned long); i++)
940 pd->stats[i] =
941 pd->carry[i] << (S6_GMAC_STAT_SIZE_MIN - 1);
942 s6gmac_stats_collect(pd, &statinf[0][0]);
943 s6gmac_stats_collect(pd, &statinf[1][0]);
944 i = s6gmac_stats_pending(pd, 0) |
945 s6gmac_stats_pending(pd, 1);
946 spin_unlock_irqrestore(&pd->lock, flags);
947 } while (i);
948 st->rx_errors = st->rx_crc_errors +
949 st->rx_frame_errors +
950 st->rx_length_errors +
951 st->rx_missed_errors;
952 st->tx_errors += st->tx_aborted_errors;
953 return st;
954}
955
956static int __devinit s6gmac_probe(struct platform_device *pdev)
957{
958 struct net_device *dev;
959 struct s6gmac *pd;
960 int res;
961 unsigned long i;
962 struct mii_bus *mb;
963 dev = alloc_etherdev(sizeof(*pd));
964 if (!dev) {
965 printk(KERN_ERR DRV_PRMT "etherdev alloc failed, aborting.\n");
966 return -ENOMEM;
967 }
968 dev->open = s6gmac_open;
969 dev->stop = s6gmac_stop;
970 dev->hard_start_xmit = s6gmac_tx;
971 dev->tx_timeout = s6gmac_tx_timeout;
972 dev->watchdog_timeo = HZ;
973 dev->get_stats = s6gmac_stats;
974 dev->irq = platform_get_irq(pdev, 0);
975 pd = netdev_priv(dev);
976 memset(pd, 0, sizeof(*pd));
977 spin_lock_init(&pd->lock);
978 pd->reg = platform_get_resource(pdev, IORESOURCE_MEM, 0)->start;
979 i = platform_get_resource(pdev, IORESOURCE_DMA, 0)->start;
980 pd->tx_dma = DMA_MASK_DMAC(i);
981 pd->tx_chan = DMA_INDEX_CHNL(i);
982 i = platform_get_resource(pdev, IORESOURCE_DMA, 1)->start;
983 pd->rx_dma = DMA_MASK_DMAC(i);
984 pd->rx_chan = DMA_INDEX_CHNL(i);
985 pd->io = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
986 res = request_irq(dev->irq, s6gmac_interrupt, 0, dev->name, dev);
987 if (res) {
988 printk(KERN_ERR DRV_PRMT "irq request failed: %d\n", dev->irq);
989 goto errirq;
990 }
991 res = register_netdev(dev);
992 if (res) {
993 printk(KERN_ERR DRV_PRMT "error registering device %s\n",
994 dev->name);
995 goto errdev;
996 }
997 mb = mdiobus_alloc();
998 if (!mb) {
999 printk(KERN_ERR DRV_PRMT "error allocating mii bus\n");
1000 goto errmii;
1001 }
1002 mb->name = "s6gmac_mii";
1003 mb->read = s6mii_read;
1004 mb->write = s6mii_write;
1005 mb->reset = s6mii_reset;
1006 mb->priv = pd;
1007 snprintf(mb->id, MII_BUS_ID_SIZE, "0");
1008 mb->phy_mask = ~(1 << 0);
1009 mb->irq = &pd->mii.irq[0];
1010 for (i = 0; i < PHY_MAX_ADDR; i++) {
1011 int n = platform_get_irq(pdev, i + 1);
1012 if (n < 0)
1013 n = PHY_POLL;
1014 pd->mii.irq[i] = n;
1015 }
1016 mdiobus_register(mb);
1017 pd->mii.bus = mb;
1018 res = s6gmac_phy_start(dev);
1019 if (res)
1020 return res;
1021 platform_set_drvdata(pdev, dev);
1022 return 0;
1023errmii:
1024 unregister_netdev(dev);
1025errdev:
1026 free_irq(dev->irq, dev);
1027errirq:
1028 free_netdev(dev);
1029 return res;
1030}
1031
1032static int __devexit s6gmac_remove(struct platform_device *pdev)
1033{
1034 struct net_device *dev = platform_get_drvdata(pdev);
1035 if (dev) {
1036 struct s6gmac *pd = netdev_priv(dev);
1037 mdiobus_unregister(pd->mii.bus);
1038 unregister_netdev(dev);
1039 free_irq(dev->irq, dev);
1040 free_netdev(dev);
1041 platform_set_drvdata(pdev, NULL);
1042 }
1043 return 0;
1044}
1045
1046static struct platform_driver s6gmac_driver = {
1047 .probe = s6gmac_probe,
1048 .remove = __devexit_p(s6gmac_remove),
1049 .driver = {
1050 .name = "s6gmac",
1051 .owner = THIS_MODULE,
1052 },
1053};
1054
1055static int __init s6gmac_init(void)
1056{
1057 printk(KERN_INFO DRV_PRMT "S6 GMAC ethernet driver\n");
1058 return platform_driver_register(&s6gmac_driver);
1059}
1060
1061
1062static void __exit s6gmac_exit(void)
1063{
1064 platform_driver_unregister(&s6gmac_driver);
1065}
1066
1067module_init(s6gmac_init);
1068module_exit(s6gmac_exit);
1069
1070MODULE_LICENSE("GPL");
1071MODULE_DESCRIPTION("S6105 on chip Ethernet driver");
1072MODULE_AUTHOR("Oskar Schirmer <os@emlix.com>");