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1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/crc32.h>
42#include <linux/spinlock.h>
43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/irq.h>
46#include <linux/uaccess.h>
47#include <linux/phy.h>
48
49#include <asm/processor.h>
50
51#define DRV_NAME "r6040"
52#define DRV_VERSION "0.27"
53#define DRV_RELDATE "23Feb2011"
54
55/* PHY CHIP Address */
56#define PHY1_ADDR 1 /* For MAC1 */
57#define PHY2_ADDR 3 /* For MAC2 */
58#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61/* Time in jiffies before concluding the transmitter is hung. */
62#define TX_TIMEOUT (6000 * HZ / 1000)
63
64/* RDC MAC I/O Size */
65#define R6040_IO_SIZE 256
66
67/* MAX RDC MAC */
68#define MAX_MAC 2
69
70/* MAC registers */
71#define MCR0 0x00 /* Control register 0 */
72#define MCR0_PROMISC 0x0020 /* Promiscuous mode */
73#define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
74#define MCR1 0x04 /* Control register 1 */
75#define MAC_RST 0x0001 /* Reset the MAC */
76#define MBCR 0x08 /* Bus control */
77#define MT_ICR 0x0C /* TX interrupt control */
78#define MR_ICR 0x10 /* RX interrupt control */
79#define MTPR 0x14 /* TX poll command register */
80#define MR_BSR 0x18 /* RX buffer size */
81#define MR_DCR 0x1A /* RX descriptor control */
82#define MLSR 0x1C /* Last status */
83#define MMDIO 0x20 /* MDIO control register */
84#define MDIO_WRITE 0x4000 /* MDIO write */
85#define MDIO_READ 0x2000 /* MDIO read */
86#define MMRD 0x24 /* MDIO read data register */
87#define MMWD 0x28 /* MDIO write data register */
88#define MTD_SA0 0x2C /* TX descriptor start address 0 */
89#define MTD_SA1 0x30 /* TX descriptor start address 1 */
90#define MRD_SA0 0x34 /* RX descriptor start address 0 */
91#define MRD_SA1 0x38 /* RX descriptor start address 1 */
92#define MISR 0x3C /* Status register */
93#define MIER 0x40 /* INT enable register */
94#define MSK_INT 0x0000 /* Mask off interrupts */
95#define RX_FINISH 0x0001 /* RX finished */
96#define RX_NO_DESC 0x0002 /* No RX descriptor available */
97#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
98#define RX_EARLY 0x0008 /* RX early */
99#define TX_FINISH 0x0010 /* TX finished */
100#define TX_EARLY 0x0080 /* TX early */
101#define EVENT_OVRFL 0x0100 /* Event counter overflow */
102#define LINK_CHANGED 0x0200 /* PHY link changed */
103#define ME_CISR 0x44 /* Event counter INT status */
104#define ME_CIER 0x48 /* Event counter INT enable */
105#define MR_CNT 0x50 /* Successfully received packet counter */
106#define ME_CNT0 0x52 /* Event counter 0 */
107#define ME_CNT1 0x54 /* Event counter 1 */
108#define ME_CNT2 0x56 /* Event counter 2 */
109#define ME_CNT3 0x58 /* Event counter 3 */
110#define MT_CNT 0x5A /* Successfully transmit packet counter */
111#define ME_CNT4 0x5C /* Event counter 4 */
112#define MP_CNT 0x5E /* Pause frame counter register */
113#define MAR0 0x60 /* Hash table 0 */
114#define MAR1 0x62 /* Hash table 1 */
115#define MAR2 0x64 /* Hash table 2 */
116#define MAR3 0x66 /* Hash table 3 */
117#define MID_0L 0x68 /* Multicast address MID0 Low */
118#define MID_0M 0x6A /* Multicast address MID0 Medium */
119#define MID_0H 0x6C /* Multicast address MID0 High */
120#define MID_1L 0x70 /* MID1 Low */
121#define MID_1M 0x72 /* MID1 Medium */
122#define MID_1H 0x74 /* MID1 High */
123#define MID_2L 0x78 /* MID2 Low */
124#define MID_2M 0x7A /* MID2 Medium */
125#define MID_2H 0x7C /* MID2 High */
126#define MID_3L 0x80 /* MID3 Low */
127#define MID_3M 0x82 /* MID3 Medium */
128#define MID_3H 0x84 /* MID3 High */
129#define PHY_CC 0x88 /* PHY status change configuration register */
130#define PHY_ST 0x8A /* PHY status register */
131#define MAC_SM 0xAC /* MAC status machine */
132#define MAC_ID 0xBE /* Identifier register */
133
134#define TX_DCNT 0x80 /* TX descriptor count */
135#define RX_DCNT 0x80 /* RX descriptor count */
136#define MAX_BUF_SIZE 0x600
137#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
138#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
139#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
140#define MCAST_MAX 3 /* Max number multicast addresses to filter */
141
142/* Descriptor status */
143#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
144#define DSC_RX_OK 0x4000 /* RX was successful */
145#define DSC_RX_ERR 0x0800 /* RX PHY error */
146#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
147#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
148#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
149#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
150#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
151#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
152#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
153#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
154#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
155#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
156
157/* PHY settings */
158#define ICPLUS_PHY_ID 0x0243
159
160MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
161 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
162 "Florian Fainelli <florian@openwrt.org>");
163MODULE_LICENSE("GPL");
164MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
165MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
166
167/* RX and TX interrupts that we handle */
168#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
169#define TX_INTS (TX_FINISH)
170#define INT_MASK (RX_INTS | TX_INTS)
171
172struct r6040_descriptor {
173 u16 status, len; /* 0-3 */
174 __le32 buf; /* 4-7 */
175 __le32 ndesc; /* 8-B */
176 u32 rev1; /* C-F */
177 char *vbufp; /* 10-13 */
178 struct r6040_descriptor *vndescp; /* 14-17 */
179 struct sk_buff *skb_ptr; /* 18-1B */
180 u32 rev2; /* 1C-1F */
181} __attribute__((aligned(32)));
182
183struct r6040_private {
184 spinlock_t lock; /* driver lock */
185 struct pci_dev *pdev;
186 struct r6040_descriptor *rx_insert_ptr;
187 struct r6040_descriptor *rx_remove_ptr;
188 struct r6040_descriptor *tx_insert_ptr;
189 struct r6040_descriptor *tx_remove_ptr;
190 struct r6040_descriptor *rx_ring;
191 struct r6040_descriptor *tx_ring;
192 dma_addr_t rx_ring_dma;
193 dma_addr_t tx_ring_dma;
194 u16 tx_free_desc, phy_addr;
195 u16 mcr0, mcr1;
196 struct net_device *dev;
197 struct mii_bus *mii_bus;
198 struct napi_struct napi;
199 void __iomem *base;
200 struct phy_device *phydev;
201 int old_link;
202 int old_duplex;
203};
204
205static char version[] __devinitdata = DRV_NAME
206 ": RDC R6040 NAPI net driver,"
207 "version "DRV_VERSION " (" DRV_RELDATE ")";
208
209static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
210
211/* Read a word data from PHY Chip */
212static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
213{
214 int limit = 2048;
215 u16 cmd;
216
217 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
218 /* Wait for the read bit to be cleared */
219 while (limit--) {
220 cmd = ioread16(ioaddr + MMDIO);
221 if (!(cmd & MDIO_READ))
222 break;
223 }
224
225 return ioread16(ioaddr + MMRD);
226}
227
228/* Write a word data from PHY Chip */
229static void r6040_phy_write(void __iomem *ioaddr,
230 int phy_addr, int reg, u16 val)
231{
232 int limit = 2048;
233 u16 cmd;
234
235 iowrite16(val, ioaddr + MMWD);
236 /* Write the command to the MDIO bus */
237 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
238 /* Wait for the write bit to be cleared */
239 while (limit--) {
240 cmd = ioread16(ioaddr + MMDIO);
241 if (!(cmd & MDIO_WRITE))
242 break;
243 }
244}
245
246static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
247{
248 struct net_device *dev = bus->priv;
249 struct r6040_private *lp = netdev_priv(dev);
250 void __iomem *ioaddr = lp->base;
251
252 return r6040_phy_read(ioaddr, phy_addr, reg);
253}
254
255static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
256 int reg, u16 value)
257{
258 struct net_device *dev = bus->priv;
259 struct r6040_private *lp = netdev_priv(dev);
260 void __iomem *ioaddr = lp->base;
261
262 r6040_phy_write(ioaddr, phy_addr, reg, value);
263
264 return 0;
265}
266
267static int r6040_mdiobus_reset(struct mii_bus *bus)
268{
269 return 0;
270}
271
272static void r6040_free_txbufs(struct net_device *dev)
273{
274 struct r6040_private *lp = netdev_priv(dev);
275 int i;
276
277 for (i = 0; i < TX_DCNT; i++) {
278 if (lp->tx_insert_ptr->skb_ptr) {
279 pci_unmap_single(lp->pdev,
280 le32_to_cpu(lp->tx_insert_ptr->buf),
281 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
282 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
283 lp->tx_insert_ptr->skb_ptr = NULL;
284 }
285 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
286 }
287}
288
289static void r6040_free_rxbufs(struct net_device *dev)
290{
291 struct r6040_private *lp = netdev_priv(dev);
292 int i;
293
294 for (i = 0; i < RX_DCNT; i++) {
295 if (lp->rx_insert_ptr->skb_ptr) {
296 pci_unmap_single(lp->pdev,
297 le32_to_cpu(lp->rx_insert_ptr->buf),
298 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
299 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
300 lp->rx_insert_ptr->skb_ptr = NULL;
301 }
302 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
303 }
304}
305
306static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
307 dma_addr_t desc_dma, int size)
308{
309 struct r6040_descriptor *desc = desc_ring;
310 dma_addr_t mapping = desc_dma;
311
312 while (size-- > 0) {
313 mapping += sizeof(*desc);
314 desc->ndesc = cpu_to_le32(mapping);
315 desc->vndescp = desc + 1;
316 desc++;
317 }
318 desc--;
319 desc->ndesc = cpu_to_le32(desc_dma);
320 desc->vndescp = desc_ring;
321}
322
323static void r6040_init_txbufs(struct net_device *dev)
324{
325 struct r6040_private *lp = netdev_priv(dev);
326
327 lp->tx_free_desc = TX_DCNT;
328
329 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
330 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
331}
332
333static int r6040_alloc_rxbufs(struct net_device *dev)
334{
335 struct r6040_private *lp = netdev_priv(dev);
336 struct r6040_descriptor *desc;
337 struct sk_buff *skb;
338 int rc;
339
340 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
341 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
342
343 /* Allocate skbs for the rx descriptors */
344 desc = lp->rx_ring;
345 do {
346 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
347 if (!skb) {
348 netdev_err(dev, "failed to alloc skb for rx\n");
349 rc = -ENOMEM;
350 goto err_exit;
351 }
352 desc->skb_ptr = skb;
353 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
354 desc->skb_ptr->data,
355 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
356 desc->status = DSC_OWNER_MAC;
357 desc = desc->vndescp;
358 } while (desc != lp->rx_ring);
359
360 return 0;
361
362err_exit:
363 /* Deallocate all previously allocated skbs */
364 r6040_free_rxbufs(dev);
365 return rc;
366}
367
368static void r6040_init_mac_regs(struct net_device *dev)
369{
370 struct r6040_private *lp = netdev_priv(dev);
371 void __iomem *ioaddr = lp->base;
372 int limit = 2048;
373 u16 cmd;
374
375 /* Mask Off Interrupt */
376 iowrite16(MSK_INT, ioaddr + MIER);
377
378 /* Reset RDC MAC */
379 iowrite16(MAC_RST, ioaddr + MCR1);
380 while (limit--) {
381 cmd = ioread16(ioaddr + MCR1);
382 if (cmd & 0x1)
383 break;
384 }
385 /* Reset internal state machine */
386 iowrite16(2, ioaddr + MAC_SM);
387 iowrite16(0, ioaddr + MAC_SM);
388 mdelay(5);
389
390 /* MAC Bus Control Register */
391 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
392
393 /* Buffer Size Register */
394 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
395
396 /* Write TX ring start address */
397 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
398 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
399
400 /* Write RX ring start address */
401 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
402 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
403
404 /* Set interrupt waiting time and packet numbers */
405 iowrite16(0, ioaddr + MT_ICR);
406 iowrite16(0, ioaddr + MR_ICR);
407
408 /* Enable interrupts */
409 iowrite16(INT_MASK, ioaddr + MIER);
410
411 /* Enable TX and RX */
412 iowrite16(lp->mcr0 | 0x0002, ioaddr);
413
414 /* Let TX poll the descriptors
415 * we may got called by r6040_tx_timeout which has left
416 * some unsent tx buffers */
417 iowrite16(0x01, ioaddr + MTPR);
418}
419
420static void r6040_tx_timeout(struct net_device *dev)
421{
422 struct r6040_private *priv = netdev_priv(dev);
423 void __iomem *ioaddr = priv->base;
424
425 netdev_warn(dev, "transmit timed out, int enable %4.4x "
426 "status %4.4x\n",
427 ioread16(ioaddr + MIER),
428 ioread16(ioaddr + MISR));
429
430 dev->stats.tx_errors++;
431
432 /* Reset MAC and re-init all registers */
433 r6040_init_mac_regs(dev);
434}
435
436static struct net_device_stats *r6040_get_stats(struct net_device *dev)
437{
438 struct r6040_private *priv = netdev_priv(dev);
439 void __iomem *ioaddr = priv->base;
440 unsigned long flags;
441
442 spin_lock_irqsave(&priv->lock, flags);
443 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
444 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
445 spin_unlock_irqrestore(&priv->lock, flags);
446
447 return &dev->stats;
448}
449
450/* Stop RDC MAC and Free the allocated resource */
451static void r6040_down(struct net_device *dev)
452{
453 struct r6040_private *lp = netdev_priv(dev);
454 void __iomem *ioaddr = lp->base;
455 int limit = 2048;
456 u16 *adrp;
457 u16 cmd;
458
459 /* Stop MAC */
460 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
461 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
462 while (limit--) {
463 cmd = ioread16(ioaddr + MCR1);
464 if (cmd & 0x1)
465 break;
466 }
467
468 /* Restore MAC Address to MIDx */
469 adrp = (u16 *) dev->dev_addr;
470 iowrite16(adrp[0], ioaddr + MID_0L);
471 iowrite16(adrp[1], ioaddr + MID_0M);
472 iowrite16(adrp[2], ioaddr + MID_0H);
473}
474
475static int r6040_close(struct net_device *dev)
476{
477 struct r6040_private *lp = netdev_priv(dev);
478 struct pci_dev *pdev = lp->pdev;
479
480 spin_lock_irq(&lp->lock);
481 napi_disable(&lp->napi);
482 netif_stop_queue(dev);
483 r6040_down(dev);
484
485 free_irq(dev->irq, dev);
486
487 /* Free RX buffer */
488 r6040_free_rxbufs(dev);
489
490 /* Free TX buffer */
491 r6040_free_txbufs(dev);
492
493 spin_unlock_irq(&lp->lock);
494
495 /* Free Descriptor memory */
496 if (lp->rx_ring) {
497 pci_free_consistent(pdev,
498 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
499 lp->rx_ring = NULL;
500 }
501
502 if (lp->tx_ring) {
503 pci_free_consistent(pdev,
504 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
505 lp->tx_ring = NULL;
506 }
507
508 return 0;
509}
510
511static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
512{
513 struct r6040_private *lp = netdev_priv(dev);
514
515 if (!lp->phydev)
516 return -EINVAL;
517
518 return phy_mii_ioctl(lp->phydev, rq, cmd);
519}
520
521static int r6040_rx(struct net_device *dev, int limit)
522{
523 struct r6040_private *priv = netdev_priv(dev);
524 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
525 struct sk_buff *skb_ptr, *new_skb;
526 int count = 0;
527 u16 err;
528
529 /* Limit not reached and the descriptor belongs to the CPU */
530 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
531 /* Read the descriptor status */
532 err = descptr->status;
533 /* Global error status set */
534 if (err & DSC_RX_ERR) {
535 /* RX dribble */
536 if (err & DSC_RX_ERR_DRI)
537 dev->stats.rx_frame_errors++;
538 /* Buffer length exceeded */
539 if (err & DSC_RX_ERR_BUF)
540 dev->stats.rx_length_errors++;
541 /* Packet too long */
542 if (err & DSC_RX_ERR_LONG)
543 dev->stats.rx_length_errors++;
544 /* Packet < 64 bytes */
545 if (err & DSC_RX_ERR_RUNT)
546 dev->stats.rx_length_errors++;
547 /* CRC error */
548 if (err & DSC_RX_ERR_CRC) {
549 spin_lock(&priv->lock);
550 dev->stats.rx_crc_errors++;
551 spin_unlock(&priv->lock);
552 }
553 goto next_descr;
554 }
555
556 /* Packet successfully received */
557 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
558 if (!new_skb) {
559 dev->stats.rx_dropped++;
560 goto next_descr;
561 }
562 skb_ptr = descptr->skb_ptr;
563 skb_ptr->dev = priv->dev;
564
565 /* Do not count the CRC */
566 skb_put(skb_ptr, descptr->len - 4);
567 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
568 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
569 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
570
571 /* Send to upper layer */
572 netif_receive_skb(skb_ptr);
573 dev->stats.rx_packets++;
574 dev->stats.rx_bytes += descptr->len - 4;
575
576 /* put new skb into descriptor */
577 descptr->skb_ptr = new_skb;
578 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
579 descptr->skb_ptr->data,
580 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
581
582next_descr:
583 /* put the descriptor back to the MAC */
584 descptr->status = DSC_OWNER_MAC;
585 descptr = descptr->vndescp;
586 count++;
587 }
588 priv->rx_remove_ptr = descptr;
589
590 return count;
591}
592
593static void r6040_tx(struct net_device *dev)
594{
595 struct r6040_private *priv = netdev_priv(dev);
596 struct r6040_descriptor *descptr;
597 void __iomem *ioaddr = priv->base;
598 struct sk_buff *skb_ptr;
599 u16 err;
600
601 spin_lock(&priv->lock);
602 descptr = priv->tx_remove_ptr;
603 while (priv->tx_free_desc < TX_DCNT) {
604 /* Check for errors */
605 err = ioread16(ioaddr + MLSR);
606
607 if (err & 0x0200)
608 dev->stats.rx_fifo_errors++;
609 if (err & (0x2000 | 0x4000))
610 dev->stats.tx_carrier_errors++;
611
612 if (descptr->status & DSC_OWNER_MAC)
613 break; /* Not complete */
614 skb_ptr = descptr->skb_ptr;
615 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
616 skb_ptr->len, PCI_DMA_TODEVICE);
617 /* Free buffer */
618 dev_kfree_skb_irq(skb_ptr);
619 descptr->skb_ptr = NULL;
620 /* To next descriptor */
621 descptr = descptr->vndescp;
622 priv->tx_free_desc++;
623 }
624 priv->tx_remove_ptr = descptr;
625
626 if (priv->tx_free_desc)
627 netif_wake_queue(dev);
628 spin_unlock(&priv->lock);
629}
630
631static int r6040_poll(struct napi_struct *napi, int budget)
632{
633 struct r6040_private *priv =
634 container_of(napi, struct r6040_private, napi);
635 struct net_device *dev = priv->dev;
636 void __iomem *ioaddr = priv->base;
637 int work_done;
638
639 work_done = r6040_rx(dev, budget);
640
641 if (work_done < budget) {
642 napi_complete(napi);
643 /* Enable RX interrupt */
644 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
645 }
646 return work_done;
647}
648
649/* The RDC interrupt handler. */
650static irqreturn_t r6040_interrupt(int irq, void *dev_id)
651{
652 struct net_device *dev = dev_id;
653 struct r6040_private *lp = netdev_priv(dev);
654 void __iomem *ioaddr = lp->base;
655 u16 misr, status;
656
657 /* Save MIER */
658 misr = ioread16(ioaddr + MIER);
659 /* Mask off RDC MAC interrupt */
660 iowrite16(MSK_INT, ioaddr + MIER);
661 /* Read MISR status and clear */
662 status = ioread16(ioaddr + MISR);
663
664 if (status == 0x0000 || status == 0xffff) {
665 /* Restore RDC MAC interrupt */
666 iowrite16(misr, ioaddr + MIER);
667 return IRQ_NONE;
668 }
669
670 /* RX interrupt request */
671 if (status & RX_INTS) {
672 if (status & RX_NO_DESC) {
673 /* RX descriptor unavailable */
674 dev->stats.rx_dropped++;
675 dev->stats.rx_missed_errors++;
676 }
677 if (status & RX_FIFO_FULL)
678 dev->stats.rx_fifo_errors++;
679
680 if (likely(napi_schedule_prep(&lp->napi))) {
681 /* Mask off RX interrupt */
682 misr &= ~RX_INTS;
683 __napi_schedule(&lp->napi);
684 }
685 }
686
687 /* TX interrupt request */
688 if (status & TX_INTS)
689 r6040_tx(dev);
690
691 /* Restore RDC MAC interrupt */
692 iowrite16(misr, ioaddr + MIER);
693
694 return IRQ_HANDLED;
695}
696
697#ifdef CONFIG_NET_POLL_CONTROLLER
698static void r6040_poll_controller(struct net_device *dev)
699{
700 disable_irq(dev->irq);
701 r6040_interrupt(dev->irq, dev);
702 enable_irq(dev->irq);
703}
704#endif
705
706/* Init RDC MAC */
707static int r6040_up(struct net_device *dev)
708{
709 struct r6040_private *lp = netdev_priv(dev);
710 void __iomem *ioaddr = lp->base;
711 int ret;
712
713 /* Initialise and alloc RX/TX buffers */
714 r6040_init_txbufs(dev);
715 ret = r6040_alloc_rxbufs(dev);
716 if (ret)
717 return ret;
718
719 /* improve performance (by RDC guys) */
720 r6040_phy_write(ioaddr, 30, 17,
721 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
722 r6040_phy_write(ioaddr, 30, 17,
723 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
724 r6040_phy_write(ioaddr, 0, 19, 0x0000);
725 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
726
727 /* Initialize all MAC registers */
728 r6040_init_mac_regs(dev);
729
730 return 0;
731}
732
733
734/* Read/set MAC address routines */
735static void r6040_mac_address(struct net_device *dev)
736{
737 struct r6040_private *lp = netdev_priv(dev);
738 void __iomem *ioaddr = lp->base;
739 u16 *adrp;
740
741 /* MAC operation register */
742 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
743 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
744 iowrite16(0, ioaddr + MAC_SM);
745 mdelay(5);
746
747 /* Restore MAC Address */
748 adrp = (u16 *) dev->dev_addr;
749 iowrite16(adrp[0], ioaddr + MID_0L);
750 iowrite16(adrp[1], ioaddr + MID_0M);
751 iowrite16(adrp[2], ioaddr + MID_0H);
752
753 /* Store MAC Address in perm_addr */
754 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
755}
756
757static int r6040_open(struct net_device *dev)
758{
759 struct r6040_private *lp = netdev_priv(dev);
760 int ret;
761
762 /* Request IRQ and Register interrupt handler */
763 ret = request_irq(dev->irq, r6040_interrupt,
764 IRQF_SHARED, dev->name, dev);
765 if (ret)
766 goto out;
767
768 /* Set MAC address */
769 r6040_mac_address(dev);
770
771 /* Allocate Descriptor memory */
772 lp->rx_ring =
773 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
774 if (!lp->rx_ring) {
775 ret = -ENOMEM;
776 goto err_free_irq;
777 }
778
779 lp->tx_ring =
780 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
781 if (!lp->tx_ring) {
782 ret = -ENOMEM;
783 goto err_free_rx_ring;
784 }
785
786 ret = r6040_up(dev);
787 if (ret)
788 goto err_free_tx_ring;
789
790 napi_enable(&lp->napi);
791 netif_start_queue(dev);
792
793 return 0;
794
795err_free_tx_ring:
796 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
797 lp->tx_ring_dma);
798err_free_rx_ring:
799 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
800 lp->rx_ring_dma);
801err_free_irq:
802 free_irq(dev->irq, dev);
803out:
804 return ret;
805}
806
807static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
808 struct net_device *dev)
809{
810 struct r6040_private *lp = netdev_priv(dev);
811 struct r6040_descriptor *descptr;
812 void __iomem *ioaddr = lp->base;
813 unsigned long flags;
814
815 /* Critical Section */
816 spin_lock_irqsave(&lp->lock, flags);
817
818 /* TX resource check */
819 if (!lp->tx_free_desc) {
820 spin_unlock_irqrestore(&lp->lock, flags);
821 netif_stop_queue(dev);
822 netdev_err(dev, ": no tx descriptor\n");
823 return NETDEV_TX_BUSY;
824 }
825
826 /* Statistic Counter */
827 dev->stats.tx_packets++;
828 dev->stats.tx_bytes += skb->len;
829 /* Set TX descriptor & Transmit it */
830 lp->tx_free_desc--;
831 descptr = lp->tx_insert_ptr;
832 if (skb->len < MISR)
833 descptr->len = MISR;
834 else
835 descptr->len = skb->len;
836
837 descptr->skb_ptr = skb;
838 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
839 skb->data, skb->len, PCI_DMA_TODEVICE));
840 descptr->status = DSC_OWNER_MAC;
841
842 skb_tx_timestamp(skb);
843
844 /* Trigger the MAC to check the TX descriptor */
845 iowrite16(0x01, ioaddr + MTPR);
846 lp->tx_insert_ptr = descptr->vndescp;
847
848 /* If no tx resource, stop */
849 if (!lp->tx_free_desc)
850 netif_stop_queue(dev);
851
852 spin_unlock_irqrestore(&lp->lock, flags);
853
854 return NETDEV_TX_OK;
855}
856
857static void r6040_multicast_list(struct net_device *dev)
858{
859 struct r6040_private *lp = netdev_priv(dev);
860 void __iomem *ioaddr = lp->base;
861 unsigned long flags;
862 struct netdev_hw_addr *ha;
863 int i;
864 u16 *adrp;
865 u16 hash_table[4] = { 0 };
866
867 spin_lock_irqsave(&lp->lock, flags);
868
869 /* Keep our MAC Address */
870 adrp = (u16 *)dev->dev_addr;
871 iowrite16(adrp[0], ioaddr + MID_0L);
872 iowrite16(adrp[1], ioaddr + MID_0M);
873 iowrite16(adrp[2], ioaddr + MID_0H);
874
875 /* Clear AMCP & PROM bits */
876 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
877
878 /* Promiscuous mode */
879 if (dev->flags & IFF_PROMISC)
880 lp->mcr0 |= MCR0_PROMISC;
881
882 /* Enable multicast hash table function to
883 * receive all multicast packets. */
884 else if (dev->flags & IFF_ALLMULTI) {
885 lp->mcr0 |= MCR0_HASH_EN;
886
887 for (i = 0; i < MCAST_MAX ; i++) {
888 iowrite16(0, ioaddr + MID_1L + 8 * i);
889 iowrite16(0, ioaddr + MID_1M + 8 * i);
890 iowrite16(0, ioaddr + MID_1H + 8 * i);
891 }
892
893 for (i = 0; i < 4; i++)
894 hash_table[i] = 0xffff;
895 }
896 /* Use internal multicast address registers if the number of
897 * multicast addresses is not greater than MCAST_MAX. */
898 else if (netdev_mc_count(dev) <= MCAST_MAX) {
899 i = 0;
900 netdev_for_each_mc_addr(ha, dev) {
901 u16 *adrp = (u16 *) ha->addr;
902 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
903 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
904 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
905 i++;
906 }
907 while (i < MCAST_MAX) {
908 iowrite16(0, ioaddr + MID_1L + 8 * i);
909 iowrite16(0, ioaddr + MID_1M + 8 * i);
910 iowrite16(0, ioaddr + MID_1H + 8 * i);
911 i++;
912 }
913 }
914 /* Otherwise, Enable multicast hash table function. */
915 else {
916 u32 crc;
917
918 lp->mcr0 |= MCR0_HASH_EN;
919
920 for (i = 0; i < MCAST_MAX ; i++) {
921 iowrite16(0, ioaddr + MID_1L + 8 * i);
922 iowrite16(0, ioaddr + MID_1M + 8 * i);
923 iowrite16(0, ioaddr + MID_1H + 8 * i);
924 }
925
926 /* Build multicast hash table */
927 netdev_for_each_mc_addr(ha, dev) {
928 u8 *addrs = ha->addr;
929
930 crc = ether_crc(ETH_ALEN, addrs);
931 crc >>= 26;
932 hash_table[crc >> 4] |= 1 << (crc & 0xf);
933 }
934 }
935
936 iowrite16(lp->mcr0, ioaddr + MCR0);
937
938 /* Fill the MAC hash tables with their values */
939 if (lp->mcr0 && MCR0_HASH_EN) {
940 iowrite16(hash_table[0], ioaddr + MAR0);
941 iowrite16(hash_table[1], ioaddr + MAR1);
942 iowrite16(hash_table[2], ioaddr + MAR2);
943 iowrite16(hash_table[3], ioaddr + MAR3);
944 }
945
946 spin_unlock_irqrestore(&lp->lock, flags);
947}
948
949static void netdev_get_drvinfo(struct net_device *dev,
950 struct ethtool_drvinfo *info)
951{
952 struct r6040_private *rp = netdev_priv(dev);
953
954 strcpy(info->driver, DRV_NAME);
955 strcpy(info->version, DRV_VERSION);
956 strcpy(info->bus_info, pci_name(rp->pdev));
957}
958
959static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
960{
961 struct r6040_private *rp = netdev_priv(dev);
962
963 return phy_ethtool_gset(rp->phydev, cmd);
964}
965
966static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
967{
968 struct r6040_private *rp = netdev_priv(dev);
969
970 return phy_ethtool_sset(rp->phydev, cmd);
971}
972
973static const struct ethtool_ops netdev_ethtool_ops = {
974 .get_drvinfo = netdev_get_drvinfo,
975 .get_settings = netdev_get_settings,
976 .set_settings = netdev_set_settings,
977 .get_link = ethtool_op_get_link,
978};
979
980static const struct net_device_ops r6040_netdev_ops = {
981 .ndo_open = r6040_open,
982 .ndo_stop = r6040_close,
983 .ndo_start_xmit = r6040_start_xmit,
984 .ndo_get_stats = r6040_get_stats,
985 .ndo_set_multicast_list = r6040_multicast_list,
986 .ndo_change_mtu = eth_change_mtu,
987 .ndo_validate_addr = eth_validate_addr,
988 .ndo_set_mac_address = eth_mac_addr,
989 .ndo_do_ioctl = r6040_ioctl,
990 .ndo_tx_timeout = r6040_tx_timeout,
991#ifdef CONFIG_NET_POLL_CONTROLLER
992 .ndo_poll_controller = r6040_poll_controller,
993#endif
994};
995
996static void r6040_adjust_link(struct net_device *dev)
997{
998 struct r6040_private *lp = netdev_priv(dev);
999 struct phy_device *phydev = lp->phydev;
1000 int status_changed = 0;
1001 void __iomem *ioaddr = lp->base;
1002
1003 BUG_ON(!phydev);
1004
1005 if (lp->old_link != phydev->link) {
1006 status_changed = 1;
1007 lp->old_link = phydev->link;
1008 }
1009
1010 /* reflect duplex change */
1011 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1012 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0);
1013 iowrite16(lp->mcr0, ioaddr);
1014
1015 status_changed = 1;
1016 lp->old_duplex = phydev->duplex;
1017 }
1018
1019 if (status_changed) {
1020 pr_info("%s: link %s", dev->name, phydev->link ?
1021 "UP" : "DOWN");
1022 if (phydev->link)
1023 pr_cont(" - %d/%s", phydev->speed,
1024 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1025 pr_cont("\n");
1026 }
1027}
1028
1029static int r6040_mii_probe(struct net_device *dev)
1030{
1031 struct r6040_private *lp = netdev_priv(dev);
1032 struct phy_device *phydev = NULL;
1033
1034 phydev = phy_find_first(lp->mii_bus);
1035 if (!phydev) {
1036 dev_err(&lp->pdev->dev, "no PHY found\n");
1037 return -ENODEV;
1038 }
1039
1040 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1041 0, PHY_INTERFACE_MODE_MII);
1042
1043 if (IS_ERR(phydev)) {
1044 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1045 return PTR_ERR(phydev);
1046 }
1047
1048 /* mask with MAC supported features */
1049 phydev->supported &= (SUPPORTED_10baseT_Half
1050 | SUPPORTED_10baseT_Full
1051 | SUPPORTED_100baseT_Half
1052 | SUPPORTED_100baseT_Full
1053 | SUPPORTED_Autoneg
1054 | SUPPORTED_MII
1055 | SUPPORTED_TP);
1056
1057 phydev->advertising = phydev->supported;
1058 lp->phydev = phydev;
1059 lp->old_link = 0;
1060 lp->old_duplex = -1;
1061
1062 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1063 "(mii_bus:phy_addr=%s)\n",
1064 phydev->drv->name, dev_name(&phydev->dev));
1065
1066 return 0;
1067}
1068
1069static int __devinit r6040_init_one(struct pci_dev *pdev,
1070 const struct pci_device_id *ent)
1071{
1072 struct net_device *dev;
1073 struct r6040_private *lp;
1074 void __iomem *ioaddr;
1075 int err, io_size = R6040_IO_SIZE;
1076 static int card_idx = -1;
1077 int bar = 0;
1078 u16 *adrp;
1079 int i;
1080
1081 pr_info("%s\n", version);
1082
1083 err = pci_enable_device(pdev);
1084 if (err)
1085 goto err_out;
1086
1087 /* this should always be supported */
1088 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1089 if (err) {
1090 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1091 "not supported by the card\n");
1092 goto err_out;
1093 }
1094 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1095 if (err) {
1096 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1097 "not supported by the card\n");
1098 goto err_out;
1099 }
1100
1101 /* IO Size check */
1102 if (pci_resource_len(pdev, bar) < io_size) {
1103 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1104 err = -EIO;
1105 goto err_out;
1106 }
1107
1108 pci_set_master(pdev);
1109
1110 dev = alloc_etherdev(sizeof(struct r6040_private));
1111 if (!dev) {
1112 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1113 err = -ENOMEM;
1114 goto err_out;
1115 }
1116 SET_NETDEV_DEV(dev, &pdev->dev);
1117 lp = netdev_priv(dev);
1118
1119 err = pci_request_regions(pdev, DRV_NAME);
1120
1121 if (err) {
1122 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1123 goto err_out_free_dev;
1124 }
1125
1126 ioaddr = pci_iomap(pdev, bar, io_size);
1127 if (!ioaddr) {
1128 dev_err(&pdev->dev, "ioremap failed for device\n");
1129 err = -EIO;
1130 goto err_out_free_res;
1131 }
1132 /* If PHY status change register is still set to zero it means the
1133 * bootloader didn't initialize it */
1134 if (ioread16(ioaddr + PHY_CC) == 0)
1135 iowrite16(0x9f07, ioaddr + PHY_CC);
1136
1137 /* Init system & device */
1138 lp->base = ioaddr;
1139 dev->irq = pdev->irq;
1140
1141 spin_lock_init(&lp->lock);
1142 pci_set_drvdata(pdev, dev);
1143
1144 /* Set MAC address */
1145 card_idx++;
1146
1147 adrp = (u16 *)dev->dev_addr;
1148 adrp[0] = ioread16(ioaddr + MID_0L);
1149 adrp[1] = ioread16(ioaddr + MID_0M);
1150 adrp[2] = ioread16(ioaddr + MID_0H);
1151
1152 /* Some bootloader/BIOSes do not initialize
1153 * MAC address, warn about that */
1154 if (!(adrp[0] || adrp[1] || adrp[2])) {
1155 netdev_warn(dev, "MAC address not initialized, "
1156 "generating random\n");
1157 random_ether_addr(dev->dev_addr);
1158 }
1159
1160 /* Link new device into r6040_root_dev */
1161 lp->pdev = pdev;
1162 lp->dev = dev;
1163
1164 /* Init RDC private data */
1165 lp->mcr0 = 0x1002;
1166 lp->phy_addr = phy_table[card_idx];
1167
1168 /* The RDC-specific entries in the device structure. */
1169 dev->netdev_ops = &r6040_netdev_ops;
1170 dev->ethtool_ops = &netdev_ethtool_ops;
1171 dev->watchdog_timeo = TX_TIMEOUT;
1172
1173 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1174
1175 lp->mii_bus = mdiobus_alloc();
1176 if (!lp->mii_bus) {
1177 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1178 err = -ENOMEM;
1179 goto err_out_unmap;
1180 }
1181
1182 lp->mii_bus->priv = dev;
1183 lp->mii_bus->read = r6040_mdiobus_read;
1184 lp->mii_bus->write = r6040_mdiobus_write;
1185 lp->mii_bus->reset = r6040_mdiobus_reset;
1186 lp->mii_bus->name = "r6040_eth_mii";
1187 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", card_idx);
1188 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1189 if (!lp->mii_bus->irq) {
1190 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1191 err = -ENOMEM;
1192 goto err_out_mdio;
1193 }
1194
1195 for (i = 0; i < PHY_MAX_ADDR; i++)
1196 lp->mii_bus->irq[i] = PHY_POLL;
1197
1198 err = mdiobus_register(lp->mii_bus);
1199 if (err) {
1200 dev_err(&pdev->dev, "failed to register MII bus\n");
1201 goto err_out_mdio_irq;
1202 }
1203
1204 err = r6040_mii_probe(dev);
1205 if (err) {
1206 dev_err(&pdev->dev, "failed to probe MII bus\n");
1207 goto err_out_mdio_unregister;
1208 }
1209
1210 /* Register net device. After this dev->name assign */
1211 err = register_netdev(dev);
1212 if (err) {
1213 dev_err(&pdev->dev, "Failed to register net device\n");
1214 goto err_out_mdio_unregister;
1215 }
1216 return 0;
1217
1218err_out_mdio_unregister:
1219 mdiobus_unregister(lp->mii_bus);
1220err_out_mdio_irq:
1221 kfree(lp->mii_bus->irq);
1222err_out_mdio:
1223 mdiobus_free(lp->mii_bus);
1224err_out_unmap:
1225 pci_iounmap(pdev, ioaddr);
1226err_out_free_res:
1227 pci_release_regions(pdev);
1228err_out_free_dev:
1229 free_netdev(dev);
1230err_out:
1231 return err;
1232}
1233
1234static void __devexit r6040_remove_one(struct pci_dev *pdev)
1235{
1236 struct net_device *dev = pci_get_drvdata(pdev);
1237 struct r6040_private *lp = netdev_priv(dev);
1238
1239 unregister_netdev(dev);
1240 mdiobus_unregister(lp->mii_bus);
1241 kfree(lp->mii_bus->irq);
1242 mdiobus_free(lp->mii_bus);
1243 pci_release_regions(pdev);
1244 free_netdev(dev);
1245 pci_disable_device(pdev);
1246 pci_set_drvdata(pdev, NULL);
1247}
1248
1249
1250static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1251 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1252 { 0 }
1253};
1254MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1255
1256static struct pci_driver r6040_driver = {
1257 .name = DRV_NAME,
1258 .id_table = r6040_pci_tbl,
1259 .probe = r6040_init_one,
1260 .remove = __devexit_p(r6040_remove_one),
1261};
1262
1263
1264static int __init r6040_init(void)
1265{
1266 return pci_register_driver(&r6040_driver);
1267}
1268
1269
1270static void __exit r6040_cleanup(void)
1271{
1272 pci_unregister_driver(&r6040_driver);
1273}
1274
1275module_init(r6040_init);
1276module_exit(r6040_cleanup);