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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25#include <linux/bitfield.h>
26#include <linux/ctype.h>
27#include <linux/delay.h>
28#include <linux/hwmon.h>
29#include <linux/marvell_phy.h>
30#include <linux/phy.h>
31#include <linux/sfp.h>
32#include <linux/netdevice.h>
33
34#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
35#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
36
37#define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
38
39enum {
40 MV_PMA_FW_VER0 = 0xc011,
41 MV_PMA_FW_VER1 = 0xc012,
42 MV_PMA_21X0_PORT_CTRL = 0xc04a,
43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
51 MV_PMA_BOOT = 0xc050,
52 MV_PMA_BOOT_FATAL = BIT(0),
53
54 MV_PCS_BASE_T = 0x0000,
55 MV_PCS_BASE_R = 0x1000,
56 MV_PCS_1000BASEX = 0x2000,
57
58 MV_PCS_CSCR1 = 0x8000,
59 MV_PCS_CSCR1_ED_MASK = 0x0300,
60 MV_PCS_CSCR1_ED_OFF = 0x0000,
61 MV_PCS_CSCR1_ED_RX = 0x0200,
62 MV_PCS_CSCR1_ED_NLP = 0x0300,
63 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
64 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
67
68 MV_PCS_DSC1 = 0x8003,
69 MV_PCS_DSC1_ENABLE = BIT(9),
70 MV_PCS_DSC1_10GBT = 0x01c0,
71 MV_PCS_DSC1_1GBR = 0x0038,
72 MV_PCS_DSC1_100BTX = 0x0007,
73 MV_PCS_DSC2 = 0x8004,
74 MV_PCS_DSC2_2P5G = 0xf000,
75 MV_PCS_DSC2_5G = 0x0f00,
76
77 MV_PCS_CSSR1 = 0x8008,
78 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
80 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
81 MV_PCS_CSSR1_SPD1_100 = 0x4000,
82 MV_PCS_CSSR1_SPD1_10 = 0x0000,
83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
84 MV_PCS_CSSR1_RESOLVED = BIT(11),
85 MV_PCS_CSSR1_MDIX = BIT(6),
86 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
87 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
88 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
89 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
90
91 /* Temperature read register (88E2110 only) */
92 MV_PCS_TEMP = 0x8042,
93
94 /* Number of ports on the device */
95 MV_PCS_PORT_INFO = 0xd00d,
96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
98
99 /* SerDes reinitialization 88E21X0 */
100 MV_AN_21X0_SERDES_CTRL2 = 0x800f,
101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
103
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
105 * registers appear to set themselves to the 0x800X when AN is
106 * restarted, but status registers appear readable from either.
107 */
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
110
111 /* Vendor2 MMD registers */
112 MV_V2_PORT_CTRL = 0xf001,
113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
125 MV_V2_PORT_INTR_STS = 0xf040,
126 MV_V2_PORT_INTR_MASK = 0xf043,
127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
131 /* Wake on LAN registers */
132 MV_V2_WOL_CTRL = 0xf06e,
133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
135 /* Temperature control/read registers (88X3310 only) */
136 MV_V2_TEMP_CTRL = 0xf08a,
137 MV_V2_TEMP_CTRL_MASK = 0xc000,
138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
139 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
140 MV_V2_TEMP = 0xf08c,
141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
142};
143
144struct mv3310_mactype {
145 bool valid;
146 bool fixed_interface;
147 phy_interface_t interface_10g;
148};
149
150struct mv3310_chip {
151 bool (*has_downshift)(struct phy_device *phydev);
152 void (*init_supported_interfaces)(unsigned long *mask);
153 int (*get_mactype)(struct phy_device *phydev);
154 int (*set_mactype)(struct phy_device *phydev, int mactype);
155 int (*select_mactype)(unsigned long *interfaces);
156
157 const struct mv3310_mactype *mactypes;
158 size_t n_mactypes;
159
160#ifdef CONFIG_HWMON
161 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
162#endif
163};
164
165struct mv3310_priv {
166 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
167 const struct mv3310_mactype *mactype;
168
169 u32 firmware_ver;
170 bool has_downshift;
171
172 struct device *hwmon_dev;
173 char *hwmon_name;
174};
175
176static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
177{
178 return phydev->drv->driver_data;
179}
180
181#ifdef CONFIG_HWMON
182static umode_t mv3310_hwmon_is_visible(const void *data,
183 enum hwmon_sensor_types type,
184 u32 attr, int channel)
185{
186 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
187 return 0444;
188 if (type == hwmon_temp && attr == hwmon_temp_input)
189 return 0444;
190 return 0;
191}
192
193static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
194{
195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
196}
197
198static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
199{
200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
201}
202
203static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
204 u32 attr, int channel, long *value)
205{
206 struct phy_device *phydev = dev_get_drvdata(dev);
207 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
208 int temp;
209
210 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
211 *value = MSEC_PER_SEC;
212 return 0;
213 }
214
215 if (type == hwmon_temp && attr == hwmon_temp_input) {
216 temp = chip->hwmon_read_temp_reg(phydev);
217 if (temp < 0)
218 return temp;
219
220 *value = ((temp & 0xff) - 75) * 1000;
221
222 return 0;
223 }
224
225 return -EOPNOTSUPP;
226}
227
228static const struct hwmon_ops mv3310_hwmon_ops = {
229 .is_visible = mv3310_hwmon_is_visible,
230 .read = mv3310_hwmon_read,
231};
232
233static u32 mv3310_hwmon_chip_config[] = {
234 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
235 0,
236};
237
238static const struct hwmon_channel_info mv3310_hwmon_chip = {
239 .type = hwmon_chip,
240 .config = mv3310_hwmon_chip_config,
241};
242
243static u32 mv3310_hwmon_temp_config[] = {
244 HWMON_T_INPUT,
245 0,
246};
247
248static const struct hwmon_channel_info mv3310_hwmon_temp = {
249 .type = hwmon_temp,
250 .config = mv3310_hwmon_temp_config,
251};
252
253static const struct hwmon_channel_info * const mv3310_hwmon_info[] = {
254 &mv3310_hwmon_chip,
255 &mv3310_hwmon_temp,
256 NULL,
257};
258
259static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
260 .ops = &mv3310_hwmon_ops,
261 .info = mv3310_hwmon_info,
262};
263
264static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
265{
266 u16 val;
267 int ret;
268
269 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
270 return 0;
271
272 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
273 MV_V2_TEMP_UNKNOWN);
274 if (ret < 0)
275 return ret;
276
277 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
278
279 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
280 MV_V2_TEMP_CTRL_MASK, val);
281}
282
283static int mv3310_hwmon_probe(struct phy_device *phydev)
284{
285 struct device *dev = &phydev->mdio.dev;
286 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
287 int i, j, ret;
288
289 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
290 if (!priv->hwmon_name)
291 return -ENODEV;
292
293 for (i = j = 0; priv->hwmon_name[i]; i++) {
294 if (isalnum(priv->hwmon_name[i])) {
295 if (i != j)
296 priv->hwmon_name[j] = priv->hwmon_name[i];
297 j++;
298 }
299 }
300 priv->hwmon_name[j] = '\0';
301
302 ret = mv3310_hwmon_config(phydev, true);
303 if (ret)
304 return ret;
305
306 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
307 priv->hwmon_name, phydev,
308 &mv3310_hwmon_chip_info, NULL);
309
310 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
311}
312#else
313static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
314{
315 return 0;
316}
317
318static int mv3310_hwmon_probe(struct phy_device *phydev)
319{
320 return 0;
321}
322#endif
323
324static int mv3310_power_down(struct phy_device *phydev)
325{
326 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
327 MV_V2_PORT_CTRL_PWRDOWN);
328}
329
330static int mv3310_power_up(struct phy_device *phydev)
331{
332 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
333 int ret;
334
335 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
336 MV_V2_PORT_CTRL_PWRDOWN);
337
338 /* Sometimes, the power down bit doesn't clear immediately, and
339 * a read of this register causes the bit not to clear. Delay
340 * 100us to allow the PHY to come out of power down mode before
341 * the next access.
342 */
343 udelay(100);
344
345 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
346 priv->firmware_ver < 0x00030000)
347 return ret;
348
349 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
350 MV_V2_33X0_PORT_CTRL_SWRST);
351}
352
353static int mv3310_reset(struct phy_device *phydev, u32 unit)
354{
355 int val, err;
356
357 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
358 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
359 if (err < 0)
360 return err;
361
362 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
363 unit + MDIO_CTRL1, val,
364 !(val & MDIO_CTRL1_RESET),
365 5000, 100000, true);
366}
367
368static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
369{
370 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
371 int val;
372
373 if (!priv->has_downshift)
374 return -EOPNOTSUPP;
375
376 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
377 if (val < 0)
378 return val;
379
380 if (val & MV_PCS_DSC1_ENABLE)
381 /* assume that all fields are the same */
382 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
383 else
384 *ds = DOWNSHIFT_DEV_DISABLE;
385
386 return 0;
387}
388
389static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
390{
391 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
392 u16 val;
393 int err;
394
395 if (!priv->has_downshift)
396 return -EOPNOTSUPP;
397
398 if (ds == DOWNSHIFT_DEV_DISABLE)
399 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
400 MV_PCS_DSC1_ENABLE);
401
402 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
403 * set the default settings for the PHY. However, it is used for
404 * "ethtool --set-phy-tunable ethN downshift on". The intention is
405 * to enable downshift at a default number of retries. The default
406 * settings for 88x3310 are for two retries with downshift disabled.
407 * So let's use two retries with downshift enabled.
408 */
409 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
410 ds = 2;
411
412 if (ds > 8)
413 return -E2BIG;
414
415 ds -= 1;
416 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
417 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
418 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
419 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
420 if (err < 0)
421 return err;
422
423 val = MV_PCS_DSC1_ENABLE;
424 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
425 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
426 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
427
428 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
429 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
430 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
431}
432
433static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
434{
435 int val;
436
437 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
438 if (val < 0)
439 return val;
440
441 switch (val & MV_PCS_CSCR1_ED_MASK) {
442 case MV_PCS_CSCR1_ED_NLP:
443 *edpd = 1000;
444 break;
445 case MV_PCS_CSCR1_ED_RX:
446 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
447 break;
448 default:
449 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
450 break;
451 }
452 return 0;
453}
454
455static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
456{
457 u16 val;
458 int err;
459
460 switch (edpd) {
461 case 1000:
462 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
463 val = MV_PCS_CSCR1_ED_NLP;
464 break;
465
466 case ETHTOOL_PHY_EDPD_NO_TX:
467 val = MV_PCS_CSCR1_ED_RX;
468 break;
469
470 case ETHTOOL_PHY_EDPD_DISABLE:
471 val = MV_PCS_CSCR1_ED_OFF;
472 break;
473
474 default:
475 return -EINVAL;
476 }
477
478 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
479 MV_PCS_CSCR1_ED_MASK, val);
480 if (err > 0)
481 err = mv3310_reset(phydev, MV_PCS_BASE_T);
482
483 return err;
484}
485
486static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
487{
488 struct phy_device *phydev = upstream;
489 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
490 DECLARE_PHY_INTERFACE_MASK(interfaces);
491 phy_interface_t iface;
492
493 sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
494 iface = sfp_select_interface(phydev->sfp_bus, support);
495
496 if (iface != PHY_INTERFACE_MODE_10GBASER) {
497 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
498 return -EINVAL;
499 }
500 return 0;
501}
502
503static const struct sfp_upstream_ops mv3310_sfp_ops = {
504 .attach = phy_sfp_attach,
505 .detach = phy_sfp_detach,
506 .module_insert = mv3310_sfp_insert,
507};
508
509static int mv3310_probe(struct phy_device *phydev)
510{
511 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
512 struct mv3310_priv *priv;
513 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
514 int ret;
515
516 if (!phydev->is_c45 ||
517 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
518 return -ENODEV;
519
520 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
521 if (ret < 0)
522 return ret;
523
524 if (ret & MV_PMA_BOOT_FATAL) {
525 dev_warn(&phydev->mdio.dev,
526 "PHY failed to boot firmware, status=%04x\n", ret);
527 return -ENODEV;
528 }
529
530 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
531 if (!priv)
532 return -ENOMEM;
533
534 dev_set_drvdata(&phydev->mdio.dev, priv);
535
536 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
537 if (ret < 0)
538 return ret;
539
540 priv->firmware_ver = ret << 16;
541
542 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
543 if (ret < 0)
544 return ret;
545
546 priv->firmware_ver |= ret;
547
548 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
549 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
550 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
551
552 if (chip->has_downshift)
553 priv->has_downshift = chip->has_downshift(phydev);
554
555 /* Powering down the port when not in use saves about 600mW */
556 ret = mv3310_power_down(phydev);
557 if (ret)
558 return ret;
559
560 ret = mv3310_hwmon_probe(phydev);
561 if (ret)
562 return ret;
563
564 chip->init_supported_interfaces(priv->supported_interfaces);
565
566 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
567}
568
569static void mv3310_remove(struct phy_device *phydev)
570{
571 mv3310_hwmon_config(phydev, false);
572}
573
574static int mv3310_suspend(struct phy_device *phydev)
575{
576 return mv3310_power_down(phydev);
577}
578
579static int mv3310_resume(struct phy_device *phydev)
580{
581 int ret;
582
583 ret = mv3310_power_up(phydev);
584 if (ret)
585 return ret;
586
587 return mv3310_hwmon_config(phydev, true);
588}
589
590/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
591 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
592 * support 2.5GBASET and 5GBASET. For these models, we can still read their
593 * 2.5G/5G extended abilities register (1.21). We detect these models based on
594 * the PMA device identifier, with a mask matching models known to have this
595 * issue
596 */
597static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
598{
599 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
600 return false;
601
602 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
603 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
604 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
605}
606
607static int mv2110_get_mactype(struct phy_device *phydev)
608{
609 int mactype;
610
611 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
612 if (mactype < 0)
613 return mactype;
614
615 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
616}
617
618static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
619{
620 int err, val;
621
622 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
623 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
624 MV_PMA_21X0_PORT_CTRL_SWRST |
625 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
626 MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
627 if (err)
628 return err;
629
630 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
631 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
632 MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
633 if (err)
634 return err;
635
636 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
637 MV_AN_21X0_SERDES_CTRL2, val,
638 !(val &
639 MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
640 5000, 100000, true);
641 if (err)
642 return err;
643
644 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
645 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
646}
647
648static int mv2110_select_mactype(unsigned long *interfaces)
649{
650 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
651 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
652 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
653 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
654 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
655 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
656 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
657 else
658 return -1;
659}
660
661static int mv3310_get_mactype(struct phy_device *phydev)
662{
663 int mactype;
664
665 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
666 if (mactype < 0)
667 return mactype;
668
669 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
670}
671
672static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
673{
674 int ret;
675
676 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
677 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
678 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
679 mactype);
680 if (ret <= 0)
681 return ret;
682
683 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
684 MV_V2_33X0_PORT_CTRL_SWRST);
685}
686
687static int mv3310_select_mactype(unsigned long *interfaces)
688{
689 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
690 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
691 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
692 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
693 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
694 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
695 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
696 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
697 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
698 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
699 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
700 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
701 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
702 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
703 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
704 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
705 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
706 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces))
707 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
708 else
709 return -1;
710}
711
712static const struct mv3310_mactype mv2110_mactypes[] = {
713 [MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII] = {
714 .valid = true,
715 .fixed_interface = true,
716 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
717 },
718 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER] = {
719 .valid = true,
720 .interface_10g = PHY_INTERFACE_MODE_NA,
721 },
722 [MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN] = {
723 .valid = true,
724 .interface_10g = PHY_INTERFACE_MODE_NA,
725 },
726 [MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
727 .valid = true,
728 .fixed_interface = true,
729 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
730 },
731};
732
733static const struct mv3310_mactype mv3310_mactypes[] = {
734 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {
735 .valid = true,
736 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
737 },
738 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH] = {
739 .valid = true,
740 .fixed_interface = true,
741 .interface_10g = PHY_INTERFACE_MODE_XAUI,
742 },
743 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {
744 .valid = true,
745 .fixed_interface = true,
746 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
747 },
748 [MV_V2_3310_PORT_CTRL_MACTYPE_XAUI] = {
749 .valid = true,
750 .interface_10g = PHY_INTERFACE_MODE_XAUI,
751 },
752 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {
753 .valid = true,
754 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
755 },
756 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {
757 .valid = true,
758 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
759 },
760 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
761 .valid = true,
762 .fixed_interface = true,
763 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
764 },
765 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {
766 .valid = true,
767 .fixed_interface = true,
768 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
769 },
770};
771
772static const struct mv3310_mactype mv3340_mactypes[] = {
773 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {
774 .valid = true,
775 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
776 },
777 [MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN] = {
778 .valid = true,
779 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
780 },
781 [MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {
782 .valid = true,
783 .fixed_interface = true,
784 .interface_10g = PHY_INTERFACE_MODE_RXAUI,
785 },
786 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {
787 .valid = true,
788 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
789 },
790 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {
791 .valid = true,
792 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
793 },
794 [MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {
795 .valid = true,
796 .fixed_interface = true,
797 .interface_10g = PHY_INTERFACE_MODE_10GBASER,
798 },
799 [MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {
800 .valid = true,
801 .fixed_interface = true,
802 .interface_10g = PHY_INTERFACE_MODE_USXGMII,
803 },
804};
805
806static void mv3310_fill_possible_interfaces(struct phy_device *phydev)
807{
808 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
809 unsigned long *possible = phydev->possible_interfaces;
810 const struct mv3310_mactype *mactype = priv->mactype;
811
812 if (mactype->interface_10g != PHY_INTERFACE_MODE_NA)
813 __set_bit(priv->mactype->interface_10g, possible);
814
815 if (!mactype->fixed_interface) {
816 __set_bit(PHY_INTERFACE_MODE_5GBASER, possible);
817 __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
818 __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
819 }
820}
821
822static int mv3310_config_init(struct phy_device *phydev)
823{
824 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
825 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
826 int err, mactype;
827
828 /* Check that the PHY interface type is compatible */
829 if (!test_bit(phydev->interface, priv->supported_interfaces))
830 return -ENODEV;
831
832 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
833
834 /* Power up so reset works */
835 err = mv3310_power_up(phydev);
836 if (err)
837 return err;
838
839 /* If host provided host supported interface modes, try to select the
840 * best one
841 */
842 if (!phy_interface_empty(phydev->host_interfaces)) {
843 mactype = chip->select_mactype(phydev->host_interfaces);
844 if (mactype >= 0) {
845 phydev_info(phydev, "Changing MACTYPE to %i\n",
846 mactype);
847 err = chip->set_mactype(phydev, mactype);
848 if (err)
849 return err;
850 }
851 }
852
853 mactype = chip->get_mactype(phydev);
854 if (mactype < 0)
855 return mactype;
856
857 if (mactype >= chip->n_mactypes || !chip->mactypes[mactype].valid) {
858 phydev_err(phydev, "MACTYPE configuration invalid\n");
859 return -EINVAL;
860 }
861
862 priv->mactype = &chip->mactypes[mactype];
863
864 mv3310_fill_possible_interfaces(phydev);
865
866 /* Enable EDPD mode - saving 600mW */
867 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
868 if (err)
869 return err;
870
871 /* Allow downshift */
872 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
873 if (err && err != -EOPNOTSUPP)
874 return err;
875
876 return 0;
877}
878
879static int mv3310_get_features(struct phy_device *phydev)
880{
881 int ret, val;
882
883 ret = genphy_c45_pma_read_abilities(phydev);
884 if (ret)
885 return ret;
886
887 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
888 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
889 MDIO_PMA_NG_EXTABLE);
890 if (val < 0)
891 return val;
892
893 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
894 phydev->supported,
895 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
896
897 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
898 phydev->supported,
899 val & MDIO_PMA_NG_EXTABLE_5GBT);
900 }
901
902 return 0;
903}
904
905static int mv3310_config_mdix(struct phy_device *phydev)
906{
907 u16 val;
908 int err;
909
910 switch (phydev->mdix_ctrl) {
911 case ETH_TP_MDI_AUTO:
912 val = MV_PCS_CSCR1_MDIX_AUTO;
913 break;
914 case ETH_TP_MDI_X:
915 val = MV_PCS_CSCR1_MDIX_MDIX;
916 break;
917 case ETH_TP_MDI:
918 val = MV_PCS_CSCR1_MDIX_MDI;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
925 MV_PCS_CSCR1_MDIX_MASK, val);
926 if (err > 0)
927 err = mv3310_reset(phydev, MV_PCS_BASE_T);
928
929 return err;
930}
931
932static int mv3310_config_aneg(struct phy_device *phydev)
933{
934 bool changed = false;
935 u16 reg;
936 int ret;
937
938 ret = mv3310_config_mdix(phydev);
939 if (ret < 0)
940 return ret;
941
942 if (phydev->autoneg == AUTONEG_DISABLE)
943 return genphy_c45_pma_setup_forced(phydev);
944
945 ret = genphy_c45_an_config_aneg(phydev);
946 if (ret < 0)
947 return ret;
948 if (ret > 0)
949 changed = true;
950
951 /* Clause 45 has no standardized support for 1000BaseT, therefore
952 * use vendor registers for this mode.
953 */
954 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
955 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
956 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
957 if (ret < 0)
958 return ret;
959 if (ret > 0)
960 changed = true;
961
962 return genphy_c45_check_and_restart_aneg(phydev, changed);
963}
964
965static int mv3310_aneg_done(struct phy_device *phydev)
966{
967 int val;
968
969 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
970 if (val < 0)
971 return val;
972
973 if (val & MDIO_STAT1_LSTATUS)
974 return 1;
975
976 return genphy_c45_aneg_done(phydev);
977}
978
979static void mv3310_update_interface(struct phy_device *phydev)
980{
981 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
982
983 if (!phydev->link)
984 return;
985
986 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
987 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
988 * internal 16KB buffer.
989 *
990 * In USXGMII mode the PHY interface mode is also fixed.
991 */
992 if (priv->mactype->fixed_interface) {
993 phydev->interface = priv->mactype->interface_10g;
994 return;
995 }
996
997 /* The PHY automatically switches its serdes interface (and active PHYXS
998 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
999 * xaui / rxaui modes according to the speed.
1000 * Florian suggests setting phydev->interface to communicate this to the
1001 * MAC. Only do this if we are already in one of the above modes.
1002 */
1003 switch (phydev->speed) {
1004 case SPEED_10000:
1005 phydev->interface = priv->mactype->interface_10g;
1006 break;
1007 case SPEED_5000:
1008 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
1009 break;
1010 case SPEED_2500:
1011 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1012 break;
1013 case SPEED_1000:
1014 case SPEED_100:
1015 case SPEED_10:
1016 phydev->interface = PHY_INTERFACE_MODE_SGMII;
1017 break;
1018 default:
1019 break;
1020 }
1021}
1022
1023/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
1024static int mv3310_read_status_10gbaser(struct phy_device *phydev)
1025{
1026 phydev->link = 1;
1027 phydev->speed = SPEED_10000;
1028 phydev->duplex = DUPLEX_FULL;
1029 phydev->port = PORT_FIBRE;
1030
1031 return 0;
1032}
1033
1034static int mv3310_read_status_copper(struct phy_device *phydev)
1035{
1036 int cssr1, speed, val;
1037
1038 val = genphy_c45_read_link(phydev);
1039 if (val < 0)
1040 return val;
1041
1042 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1043 if (val < 0)
1044 return val;
1045
1046 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
1047 if (cssr1 < 0)
1048 return cssr1;
1049
1050 /* If the link settings are not resolved, mark the link down */
1051 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
1052 phydev->link = 0;
1053 return 0;
1054 }
1055
1056 /* Read the copper link settings */
1057 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
1058 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
1059 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
1060
1061 switch (speed) {
1062 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
1063 phydev->speed = SPEED_10000;
1064 break;
1065
1066 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
1067 phydev->speed = SPEED_5000;
1068 break;
1069
1070 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
1071 phydev->speed = SPEED_2500;
1072 break;
1073
1074 case MV_PCS_CSSR1_SPD1_1000:
1075 phydev->speed = SPEED_1000;
1076 break;
1077
1078 case MV_PCS_CSSR1_SPD1_100:
1079 phydev->speed = SPEED_100;
1080 break;
1081
1082 case MV_PCS_CSSR1_SPD1_10:
1083 phydev->speed = SPEED_10;
1084 break;
1085 }
1086
1087 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1088 DUPLEX_FULL : DUPLEX_HALF;
1089 phydev->port = PORT_TP;
1090 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1091 ETH_TP_MDI_X : ETH_TP_MDI;
1092
1093 if (val & MDIO_AN_STAT1_COMPLETE) {
1094 val = genphy_c45_read_lpa(phydev);
1095 if (val < 0)
1096 return val;
1097
1098 /* Read the link partner's 1G advertisement */
1099 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
1100 if (val < 0)
1101 return val;
1102
1103 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1104
1105 /* Update the pause status */
1106 phy_resolve_aneg_pause(phydev);
1107 }
1108
1109 return 0;
1110}
1111
1112static int mv3310_read_status(struct phy_device *phydev)
1113{
1114 int err, val;
1115
1116 phydev->speed = SPEED_UNKNOWN;
1117 phydev->duplex = DUPLEX_UNKNOWN;
1118 linkmode_zero(phydev->lp_advertising);
1119 phydev->link = 0;
1120 phydev->pause = 0;
1121 phydev->asym_pause = 0;
1122 phydev->mdix = ETH_TP_MDI_INVALID;
1123
1124 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1125 if (val < 0)
1126 return val;
1127
1128 if (val & MDIO_STAT1_LSTATUS)
1129 err = mv3310_read_status_10gbaser(phydev);
1130 else
1131 err = mv3310_read_status_copper(phydev);
1132 if (err < 0)
1133 return err;
1134
1135 if (phydev->link)
1136 mv3310_update_interface(phydev);
1137
1138 return 0;
1139}
1140
1141static int mv3310_get_tunable(struct phy_device *phydev,
1142 struct ethtool_tunable *tuna, void *data)
1143{
1144 switch (tuna->id) {
1145 case ETHTOOL_PHY_DOWNSHIFT:
1146 return mv3310_get_downshift(phydev, data);
1147 case ETHTOOL_PHY_EDPD:
1148 return mv3310_get_edpd(phydev, data);
1149 default:
1150 return -EOPNOTSUPP;
1151 }
1152}
1153
1154static int mv3310_set_tunable(struct phy_device *phydev,
1155 struct ethtool_tunable *tuna, const void *data)
1156{
1157 switch (tuna->id) {
1158 case ETHTOOL_PHY_DOWNSHIFT:
1159 return mv3310_set_downshift(phydev, *(u8 *)data);
1160 case ETHTOOL_PHY_EDPD:
1161 return mv3310_set_edpd(phydev, *(u16 *)data);
1162 default:
1163 return -EOPNOTSUPP;
1164 }
1165}
1166
1167static bool mv3310_has_downshift(struct phy_device *phydev)
1168{
1169 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
1170
1171 /* Fails to downshift with firmware older than v0.3.5.0 */
1172 return priv->firmware_ver >= MV_VERSION(0,3,5,0);
1173}
1174
1175static void mv3310_init_supported_interfaces(unsigned long *mask)
1176{
1177 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1178 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1179 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1180 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
1181 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1182 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1183 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1184}
1185
1186static void mv3340_init_supported_interfaces(unsigned long *mask)
1187{
1188 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1189 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1190 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1191 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1192 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1193 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1194}
1195
1196static void mv2110_init_supported_interfaces(unsigned long *mask)
1197{
1198 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1199 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1200 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1201 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1202 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1203}
1204
1205static void mv2111_init_supported_interfaces(unsigned long *mask)
1206{
1207 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1208 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1209 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1210 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1211}
1212
1213static const struct mv3310_chip mv3310_type = {
1214 .has_downshift = mv3310_has_downshift,
1215 .init_supported_interfaces = mv3310_init_supported_interfaces,
1216 .get_mactype = mv3310_get_mactype,
1217 .set_mactype = mv3310_set_mactype,
1218 .select_mactype = mv3310_select_mactype,
1219
1220 .mactypes = mv3310_mactypes,
1221 .n_mactypes = ARRAY_SIZE(mv3310_mactypes),
1222
1223#ifdef CONFIG_HWMON
1224 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1225#endif
1226};
1227
1228static const struct mv3310_chip mv3340_type = {
1229 .has_downshift = mv3310_has_downshift,
1230 .init_supported_interfaces = mv3340_init_supported_interfaces,
1231 .get_mactype = mv3310_get_mactype,
1232 .set_mactype = mv3310_set_mactype,
1233 .select_mactype = mv3310_select_mactype,
1234
1235 .mactypes = mv3340_mactypes,
1236 .n_mactypes = ARRAY_SIZE(mv3340_mactypes),
1237
1238#ifdef CONFIG_HWMON
1239 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1240#endif
1241};
1242
1243static const struct mv3310_chip mv2110_type = {
1244 .init_supported_interfaces = mv2110_init_supported_interfaces,
1245 .get_mactype = mv2110_get_mactype,
1246 .set_mactype = mv2110_set_mactype,
1247 .select_mactype = mv2110_select_mactype,
1248
1249 .mactypes = mv2110_mactypes,
1250 .n_mactypes = ARRAY_SIZE(mv2110_mactypes),
1251
1252#ifdef CONFIG_HWMON
1253 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1254#endif
1255};
1256
1257static const struct mv3310_chip mv2111_type = {
1258 .init_supported_interfaces = mv2111_init_supported_interfaces,
1259 .get_mactype = mv2110_get_mactype,
1260 .set_mactype = mv2110_set_mactype,
1261 .select_mactype = mv2110_select_mactype,
1262
1263 .mactypes = mv2110_mactypes,
1264 .n_mactypes = ARRAY_SIZE(mv2110_mactypes),
1265
1266#ifdef CONFIG_HWMON
1267 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1268#endif
1269};
1270
1271static int mv3310_get_number_of_ports(struct phy_device *phydev)
1272{
1273 int ret;
1274
1275 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1276 if (ret < 0)
1277 return ret;
1278
1279 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1280 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1281
1282 return ret + 1;
1283}
1284
1285static int mv3310_match_phy_device(struct phy_device *phydev)
1286{
1287 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1288 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1289 return 0;
1290
1291 return mv3310_get_number_of_ports(phydev) == 1;
1292}
1293
1294static int mv3340_match_phy_device(struct phy_device *phydev)
1295{
1296 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1297 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1298 return 0;
1299
1300 return mv3310_get_number_of_ports(phydev) == 4;
1301}
1302
1303static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1304{
1305 int val;
1306
1307 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1308 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1309 return 0;
1310
1311 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1312 if (val < 0)
1313 return val;
1314
1315 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1316}
1317
1318static int mv2110_match_phy_device(struct phy_device *phydev)
1319{
1320 return mv211x_match_phy_device(phydev, true);
1321}
1322
1323static int mv2111_match_phy_device(struct phy_device *phydev)
1324{
1325 return mv211x_match_phy_device(phydev, false);
1326}
1327
1328static void mv3110_get_wol(struct phy_device *phydev,
1329 struct ethtool_wolinfo *wol)
1330{
1331 int ret;
1332
1333 wol->supported = WAKE_MAGIC;
1334 wol->wolopts = 0;
1335
1336 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1337 if (ret < 0)
1338 return;
1339
1340 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
1341 wol->wolopts |= WAKE_MAGIC;
1342}
1343
1344static int mv3110_set_wol(struct phy_device *phydev,
1345 struct ethtool_wolinfo *wol)
1346{
1347 int ret;
1348
1349 if (wol->wolopts & WAKE_MAGIC) {
1350 /* Enable the WOL interrupt */
1351 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1352 MV_V2_PORT_INTR_MASK,
1353 MV_V2_PORT_INTR_STS_WOL_EN);
1354 if (ret < 0)
1355 return ret;
1356
1357 /* Store the device address for the magic packet */
1358 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1359 MV_V2_MAGIC_PKT_WORD2,
1360 ((phydev->attached_dev->dev_addr[5] << 8) |
1361 phydev->attached_dev->dev_addr[4]));
1362 if (ret < 0)
1363 return ret;
1364
1365 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1366 MV_V2_MAGIC_PKT_WORD1,
1367 ((phydev->attached_dev->dev_addr[3] << 8) |
1368 phydev->attached_dev->dev_addr[2]));
1369 if (ret < 0)
1370 return ret;
1371
1372 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1373 MV_V2_MAGIC_PKT_WORD0,
1374 ((phydev->attached_dev->dev_addr[1] << 8) |
1375 phydev->attached_dev->dev_addr[0]));
1376 if (ret < 0)
1377 return ret;
1378
1379 /* Clear WOL status and enable magic packet matching */
1380 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1381 MV_V2_WOL_CTRL,
1382 MV_V2_WOL_CTRL_MAGIC_PKT_EN |
1383 MV_V2_WOL_CTRL_CLEAR_STS);
1384 if (ret < 0)
1385 return ret;
1386 } else {
1387 /* Disable magic packet matching & reset WOL status bit */
1388 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1389 MV_V2_WOL_CTRL,
1390 MV_V2_WOL_CTRL_MAGIC_PKT_EN,
1391 MV_V2_WOL_CTRL_CLEAR_STS);
1392 if (ret < 0)
1393 return ret;
1394 }
1395
1396 /* Reset the clear WOL status bit as it does not self-clear */
1397 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1398 MV_V2_WOL_CTRL,
1399 MV_V2_WOL_CTRL_CLEAR_STS);
1400}
1401
1402static struct phy_driver mv3310_drivers[] = {
1403 {
1404 .phy_id = MARVELL_PHY_ID_88X3310,
1405 .phy_id_mask = MARVELL_PHY_ID_MASK,
1406 .match_phy_device = mv3310_match_phy_device,
1407 .name = "mv88x3310",
1408 .driver_data = &mv3310_type,
1409 .get_features = mv3310_get_features,
1410 .config_init = mv3310_config_init,
1411 .probe = mv3310_probe,
1412 .suspend = mv3310_suspend,
1413 .resume = mv3310_resume,
1414 .config_aneg = mv3310_config_aneg,
1415 .aneg_done = mv3310_aneg_done,
1416 .read_status = mv3310_read_status,
1417 .get_tunable = mv3310_get_tunable,
1418 .set_tunable = mv3310_set_tunable,
1419 .remove = mv3310_remove,
1420 .set_loopback = genphy_c45_loopback,
1421 .get_wol = mv3110_get_wol,
1422 .set_wol = mv3110_set_wol,
1423 },
1424 {
1425 .phy_id = MARVELL_PHY_ID_88X3310,
1426 .phy_id_mask = MARVELL_PHY_ID_MASK,
1427 .match_phy_device = mv3340_match_phy_device,
1428 .name = "mv88x3340",
1429 .driver_data = &mv3340_type,
1430 .get_features = mv3310_get_features,
1431 .config_init = mv3310_config_init,
1432 .probe = mv3310_probe,
1433 .suspend = mv3310_suspend,
1434 .resume = mv3310_resume,
1435 .config_aneg = mv3310_config_aneg,
1436 .aneg_done = mv3310_aneg_done,
1437 .read_status = mv3310_read_status,
1438 .get_tunable = mv3310_get_tunable,
1439 .set_tunable = mv3310_set_tunable,
1440 .remove = mv3310_remove,
1441 .set_loopback = genphy_c45_loopback,
1442 },
1443 {
1444 .phy_id = MARVELL_PHY_ID_88E2110,
1445 .phy_id_mask = MARVELL_PHY_ID_MASK,
1446 .match_phy_device = mv2110_match_phy_device,
1447 .name = "mv88e2110",
1448 .driver_data = &mv2110_type,
1449 .probe = mv3310_probe,
1450 .suspend = mv3310_suspend,
1451 .resume = mv3310_resume,
1452 .config_init = mv3310_config_init,
1453 .config_aneg = mv3310_config_aneg,
1454 .aneg_done = mv3310_aneg_done,
1455 .read_status = mv3310_read_status,
1456 .get_tunable = mv3310_get_tunable,
1457 .set_tunable = mv3310_set_tunable,
1458 .remove = mv3310_remove,
1459 .set_loopback = genphy_c45_loopback,
1460 .get_wol = mv3110_get_wol,
1461 .set_wol = mv3110_set_wol,
1462 },
1463 {
1464 .phy_id = MARVELL_PHY_ID_88E2110,
1465 .phy_id_mask = MARVELL_PHY_ID_MASK,
1466 .match_phy_device = mv2111_match_phy_device,
1467 .name = "mv88e2111",
1468 .driver_data = &mv2111_type,
1469 .probe = mv3310_probe,
1470 .suspend = mv3310_suspend,
1471 .resume = mv3310_resume,
1472 .config_init = mv3310_config_init,
1473 .config_aneg = mv3310_config_aneg,
1474 .aneg_done = mv3310_aneg_done,
1475 .read_status = mv3310_read_status,
1476 .get_tunable = mv3310_get_tunable,
1477 .set_tunable = mv3310_set_tunable,
1478 .remove = mv3310_remove,
1479 .set_loopback = genphy_c45_loopback,
1480 },
1481};
1482
1483module_phy_driver(mv3310_drivers);
1484
1485static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1486 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1487 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1488 { },
1489};
1490MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1491MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1492MODULE_LICENSE("GPL");