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1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/dmaengine.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/of_mdio.h>
29#include <linux/etherdevice.h>
30#include <asm/dma-mapping.h>
31#include <linux/in.h>
32#include <linux/skbuff.h>
33
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <net/checksum.h>
37#include <linux/inet_lro.h>
38#include <linux/prefetch.h>
39
40#include <asm/irq.h>
41#include <asm/firmware.h>
42#include <asm/pasemi_dma.h>
43
44#include "pasemi_mac.h"
45
46/* We have our own align, since ppc64 in general has it at 0 because
47 * of design flaws in some of the server bridge chips. However, for
48 * PWRficient doing the unaligned copies is more expensive than doing
49 * unaligned DMA, so make sure the data is aligned instead.
50 */
51#define LOCAL_SKB_ALIGN 2
52
53/* TODO list
54 *
55 * - Multicast support
56 * - Large MTU support
57 * - SW LRO
58 * - Multiqueue RX/TX
59 */
60
61#define LRO_MAX_AGGR 64
62
63#define PE_MIN_MTU 64
64#define PE_MAX_MTU 9000
65#define PE_DEF_MTU ETH_DATA_LEN
66
67#define DEFAULT_MSG_ENABLE \
68 (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK | \
71 NETIF_MSG_TIMER | \
72 NETIF_MSG_IFDOWN | \
73 NETIF_MSG_IFUP | \
74 NETIF_MSG_RX_ERR | \
75 NETIF_MSG_TX_ERR)
76
77MODULE_LICENSE("GPL");
78MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
79MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
80
81static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
82module_param(debug, int, 0);
83MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
84
85extern const struct ethtool_ops pasemi_mac_ethtool_ops;
86
87static int translation_enabled(void)
88{
89#if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
90 return 1;
91#else
92 return firmware_has_feature(FW_FEATURE_LPAR);
93#endif
94}
95
96static void write_iob_reg(unsigned int reg, unsigned int val)
97{
98 pasemi_write_iob_reg(reg, val);
99}
100
101static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
102{
103 return pasemi_read_mac_reg(mac->dma_if, reg);
104}
105
106static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
107 unsigned int val)
108{
109 pasemi_write_mac_reg(mac->dma_if, reg, val);
110}
111
112static unsigned int read_dma_reg(unsigned int reg)
113{
114 return pasemi_read_dma_reg(reg);
115}
116
117static void write_dma_reg(unsigned int reg, unsigned int val)
118{
119 pasemi_write_dma_reg(reg, val);
120}
121
122static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
123{
124 return mac->rx;
125}
126
127static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
128{
129 return mac->tx;
130}
131
132static inline void prefetch_skb(const struct sk_buff *skb)
133{
134 const void *d = skb;
135
136 prefetch(d);
137 prefetch(d+64);
138 prefetch(d+128);
139 prefetch(d+192);
140}
141
142static int mac_to_intf(struct pasemi_mac *mac)
143{
144 struct pci_dev *pdev = mac->pdev;
145 u32 tmp;
146 int nintf, off, i, j;
147 int devfn = pdev->devfn;
148
149 tmp = read_dma_reg(PAS_DMA_CAP_IFI);
150 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
151 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
152
153 /* IOFF contains the offset to the registers containing the
154 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
155 * of total interfaces. Each register contains 4 devfns.
156 * Just do a linear search until we find the devfn of the MAC
157 * we're trying to look up.
158 */
159
160 for (i = 0; i < (nintf+3)/4; i++) {
161 tmp = read_dma_reg(off+4*i);
162 for (j = 0; j < 4; j++) {
163 if (((tmp >> (8*j)) & 0xff) == devfn)
164 return i*4 + j;
165 }
166 }
167 return -1;
168}
169
170static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
171{
172 unsigned int flags;
173
174 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
175 flags &= ~PAS_MAC_CFG_PCFG_PE;
176 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
177}
178
179static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
180{
181 unsigned int flags;
182
183 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
184 flags |= PAS_MAC_CFG_PCFG_PE;
185 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
186}
187
188static int pasemi_get_mac_addr(struct pasemi_mac *mac)
189{
190 struct pci_dev *pdev = mac->pdev;
191 struct device_node *dn = pci_device_to_OF_node(pdev);
192 int len;
193 const u8 *maddr;
194 u8 addr[6];
195
196 if (!dn) {
197 dev_dbg(&pdev->dev,
198 "No device node for mac, not configuring\n");
199 return -ENOENT;
200 }
201
202 maddr = of_get_property(dn, "local-mac-address", &len);
203
204 if (maddr && len == 6) {
205 memcpy(mac->mac_addr, maddr, 6);
206 return 0;
207 }
208
209 /* Some old versions of firmware mistakenly uses mac-address
210 * (and as a string) instead of a byte array in local-mac-address.
211 */
212
213 if (maddr == NULL)
214 maddr = of_get_property(dn, "mac-address", NULL);
215
216 if (maddr == NULL) {
217 dev_warn(&pdev->dev,
218 "no mac address in device tree, not configuring\n");
219 return -ENOENT;
220 }
221
222 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
223 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
224 dev_warn(&pdev->dev,
225 "can't parse mac address, not configuring\n");
226 return -EINVAL;
227 }
228
229 memcpy(mac->mac_addr, addr, 6);
230
231 return 0;
232}
233
234static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p)
235{
236 struct pasemi_mac *mac = netdev_priv(dev);
237 struct sockaddr *addr = p;
238 unsigned int adr0, adr1;
239
240 if (!is_valid_ether_addr(addr->sa_data))
241 return -EINVAL;
242
243 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
244
245 adr0 = dev->dev_addr[2] << 24 |
246 dev->dev_addr[3] << 16 |
247 dev->dev_addr[4] << 8 |
248 dev->dev_addr[5];
249 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1);
250 adr1 &= ~0xffff;
251 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1];
252
253 pasemi_mac_intf_disable(mac);
254 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0);
255 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1);
256 pasemi_mac_intf_enable(mac);
257
258 return 0;
259}
260
261static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
262 void **tcph, u64 *hdr_flags, void *data)
263{
264 u64 macrx = (u64) data;
265 unsigned int ip_len;
266 struct iphdr *iph;
267
268 /* IPv4 header checksum failed */
269 if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK)
270 return -1;
271
272 /* non tcp packet */
273 skb_reset_network_header(skb);
274 iph = ip_hdr(skb);
275 if (iph->protocol != IPPROTO_TCP)
276 return -1;
277
278 ip_len = ip_hdrlen(skb);
279 skb_set_transport_header(skb, ip_len);
280 *tcph = tcp_hdr(skb);
281
282 /* check if ip header and tcp header are complete */
283 if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb))
284 return -1;
285
286 *hdr_flags = LRO_IPV4 | LRO_TCP;
287 *iphdr = iph;
288
289 return 0;
290}
291
292static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
293 const int nfrags,
294 struct sk_buff *skb,
295 const dma_addr_t *dmas)
296{
297 int f;
298 struct pci_dev *pdev = mac->dma_pdev;
299
300 pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
301
302 for (f = 0; f < nfrags; f++) {
303 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
304
305 pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE);
306 }
307 dev_kfree_skb_irq(skb);
308
309 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
310 * aligned up to a power of 2
311 */
312 return (nfrags + 3) & ~1;
313}
314
315static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
316{
317 struct pasemi_mac_csring *ring;
318 u32 val;
319 unsigned int cfg;
320 int chno;
321
322 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
323 offsetof(struct pasemi_mac_csring, chan));
324
325 if (!ring) {
326 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
327 goto out_chan;
328 }
329
330 chno = ring->chan.chno;
331
332 ring->size = CS_RING_SIZE;
333 ring->next_to_fill = 0;
334
335 /* Allocate descriptors */
336 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
337 goto out_ring_desc;
338
339 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
340 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
341 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
342 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
343
344 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
345
346 ring->events[0] = pasemi_dma_alloc_flag();
347 ring->events[1] = pasemi_dma_alloc_flag();
348 if (ring->events[0] < 0 || ring->events[1] < 0)
349 goto out_flags;
350
351 pasemi_dma_clear_flag(ring->events[0]);
352 pasemi_dma_clear_flag(ring->events[1]);
353
354 ring->fun = pasemi_dma_alloc_fun();
355 if (ring->fun < 0)
356 goto out_fun;
357
358 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
359 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
360 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
361
362 if (translation_enabled())
363 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
364
365 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
366
367 /* enable channel */
368 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
369 PAS_DMA_TXCHAN_TCMDSTA_DB |
370 PAS_DMA_TXCHAN_TCMDSTA_DE |
371 PAS_DMA_TXCHAN_TCMDSTA_DA);
372
373 return ring;
374
375out_fun:
376out_flags:
377 if (ring->events[0] >= 0)
378 pasemi_dma_free_flag(ring->events[0]);
379 if (ring->events[1] >= 0)
380 pasemi_dma_free_flag(ring->events[1]);
381 pasemi_dma_free_ring(&ring->chan);
382out_ring_desc:
383 pasemi_dma_free_chan(&ring->chan);
384out_chan:
385
386 return NULL;
387}
388
389static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
390{
391 int i;
392 mac->cs[0] = pasemi_mac_setup_csring(mac);
393 if (mac->type == MAC_TYPE_XAUI)
394 mac->cs[1] = pasemi_mac_setup_csring(mac);
395 else
396 mac->cs[1] = 0;
397
398 for (i = 0; i < MAX_CS; i++)
399 if (mac->cs[i])
400 mac->num_cs++;
401}
402
403static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
404{
405 pasemi_dma_stop_chan(&csring->chan);
406 pasemi_dma_free_flag(csring->events[0]);
407 pasemi_dma_free_flag(csring->events[1]);
408 pasemi_dma_free_ring(&csring->chan);
409 pasemi_dma_free_chan(&csring->chan);
410 pasemi_dma_free_fun(csring->fun);
411}
412
413static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
414{
415 struct pasemi_mac_rxring *ring;
416 struct pasemi_mac *mac = netdev_priv(dev);
417 int chno;
418 unsigned int cfg;
419
420 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
421 offsetof(struct pasemi_mac_rxring, chan));
422
423 if (!ring) {
424 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
425 goto out_chan;
426 }
427 chno = ring->chan.chno;
428
429 spin_lock_init(&ring->lock);
430
431 ring->size = RX_RING_SIZE;
432 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
433 RX_RING_SIZE, GFP_KERNEL);
434
435 if (!ring->ring_info)
436 goto out_ring_info;
437
438 /* Allocate descriptors */
439 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
440 goto out_ring_desc;
441
442 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
443 RX_RING_SIZE * sizeof(u64),
444 &ring->buf_dma, GFP_KERNEL);
445 if (!ring->buffers)
446 goto out_ring_desc;
447
448 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
449
450 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
451 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
452
453 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
454 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
455 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
456
457 cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
458
459 if (translation_enabled())
460 cfg |= PAS_DMA_RXCHAN_CFG_CTR;
461
462 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
463
464 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
465 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
466
467 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
468 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
469 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
470
471 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
472 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
473 PAS_DMA_RXINT_CFG_HEN;
474
475 if (translation_enabled())
476 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
477
478 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
479
480 ring->next_to_fill = 0;
481 ring->next_to_clean = 0;
482 ring->mac = mac;
483 mac->rx = ring;
484
485 return 0;
486
487out_ring_desc:
488 kfree(ring->ring_info);
489out_ring_info:
490 pasemi_dma_free_chan(&ring->chan);
491out_chan:
492 return -ENOMEM;
493}
494
495static struct pasemi_mac_txring *
496pasemi_mac_setup_tx_resources(const struct net_device *dev)
497{
498 struct pasemi_mac *mac = netdev_priv(dev);
499 u32 val;
500 struct pasemi_mac_txring *ring;
501 unsigned int cfg;
502 int chno;
503
504 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
505 offsetof(struct pasemi_mac_txring, chan));
506
507 if (!ring) {
508 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
509 goto out_chan;
510 }
511
512 chno = ring->chan.chno;
513
514 spin_lock_init(&ring->lock);
515
516 ring->size = TX_RING_SIZE;
517 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
518 TX_RING_SIZE, GFP_KERNEL);
519 if (!ring->ring_info)
520 goto out_ring_info;
521
522 /* Allocate descriptors */
523 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
524 goto out_ring_desc;
525
526 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
527 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
528 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
529 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
530
531 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
532
533 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
534 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
535 PAS_DMA_TXCHAN_CFG_UP |
536 PAS_DMA_TXCHAN_CFG_WT(4);
537
538 if (translation_enabled())
539 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
540
541 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
542
543 ring->next_to_fill = 0;
544 ring->next_to_clean = 0;
545 ring->mac = mac;
546
547 return ring;
548
549out_ring_desc:
550 kfree(ring->ring_info);
551out_ring_info:
552 pasemi_dma_free_chan(&ring->chan);
553out_chan:
554 return NULL;
555}
556
557static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
558{
559 struct pasemi_mac_txring *txring = tx_ring(mac);
560 unsigned int i, j;
561 struct pasemi_mac_buffer *info;
562 dma_addr_t dmas[MAX_SKB_FRAGS+1];
563 int freed, nfrags;
564 int start, limit;
565
566 start = txring->next_to_clean;
567 limit = txring->next_to_fill;
568
569 /* Compensate for when fill has wrapped and clean has not */
570 if (start > limit)
571 limit += TX_RING_SIZE;
572
573 for (i = start; i < limit; i += freed) {
574 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
575 if (info->dma && info->skb) {
576 nfrags = skb_shinfo(info->skb)->nr_frags;
577 for (j = 0; j <= nfrags; j++)
578 dmas[j] = txring->ring_info[(i+1+j) &
579 (TX_RING_SIZE-1)].dma;
580 freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
581 info->skb, dmas);
582 } else
583 freed = 2;
584 }
585
586 kfree(txring->ring_info);
587 pasemi_dma_free_chan(&txring->chan);
588
589}
590
591static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac)
592{
593 struct pasemi_mac_rxring *rx = rx_ring(mac);
594 unsigned int i;
595 struct pasemi_mac_buffer *info;
596
597 for (i = 0; i < RX_RING_SIZE; i++) {
598 info = &RX_DESC_INFO(rx, i);
599 if (info->skb && info->dma) {
600 pci_unmap_single(mac->dma_pdev,
601 info->dma,
602 info->skb->len,
603 PCI_DMA_FROMDEVICE);
604 dev_kfree_skb_any(info->skb);
605 }
606 info->dma = 0;
607 info->skb = NULL;
608 }
609
610 for (i = 0; i < RX_RING_SIZE; i++)
611 RX_BUFF(rx, i) = 0;
612}
613
614static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
615{
616 pasemi_mac_free_rx_buffers(mac);
617
618 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
619 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
620
621 kfree(rx_ring(mac)->ring_info);
622 pasemi_dma_free_chan(&rx_ring(mac)->chan);
623 mac->rx = NULL;
624}
625
626static void pasemi_mac_replenish_rx_ring(const struct net_device *dev,
627 const int limit)
628{
629 const struct pasemi_mac *mac = netdev_priv(dev);
630 struct pasemi_mac_rxring *rx = rx_ring(mac);
631 int fill, count;
632
633 if (limit <= 0)
634 return;
635
636 fill = rx_ring(mac)->next_to_fill;
637 for (count = 0; count < limit; count++) {
638 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
639 u64 *buff = &RX_BUFF(rx, fill);
640 struct sk_buff *skb;
641 dma_addr_t dma;
642
643 /* Entry in use? */
644 WARN_ON(*buff);
645
646 skb = dev_alloc_skb(mac->bufsz);
647 skb_reserve(skb, LOCAL_SKB_ALIGN);
648
649 if (unlikely(!skb))
650 break;
651
652 dma = pci_map_single(mac->dma_pdev, skb->data,
653 mac->bufsz - LOCAL_SKB_ALIGN,
654 PCI_DMA_FROMDEVICE);
655
656 if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) {
657 dev_kfree_skb_irq(info->skb);
658 break;
659 }
660
661 info->skb = skb;
662 info->dma = dma;
663 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma);
664 fill++;
665 }
666
667 wmb();
668
669 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
670
671 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
672 (RX_RING_SIZE - 1);
673}
674
675static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
676{
677 struct pasemi_mac_rxring *rx = rx_ring(mac);
678 unsigned int reg, pcnt;
679 /* Re-enable packet count interrupts: finally
680 * ack the packet count interrupt we got in rx_intr.
681 */
682
683 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
684
685 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
686
687 if (*rx->chan.status & PAS_STATUS_TIMER)
688 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
689
690 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
691}
692
693static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
694{
695 unsigned int reg, pcnt;
696
697 /* Re-enable packet count interrupts */
698 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
699
700 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
701
702 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
703}
704
705
706static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
707 const u64 macrx)
708{
709 unsigned int rcmdsta, ccmdsta;
710 struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
711
712 if (!netif_msg_rx_err(mac))
713 return;
714
715 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
716 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
717
718 printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n",
719 macrx, *chan->status);
720
721 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
722 rcmdsta, ccmdsta);
723}
724
725static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
726 const u64 mactx)
727{
728 unsigned int cmdsta;
729 struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
730
731 if (!netif_msg_tx_err(mac))
732 return;
733
734 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
735
736 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\
737 "tx status 0x%016llx\n", mactx, *chan->status);
738
739 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
740}
741
742static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
743 const int limit)
744{
745 const struct pasemi_dmachan *chan = &rx->chan;
746 struct pasemi_mac *mac = rx->mac;
747 struct pci_dev *pdev = mac->dma_pdev;
748 unsigned int n;
749 int count, buf_index, tot_bytes, packets;
750 struct pasemi_mac_buffer *info;
751 struct sk_buff *skb;
752 unsigned int len;
753 u64 macrx, eval;
754 dma_addr_t dma;
755
756 tot_bytes = 0;
757 packets = 0;
758
759 spin_lock(&rx->lock);
760
761 n = rx->next_to_clean;
762
763 prefetch(&RX_DESC(rx, n));
764
765 for (count = 0; count < limit; count++) {
766 macrx = RX_DESC(rx, n);
767 prefetch(&RX_DESC(rx, n+4));
768
769 if ((macrx & XCT_MACRX_E) ||
770 (*chan->status & PAS_STATUS_ERROR))
771 pasemi_mac_rx_error(mac, macrx);
772
773 if (!(macrx & XCT_MACRX_O))
774 break;
775
776 info = NULL;
777
778 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
779
780 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
781 XCT_RXRES_8B_EVAL_S;
782 buf_index = eval-1;
783
784 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
785 info = &RX_DESC_INFO(rx, buf_index);
786
787 skb = info->skb;
788
789 prefetch_skb(skb);
790
791 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
792
793 pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN,
794 PCI_DMA_FROMDEVICE);
795
796 if (macrx & XCT_MACRX_CRC) {
797 /* CRC error flagged */
798 mac->netdev->stats.rx_errors++;
799 mac->netdev->stats.rx_crc_errors++;
800 /* No need to free skb, it'll be reused */
801 goto next;
802 }
803
804 info->skb = NULL;
805 info->dma = 0;
806
807 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
808 skb->ip_summed = CHECKSUM_UNNECESSARY;
809 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
810 XCT_MACRX_CSUM_S;
811 } else
812 skb_checksum_none_assert(skb);
813
814 packets++;
815 tot_bytes += len;
816
817 /* Don't include CRC */
818 skb_put(skb, len-4);
819
820 skb->protocol = eth_type_trans(skb, mac->netdev);
821 lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx);
822
823next:
824 RX_DESC(rx, n) = 0;
825 RX_DESC(rx, n+1) = 0;
826
827 /* Need to zero it out since hardware doesn't, since the
828 * replenish loop uses it to tell when it's done.
829 */
830 RX_BUFF(rx, buf_index) = 0;
831
832 n += 4;
833 }
834
835 if (n > RX_RING_SIZE) {
836 /* Errata 5971 workaround: L2 target of headers */
837 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
838 n &= (RX_RING_SIZE-1);
839 }
840
841 rx_ring(mac)->next_to_clean = n;
842
843 lro_flush_all(&mac->lro_mgr);
844
845 /* Increase is in number of 16-byte entries, and since each descriptor
846 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
847 * count*2.
848 */
849 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
850
851 pasemi_mac_replenish_rx_ring(mac->netdev, count);
852
853 mac->netdev->stats.rx_bytes += tot_bytes;
854 mac->netdev->stats.rx_packets += packets;
855
856 spin_unlock(&rx_ring(mac)->lock);
857
858 return count;
859}
860
861/* Can't make this too large or we blow the kernel stack limits */
862#define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
863
864static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
865{
866 struct pasemi_dmachan *chan = &txring->chan;
867 struct pasemi_mac *mac = txring->mac;
868 int i, j;
869 unsigned int start, descr_count, buf_count, batch_limit;
870 unsigned int ring_limit;
871 unsigned int total_count;
872 unsigned long flags;
873 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
874 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
875 int nf[TX_CLEAN_BATCHSIZE];
876 int nr_frags;
877
878 total_count = 0;
879 batch_limit = TX_CLEAN_BATCHSIZE;
880restart:
881 spin_lock_irqsave(&txring->lock, flags);
882
883 start = txring->next_to_clean;
884 ring_limit = txring->next_to_fill;
885
886 prefetch(&TX_DESC_INFO(txring, start+1).skb);
887
888 /* Compensate for when fill has wrapped but clean has not */
889 if (start > ring_limit)
890 ring_limit += TX_RING_SIZE;
891
892 buf_count = 0;
893 descr_count = 0;
894
895 for (i = start;
896 descr_count < batch_limit && i < ring_limit;
897 i += buf_count) {
898 u64 mactx = TX_DESC(txring, i);
899 struct sk_buff *skb;
900
901 if ((mactx & XCT_MACTX_E) ||
902 (*chan->status & PAS_STATUS_ERROR))
903 pasemi_mac_tx_error(mac, mactx);
904
905 /* Skip over control descriptors */
906 if (!(mactx & XCT_MACTX_LLEN_M)) {
907 TX_DESC(txring, i) = 0;
908 TX_DESC(txring, i+1) = 0;
909 buf_count = 2;
910 continue;
911 }
912
913 skb = TX_DESC_INFO(txring, i+1).skb;
914 nr_frags = TX_DESC_INFO(txring, i).dma;
915
916 if (unlikely(mactx & XCT_MACTX_O))
917 /* Not yet transmitted */
918 break;
919
920 buf_count = 2 + nr_frags;
921 /* Since we always fill with an even number of entries, make
922 * sure we skip any unused one at the end as well.
923 */
924 if (buf_count & 1)
925 buf_count++;
926
927 for (j = 0; j <= nr_frags; j++)
928 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
929
930 skbs[descr_count] = skb;
931 nf[descr_count] = nr_frags;
932
933 TX_DESC(txring, i) = 0;
934 TX_DESC(txring, i+1) = 0;
935
936 descr_count++;
937 }
938 txring->next_to_clean = i & (TX_RING_SIZE-1);
939
940 spin_unlock_irqrestore(&txring->lock, flags);
941 netif_wake_queue(mac->netdev);
942
943 for (i = 0; i < descr_count; i++)
944 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
945
946 total_count += descr_count;
947
948 /* If the batch was full, try to clean more */
949 if (descr_count == batch_limit)
950 goto restart;
951
952 return total_count;
953}
954
955
956static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
957{
958 const struct pasemi_mac_rxring *rxring = data;
959 struct pasemi_mac *mac = rxring->mac;
960 const struct pasemi_dmachan *chan = &rxring->chan;
961 unsigned int reg;
962
963 if (!(*chan->status & PAS_STATUS_CAUSE_M))
964 return IRQ_NONE;
965
966 /* Don't reset packet count so it won't fire again but clear
967 * all others.
968 */
969
970 reg = 0;
971 if (*chan->status & PAS_STATUS_SOFT)
972 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
973 if (*chan->status & PAS_STATUS_ERROR)
974 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
975
976 napi_schedule(&mac->napi);
977
978 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
979
980 return IRQ_HANDLED;
981}
982
983#define TX_CLEAN_INTERVAL HZ
984
985static void pasemi_mac_tx_timer(unsigned long data)
986{
987 struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data;
988 struct pasemi_mac *mac = txring->mac;
989
990 pasemi_mac_clean_tx(txring);
991
992 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
993
994 pasemi_mac_restart_tx_intr(mac);
995}
996
997static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
998{
999 struct pasemi_mac_txring *txring = data;
1000 const struct pasemi_dmachan *chan = &txring->chan;
1001 struct pasemi_mac *mac = txring->mac;
1002 unsigned int reg;
1003
1004 if (!(*chan->status & PAS_STATUS_CAUSE_M))
1005 return IRQ_NONE;
1006
1007 reg = 0;
1008
1009 if (*chan->status & PAS_STATUS_SOFT)
1010 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
1011 if (*chan->status & PAS_STATUS_ERROR)
1012 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
1013
1014 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
1015
1016 napi_schedule(&mac->napi);
1017
1018 if (reg)
1019 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
1020
1021 return IRQ_HANDLED;
1022}
1023
1024static void pasemi_adjust_link(struct net_device *dev)
1025{
1026 struct pasemi_mac *mac = netdev_priv(dev);
1027 int msg;
1028 unsigned int flags;
1029 unsigned int new_flags;
1030
1031 if (!mac->phydev->link) {
1032 /* If no link, MAC speed settings don't matter. Just report
1033 * link down and return.
1034 */
1035 if (mac->link && netif_msg_link(mac))
1036 printk(KERN_INFO "%s: Link is down.\n", dev->name);
1037
1038 netif_carrier_off(dev);
1039 pasemi_mac_intf_disable(mac);
1040 mac->link = 0;
1041
1042 return;
1043 } else {
1044 pasemi_mac_intf_enable(mac);
1045 netif_carrier_on(dev);
1046 }
1047
1048 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1049 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
1050 PAS_MAC_CFG_PCFG_TSR_M);
1051
1052 if (!mac->phydev->duplex)
1053 new_flags |= PAS_MAC_CFG_PCFG_HD;
1054
1055 switch (mac->phydev->speed) {
1056 case 1000:
1057 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
1058 PAS_MAC_CFG_PCFG_TSR_1G;
1059 break;
1060 case 100:
1061 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
1062 PAS_MAC_CFG_PCFG_TSR_100M;
1063 break;
1064 case 10:
1065 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
1066 PAS_MAC_CFG_PCFG_TSR_10M;
1067 break;
1068 default:
1069 printk("Unsupported speed %d\n", mac->phydev->speed);
1070 }
1071
1072 /* Print on link or speed/duplex change */
1073 msg = mac->link != mac->phydev->link || flags != new_flags;
1074
1075 mac->duplex = mac->phydev->duplex;
1076 mac->speed = mac->phydev->speed;
1077 mac->link = mac->phydev->link;
1078
1079 if (new_flags != flags)
1080 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
1081
1082 if (msg && netif_msg_link(mac))
1083 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
1084 dev->name, mac->speed, mac->duplex ? "full" : "half");
1085}
1086
1087static int pasemi_mac_phy_init(struct net_device *dev)
1088{
1089 struct pasemi_mac *mac = netdev_priv(dev);
1090 struct device_node *dn, *phy_dn;
1091 struct phy_device *phydev;
1092
1093 dn = pci_device_to_OF_node(mac->pdev);
1094 phy_dn = of_parse_phandle(dn, "phy-handle", 0);
1095 of_node_put(phy_dn);
1096
1097 mac->link = 0;
1098 mac->speed = 0;
1099 mac->duplex = -1;
1100
1101 phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0,
1102 PHY_INTERFACE_MODE_SGMII);
1103
1104 if (IS_ERR(phydev)) {
1105 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
1106 return PTR_ERR(phydev);
1107 }
1108
1109 mac->phydev = phydev;
1110
1111 return 0;
1112}
1113
1114
1115static int pasemi_mac_open(struct net_device *dev)
1116{
1117 struct pasemi_mac *mac = netdev_priv(dev);
1118 unsigned int flags;
1119 int i, ret;
1120
1121 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1122 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1123 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1124
1125 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
1126
1127 ret = pasemi_mac_setup_rx_resources(dev);
1128 if (ret)
1129 goto out_rx_resources;
1130
1131 mac->tx = pasemi_mac_setup_tx_resources(dev);
1132
1133 if (!mac->tx)
1134 goto out_tx_ring;
1135
1136 /* We might already have allocated rings in case mtu was changed
1137 * before interface was brought up.
1138 */
1139 if (dev->mtu > 1500 && !mac->num_cs) {
1140 pasemi_mac_setup_csrings(mac);
1141 if (!mac->num_cs)
1142 goto out_tx_ring;
1143 }
1144
1145 /* Zero out rmon counters */
1146 for (i = 0; i < 32; i++)
1147 write_mac_reg(mac, PAS_MAC_RMON(i), 0);
1148
1149 /* 0x3ff with 33MHz clock is about 31us */
1150 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1151 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1152
1153 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
1154 PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
1155
1156 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
1157 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
1158
1159 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
1160 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1161 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
1162
1163 /* enable rx if */
1164 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1165 PAS_DMA_RXINT_RCMDSTA_EN |
1166 PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1167 PAS_DMA_RXINT_RCMDSTA_BP |
1168 PAS_DMA_RXINT_RCMDSTA_OO |
1169 PAS_DMA_RXINT_RCMDSTA_BT);
1170
1171 /* enable rx channel */
1172 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1173 PAS_DMA_RXCHAN_CCMDSTA_OD |
1174 PAS_DMA_RXCHAN_CCMDSTA_FD |
1175 PAS_DMA_RXCHAN_CCMDSTA_DT);
1176
1177 /* enable tx channel */
1178 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1179 PAS_DMA_TXCHAN_TCMDSTA_DB |
1180 PAS_DMA_TXCHAN_TCMDSTA_DE |
1181 PAS_DMA_TXCHAN_TCMDSTA_DA);
1182
1183 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
1184
1185 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1186 RX_RING_SIZE>>1);
1187
1188 /* Clear out any residual packet count state from firmware */
1189 pasemi_mac_restart_rx_intr(mac);
1190 pasemi_mac_restart_tx_intr(mac);
1191
1192 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
1193
1194 if (mac->type == MAC_TYPE_GMAC)
1195 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1196 else
1197 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1198
1199 /* Enable interface in MAC */
1200 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1201
1202 ret = pasemi_mac_phy_init(dev);
1203 if (ret) {
1204 /* Since we won't get link notification, just enable RX */
1205 pasemi_mac_intf_enable(mac);
1206 if (mac->type == MAC_TYPE_GMAC) {
1207 /* Warn for missing PHY on SGMII (1Gig) ports */
1208 dev_warn(&mac->pdev->dev,
1209 "PHY init failed: %d.\n", ret);
1210 dev_warn(&mac->pdev->dev,
1211 "Defaulting to 1Gbit full duplex\n");
1212 }
1213 }
1214
1215 netif_start_queue(dev);
1216 napi_enable(&mac->napi);
1217
1218 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1219 dev->name);
1220
1221 ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, IRQF_DISABLED,
1222 mac->tx_irq_name, mac->tx);
1223 if (ret) {
1224 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1225 mac->tx->chan.irq, ret);
1226 goto out_tx_int;
1227 }
1228
1229 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1230 dev->name);
1231
1232 ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, IRQF_DISABLED,
1233 mac->rx_irq_name, mac->rx);
1234 if (ret) {
1235 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1236 mac->rx->chan.irq, ret);
1237 goto out_rx_int;
1238 }
1239
1240 if (mac->phydev)
1241 phy_start(mac->phydev);
1242
1243 init_timer(&mac->tx->clean_timer);
1244 mac->tx->clean_timer.function = pasemi_mac_tx_timer;
1245 mac->tx->clean_timer.data = (unsigned long)mac->tx;
1246 mac->tx->clean_timer.expires = jiffies+HZ;
1247 add_timer(&mac->tx->clean_timer);
1248
1249 return 0;
1250
1251out_rx_int:
1252 free_irq(mac->tx->chan.irq, mac->tx);
1253out_tx_int:
1254 napi_disable(&mac->napi);
1255 netif_stop_queue(dev);
1256out_tx_ring:
1257 if (mac->tx)
1258 pasemi_mac_free_tx_resources(mac);
1259 pasemi_mac_free_rx_resources(mac);
1260out_rx_resources:
1261
1262 return ret;
1263}
1264
1265#define MAX_RETRIES 5000
1266
1267static void pasemi_mac_pause_txchan(struct pasemi_mac *mac)
1268{
1269 unsigned int sta, retries;
1270 int txch = tx_ring(mac)->chan.chno;
1271
1272 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
1273 PAS_DMA_TXCHAN_TCMDSTA_ST);
1274
1275 for (retries = 0; retries < MAX_RETRIES; retries++) {
1276 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1277 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
1278 break;
1279 cond_resched();
1280 }
1281
1282 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
1283 dev_err(&mac->dma_pdev->dev,
1284 "Failed to stop tx channel, tcmdsta %08x\n", sta);
1285
1286 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1287}
1288
1289static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac)
1290{
1291 unsigned int sta, retries;
1292 int rxch = rx_ring(mac)->chan.chno;
1293
1294 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
1295 PAS_DMA_RXCHAN_CCMDSTA_ST);
1296 for (retries = 0; retries < MAX_RETRIES; retries++) {
1297 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1298 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
1299 break;
1300 cond_resched();
1301 }
1302
1303 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
1304 dev_err(&mac->dma_pdev->dev,
1305 "Failed to stop rx channel, ccmdsta 08%x\n", sta);
1306 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1307}
1308
1309static void pasemi_mac_pause_rxint(struct pasemi_mac *mac)
1310{
1311 unsigned int sta, retries;
1312
1313 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1314 PAS_DMA_RXINT_RCMDSTA_ST);
1315 for (retries = 0; retries < MAX_RETRIES; retries++) {
1316 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1317 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
1318 break;
1319 cond_resched();
1320 }
1321
1322 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
1323 dev_err(&mac->dma_pdev->dev,
1324 "Failed to stop rx interface, rcmdsta %08x\n", sta);
1325 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
1326}
1327
1328static int pasemi_mac_close(struct net_device *dev)
1329{
1330 struct pasemi_mac *mac = netdev_priv(dev);
1331 unsigned int sta;
1332 int rxch, txch, i;
1333
1334 rxch = rx_ring(mac)->chan.chno;
1335 txch = tx_ring(mac)->chan.chno;
1336
1337 if (mac->phydev) {
1338 phy_stop(mac->phydev);
1339 phy_disconnect(mac->phydev);
1340 }
1341
1342 del_timer_sync(&mac->tx->clean_timer);
1343
1344 netif_stop_queue(dev);
1345 napi_disable(&mac->napi);
1346
1347 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1348 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1349 PAS_DMA_RXINT_RCMDSTA_OO |
1350 PAS_DMA_RXINT_RCMDSTA_BT))
1351 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1352
1353 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1354 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1355 PAS_DMA_RXCHAN_CCMDSTA_OD |
1356 PAS_DMA_RXCHAN_CCMDSTA_FD |
1357 PAS_DMA_RXCHAN_CCMDSTA_DT))
1358 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1359
1360 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1361 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1362 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
1363 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1364
1365 /* Clean out any pending buffers */
1366 pasemi_mac_clean_tx(tx_ring(mac));
1367 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1368
1369 pasemi_mac_pause_txchan(mac);
1370 pasemi_mac_pause_rxint(mac);
1371 pasemi_mac_pause_rxchan(mac);
1372 pasemi_mac_intf_disable(mac);
1373
1374 free_irq(mac->tx->chan.irq, mac->tx);
1375 free_irq(mac->rx->chan.irq, mac->rx);
1376
1377 for (i = 0; i < mac->num_cs; i++) {
1378 pasemi_mac_free_csring(mac->cs[i]);
1379 mac->cs[i] = NULL;
1380 }
1381
1382 mac->num_cs = 0;
1383
1384 /* Free resources */
1385 pasemi_mac_free_rx_resources(mac);
1386 pasemi_mac_free_tx_resources(mac);
1387
1388 return 0;
1389}
1390
1391static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
1392 const dma_addr_t *map,
1393 const unsigned int *map_size,
1394 struct pasemi_mac_txring *txring,
1395 struct pasemi_mac_csring *csring)
1396{
1397 u64 fund;
1398 dma_addr_t cs_dest;
1399 const int nh_off = skb_network_offset(skb);
1400 const int nh_len = skb_network_header_len(skb);
1401 const int nfrags = skb_shinfo(skb)->nr_frags;
1402 int cs_size, i, fill, hdr, cpyhdr, evt;
1403 dma_addr_t csdma;
1404
1405 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
1406 XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1407 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
1408 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
1409
1410 switch (ip_hdr(skb)->protocol) {
1411 case IPPROTO_TCP:
1412 fund |= XCT_FUN_SIG_TCP4;
1413 /* TCP checksum is 16 bytes into the header */
1414 cs_dest = map[0] + skb_transport_offset(skb) + 16;
1415 break;
1416 case IPPROTO_UDP:
1417 fund |= XCT_FUN_SIG_UDP4;
1418 /* UDP checksum is 6 bytes into the header */
1419 cs_dest = map[0] + skb_transport_offset(skb) + 6;
1420 break;
1421 default:
1422 BUG();
1423 }
1424
1425 /* Do the checksum offloaded */
1426 fill = csring->next_to_fill;
1427 hdr = fill;
1428
1429 CS_DESC(csring, fill++) = fund;
1430 /* Room for 8BRES. Checksum result is really 2 bytes into it */
1431 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
1432 CS_DESC(csring, fill++) = 0;
1433
1434 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
1435 for (i = 1; i <= nfrags; i++)
1436 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1437
1438 fill += i;
1439 if (fill & 1)
1440 fill++;
1441
1442 /* Copy the result into the TCP packet */
1443 cpyhdr = fill;
1444 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1445 XCT_FUN_LLEN(2) | XCT_FUN_SE;
1446 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
1447 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
1448 fill++;
1449
1450 evt = !csring->last_event;
1451 csring->last_event = evt;
1452
1453 /* Event handshaking with MAC TX */
1454 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1455 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
1456 CS_DESC(csring, fill++) = 0;
1457 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1458 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
1459 CS_DESC(csring, fill++) = 0;
1460 csring->next_to_fill = fill & (CS_RING_SIZE-1);
1461
1462 cs_size = fill - hdr;
1463 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
1464
1465 /* TX-side event handshaking */
1466 fill = txring->next_to_fill;
1467 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1468 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
1469 TX_DESC(txring, fill++) = 0;
1470 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1471 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
1472 TX_DESC(txring, fill++) = 0;
1473 txring->next_to_fill = fill;
1474
1475 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
1476}
1477
1478static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1479{
1480 struct pasemi_mac * const mac = netdev_priv(dev);
1481 struct pasemi_mac_txring * const txring = tx_ring(mac);
1482 struct pasemi_mac_csring *csring;
1483 u64 dflags = 0;
1484 u64 mactx;
1485 dma_addr_t map[MAX_SKB_FRAGS+1];
1486 unsigned int map_size[MAX_SKB_FRAGS+1];
1487 unsigned long flags;
1488 int i, nfrags;
1489 int fill;
1490 const int nh_off = skb_network_offset(skb);
1491 const int nh_len = skb_network_header_len(skb);
1492
1493 prefetch(&txring->ring_info);
1494
1495 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
1496
1497 nfrags = skb_shinfo(skb)->nr_frags;
1498
1499 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1500 PCI_DMA_TODEVICE);
1501 map_size[0] = skb_headlen(skb);
1502 if (pci_dma_mapping_error(mac->dma_pdev, map[0]))
1503 goto out_err_nolock;
1504
1505 for (i = 0; i < nfrags; i++) {
1506 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1507
1508 map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
1509 frag->page_offset, frag->size,
1510 PCI_DMA_TODEVICE);
1511 map_size[i+1] = frag->size;
1512 if (pci_dma_mapping_error(mac->dma_pdev, map[i+1])) {
1513 nfrags = i;
1514 goto out_err_nolock;
1515 }
1516 }
1517
1518 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
1519 switch (ip_hdr(skb)->protocol) {
1520 case IPPROTO_TCP:
1521 dflags |= XCT_MACTX_CSUM_TCP;
1522 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1523 dflags |= XCT_MACTX_IPO(nh_off);
1524 break;
1525 case IPPROTO_UDP:
1526 dflags |= XCT_MACTX_CSUM_UDP;
1527 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1528 dflags |= XCT_MACTX_IPO(nh_off);
1529 break;
1530 default:
1531 WARN_ON(1);
1532 }
1533 }
1534
1535 mactx = dflags | XCT_MACTX_LLEN(skb->len);
1536
1537 spin_lock_irqsave(&txring->lock, flags);
1538
1539 /* Avoid stepping on the same cache line that the DMA controller
1540 * is currently about to send, so leave at least 8 words available.
1541 * Total free space needed is mactx + fragments + 8
1542 */
1543 if (RING_AVAIL(txring) < nfrags + 14) {
1544 /* no room -- stop the queue and wait for tx intr */
1545 netif_stop_queue(dev);
1546 goto out_err;
1547 }
1548
1549 /* Queue up checksum + event descriptors, if needed */
1550 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
1551 csring = mac->cs[mac->last_cs];
1552 mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
1553
1554 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
1555 }
1556
1557 fill = txring->next_to_fill;
1558 TX_DESC(txring, fill) = mactx;
1559 TX_DESC_INFO(txring, fill).dma = nfrags;
1560 fill++;
1561 TX_DESC_INFO(txring, fill).skb = skb;
1562 for (i = 0; i <= nfrags; i++) {
1563 TX_DESC(txring, fill+i) =
1564 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1565 TX_DESC_INFO(txring, fill+i).dma = map[i];
1566 }
1567
1568 /* We have to add an even number of 8-byte entries to the ring
1569 * even if the last one is unused. That means always an odd number
1570 * of pointers + one mactx descriptor.
1571 */
1572 if (nfrags & 1)
1573 nfrags++;
1574
1575 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
1576
1577 dev->stats.tx_packets++;
1578 dev->stats.tx_bytes += skb->len;
1579
1580 spin_unlock_irqrestore(&txring->lock, flags);
1581
1582 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
1583
1584 return NETDEV_TX_OK;
1585
1586out_err:
1587 spin_unlock_irqrestore(&txring->lock, flags);
1588out_err_nolock:
1589 while (nfrags--)
1590 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1591 PCI_DMA_TODEVICE);
1592
1593 return NETDEV_TX_BUSY;
1594}
1595
1596static void pasemi_mac_set_rx_mode(struct net_device *dev)
1597{
1598 const struct pasemi_mac *mac = netdev_priv(dev);
1599 unsigned int flags;
1600
1601 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1602
1603 /* Set promiscuous */
1604 if (dev->flags & IFF_PROMISC)
1605 flags |= PAS_MAC_CFG_PCFG_PR;
1606 else
1607 flags &= ~PAS_MAC_CFG_PCFG_PR;
1608
1609 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1610}
1611
1612
1613static int pasemi_mac_poll(struct napi_struct *napi, int budget)
1614{
1615 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1616 int pkts;
1617
1618 pasemi_mac_clean_tx(tx_ring(mac));
1619 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
1620 if (pkts < budget) {
1621 /* all done, no more packets present */
1622 napi_complete(napi);
1623
1624 pasemi_mac_restart_rx_intr(mac);
1625 pasemi_mac_restart_tx_intr(mac);
1626 }
1627 return pkts;
1628}
1629
1630#ifdef CONFIG_NET_POLL_CONTROLLER
1631/*
1632 * Polling 'interrupt' - used by things like netconsole to send skbs
1633 * without having to re-enable interrupts. It's not called while
1634 * the interrupt routine is executing.
1635 */
1636static void pasemi_mac_netpoll(struct net_device *dev)
1637{
1638 const struct pasemi_mac *mac = netdev_priv(dev);
1639
1640 disable_irq(mac->tx->chan.irq);
1641 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
1642 enable_irq(mac->tx->chan.irq);
1643
1644 disable_irq(mac->rx->chan.irq);
1645 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
1646 enable_irq(mac->rx->chan.irq);
1647}
1648#endif
1649
1650static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
1651{
1652 struct pasemi_mac *mac = netdev_priv(dev);
1653 unsigned int reg;
1654 unsigned int rcmdsta = 0;
1655 int running;
1656 int ret = 0;
1657
1658 if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU)
1659 return -EINVAL;
1660
1661 running = netif_running(dev);
1662
1663 if (running) {
1664 /* Need to stop the interface, clean out all already
1665 * received buffers, free all unused buffers on the RX
1666 * interface ring, then finally re-fill the rx ring with
1667 * the new-size buffers and restart.
1668 */
1669
1670 napi_disable(&mac->napi);
1671 netif_tx_disable(dev);
1672 pasemi_mac_intf_disable(mac);
1673
1674 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1675 pasemi_mac_pause_rxint(mac);
1676 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1677 pasemi_mac_free_rx_buffers(mac);
1678
1679 }
1680
1681 /* Setup checksum channels if large MTU and none already allocated */
1682 if (new_mtu > 1500 && !mac->num_cs) {
1683 pasemi_mac_setup_csrings(mac);
1684 if (!mac->num_cs) {
1685 ret = -ENOMEM;
1686 goto out;
1687 }
1688 }
1689
1690 /* Change maxf, i.e. what size frames are accepted.
1691 * Need room for ethernet header and CRC word
1692 */
1693 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG);
1694 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M;
1695 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4);
1696 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg);
1697
1698 dev->mtu = new_mtu;
1699 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1700 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1701
1702out:
1703 if (running) {
1704 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1705 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
1706
1707 rx_ring(mac)->next_to_fill = 0;
1708 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1);
1709
1710 napi_enable(&mac->napi);
1711 netif_start_queue(dev);
1712 pasemi_mac_intf_enable(mac);
1713 }
1714
1715 return ret;
1716}
1717
1718static const struct net_device_ops pasemi_netdev_ops = {
1719 .ndo_open = pasemi_mac_open,
1720 .ndo_stop = pasemi_mac_close,
1721 .ndo_start_xmit = pasemi_mac_start_tx,
1722 .ndo_set_multicast_list = pasemi_mac_set_rx_mode,
1723 .ndo_set_mac_address = pasemi_mac_set_mac_addr,
1724 .ndo_change_mtu = pasemi_mac_change_mtu,
1725 .ndo_validate_addr = eth_validate_addr,
1726#ifdef CONFIG_NET_POLL_CONTROLLER
1727 .ndo_poll_controller = pasemi_mac_netpoll,
1728#endif
1729};
1730
1731static int __devinit
1732pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1733{
1734 struct net_device *dev;
1735 struct pasemi_mac *mac;
1736 int err, ret;
1737
1738 err = pci_enable_device(pdev);
1739 if (err)
1740 return err;
1741
1742 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1743 if (dev == NULL) {
1744 dev_err(&pdev->dev,
1745 "pasemi_mac: Could not allocate ethernet device.\n");
1746 err = -ENOMEM;
1747 goto out_disable_device;
1748 }
1749
1750 pci_set_drvdata(pdev, dev);
1751 SET_NETDEV_DEV(dev, &pdev->dev);
1752
1753 mac = netdev_priv(dev);
1754
1755 mac->pdev = pdev;
1756 mac->netdev = dev;
1757
1758 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1759
1760 dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
1761 NETIF_F_HIGHDMA | NETIF_F_GSO;
1762
1763 mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
1764 mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1765 mac->lro_mgr.lro_arr = mac->lro_desc;
1766 mac->lro_mgr.get_skb_header = get_skb_hdr;
1767 mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1768 mac->lro_mgr.dev = mac->netdev;
1769 mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1770 mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1771
1772
1773 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1774 if (!mac->dma_pdev) {
1775 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1776 err = -ENODEV;
1777 goto out;
1778 }
1779
1780 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1781 if (!mac->iob_pdev) {
1782 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1783 err = -ENODEV;
1784 goto out;
1785 }
1786
1787 /* get mac addr from device tree */
1788 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1789 err = -ENODEV;
1790 goto out;
1791 }
1792 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1793
1794 ret = mac_to_intf(mac);
1795 if (ret < 0) {
1796 dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1797 err = -ENODEV;
1798 goto out;
1799 }
1800 mac->dma_if = ret;
1801
1802 switch (pdev->device) {
1803 case 0xa005:
1804 mac->type = MAC_TYPE_GMAC;
1805 break;
1806 case 0xa006:
1807 mac->type = MAC_TYPE_XAUI;
1808 break;
1809 default:
1810 err = -ENODEV;
1811 goto out;
1812 }
1813
1814 dev->netdev_ops = &pasemi_netdev_ops;
1815 dev->mtu = PE_DEF_MTU;
1816 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1817 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1818
1819 dev->ethtool_ops = &pasemi_mac_ethtool_ops;
1820
1821 if (err)
1822 goto out;
1823
1824 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1825
1826 /* Enable most messages by default */
1827 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1828
1829 err = register_netdev(dev);
1830
1831 if (err) {
1832 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1833 err);
1834 goto out;
1835 } else if netif_msg_probe(mac)
1836 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n",
1837 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1838 mac->dma_if, dev->dev_addr);
1839
1840 return err;
1841
1842out:
1843 if (mac->iob_pdev)
1844 pci_dev_put(mac->iob_pdev);
1845 if (mac->dma_pdev)
1846 pci_dev_put(mac->dma_pdev);
1847
1848 free_netdev(dev);
1849out_disable_device:
1850 pci_disable_device(pdev);
1851 return err;
1852
1853}
1854
1855static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1856{
1857 struct net_device *netdev = pci_get_drvdata(pdev);
1858 struct pasemi_mac *mac;
1859
1860 if (!netdev)
1861 return;
1862
1863 mac = netdev_priv(netdev);
1864
1865 unregister_netdev(netdev);
1866
1867 pci_disable_device(pdev);
1868 pci_dev_put(mac->dma_pdev);
1869 pci_dev_put(mac->iob_pdev);
1870
1871 pasemi_dma_free_chan(&mac->tx->chan);
1872 pasemi_dma_free_chan(&mac->rx->chan);
1873
1874 pci_set_drvdata(pdev, NULL);
1875 free_netdev(netdev);
1876}
1877
1878static DEFINE_PCI_DEVICE_TABLE(pasemi_mac_pci_tbl) = {
1879 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1880 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1881 { },
1882};
1883
1884MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1885
1886static struct pci_driver pasemi_mac_driver = {
1887 .name = "pasemi_mac",
1888 .id_table = pasemi_mac_pci_tbl,
1889 .probe = pasemi_mac_probe,
1890 .remove = __devexit_p(pasemi_mac_remove),
1891};
1892
1893static void __exit pasemi_mac_cleanup_module(void)
1894{
1895 pci_unregister_driver(&pasemi_mac_driver);
1896}
1897
1898int pasemi_mac_init_module(void)
1899{
1900 int err;
1901
1902 err = pasemi_dma_init();
1903 if (err)
1904 return err;
1905
1906 return pci_register_driver(&pasemi_mac_driver);
1907}
1908
1909module_init(pasemi_mac_init_module);
1910module_exit(pasemi_mac_cleanup_module);