1/*
  2 * Racal-Interlan ni5010 Ethernet definitions
  3 *
  4 * This is an extension to the Linux operating system, and is covered by the
  5 * same GNU General Public License that covers that work.
  6 *
  7 * copyrights (c) 1996 by Jan-Pascal van Best (jvbest@wi.leidenuniv.nl)
  8 *
  9 * I have done a look in the following sources:
 10 *   crynwr-packet-driver by Russ Nelson
 11 */
 12
 13#define NI5010_BUFSIZE	2048	/* number of bytes in a buffer */
 14
 15#define NI5010_MAGICVAL0 0x00  /* magic-values for ni5010 card */
 16#define NI5010_MAGICVAL1 0x55
 17#define NI5010_MAGICVAL2 0xAA
 18
 19#define SA_ADDR0 0x02
 20#define SA_ADDR1 0x07
 21#define SA_ADDR2 0x01
 22
 23/* The number of low I/O ports used by the ni5010 ethercard. */
 24#define NI5010_IO_EXTENT       32
 25
 26#define PRINTK(x) if (NI5010_DEBUG) printk x
 27#define PRINTK2(x) if (NI5010_DEBUG>=2) printk x
 28#define PRINTK3(x) if (NI5010_DEBUG>=3) printk x
 29
 30/* The various IE command registers */
 31#define EDLC_XSTAT	(ioaddr + 0x00)	/* EDLC transmit csr */
 32#define EDLC_XCLR	(ioaddr + 0x00)	/* EDLC transmit "Clear IRQ" */
 33#define EDLC_XMASK	(ioaddr + 0x01)	/* EDLC transmit "IRQ Masks" */
 34#define EDLC_RSTAT	(ioaddr + 0x02)	/* EDLC receive csr */
 35#define EDLC_RCLR	(ioaddr + 0x02)	/* EDLC receive "Clear IRQ" */
 36#define EDLC_RMASK	(ioaddr + 0x03)	/* EDLC receive "IRQ Masks" */
 37#define EDLC_XMODE	(ioaddr + 0x04)	/* EDLC transmit Mode */
 38#define EDLC_RMODE	(ioaddr + 0x05)	/* EDLC receive Mode */
 39#define EDLC_RESET	(ioaddr + 0x06)	/* EDLC RESET register */
 40#define EDLC_TDR1	(ioaddr + 0x07)	/* "Time Domain Reflectometry" reg1 */
 41#define EDLC_ADDR	(ioaddr + 0x08)	/* EDLC station address, 6 bytes */
 42	 			/* 0x0E doesn't exist for r/w */
 43#define EDLC_TDR2	(ioaddr + 0x0f)	/* "Time Domain Reflectometry" reg2 */
 44#define IE_GP		(ioaddr + 0x10)	/* GP pointer (word register) */
 45				/* 0x11 is 2nd byte of GP Pointer */
 46#define IE_RCNT		(ioaddr + 0x10)	/* Count of bytes in rcv'd packet */
 47 				/* 0x11 is 2nd byte of "Byte Count" */
 48#define IE_MMODE	(ioaddr + 0x12)	/* Memory Mode register */
 49#define IE_DMA_RST	(ioaddr + 0x13)	/* IE DMA Reset.  write only */
 50#define IE_ISTAT	(ioaddr + 0x13)	/* IE Interrupt Status.  read only */
 51#define IE_RBUF		(ioaddr + 0x14)	/* IE Receive Buffer port */
 52#define IE_XBUF		(ioaddr + 0x15)	/* IE Transmit Buffer port */
 53#define IE_SAPROM	(ioaddr + 0x16)	/* window on station addr prom */
 54#define IE_RESET	(ioaddr + 0x17)	/* any write causes Board Reset */
 55
 56/* bits in EDLC_XSTAT, interrupt clear on write, status when read */
 57#define XS_TPOK		0x80	/* transmit packet successful */
 58#define XS_CS		0x40	/* carrier sense */
 59#define XS_RCVD		0x20	/* transmitted packet received */
 60#define XS_SHORT	0x10	/* transmission media is shorted */
 61#define XS_UFLW		0x08	/* underflow.  iff failed board */
 62#define XS_COLL		0x04	/* collision occurred */
 63#define XS_16COLL	0x02	/* 16th collision occurred */
 64#define XS_PERR		0x01	/* parity error */
 65
 66#define XS_CLR_UFLW	0x08	/* clear underflow */
 67#define XS_CLR_COLL	0x04	/* clear collision */
 68#define XS_CLR_16COLL	0x02	/* clear 16th collision */
 69#define XS_CLR_PERR	0x01	/* clear parity error */
 70
 71/* bits in EDLC_XMASK, mask/enable transmit interrupts.  register is r/w */
 72#define XM_TPOK		0x80	/* =1 to enable Xmt Pkt OK interrupts */
 73#define XM_RCVD		0x20	/* =1 to enable Xmt Pkt Rcvd ints */
 74#define XM_UFLW		0x08	/* =1 to enable Xmt Underflow ints */
 75#define XM_COLL		0x04	/* =1 to enable Xmt Collision ints */
 76#define XM_COLL16	0x02	/* =1 to enable Xmt 16th Coll ints */
 77#define XM_PERR		0x01	/* =1 to enable Xmt Parity Error ints */
 78 				/* note: always clear this bit */
 79#define XM_ALL		(XM_TPOK | XM_RCVD | XM_UFLW | XM_COLL | XM_COLL16)
 80
 81/* bits in EDLC_RSTAT, interrupt clear on write, status when read */
 82#define RS_PKT_OK	0x80	/* received good packet */
 83#define RS_RST_PKT	0x10	/* RESET packet received */
 84#define RS_RUNT		0x08	/* Runt Pkt rcvd.  Len < 64 Bytes */
 85#define RS_ALIGN	0x04	/* Alignment error. not 8 bit aligned */
 86#define RS_CRC_ERR	0x02	/* Bad CRC on rcvd pkt */
 87#define RS_OFLW		0x01	/* overflow for rcv FIFO */
 88#define RS_VALID_BITS	( RS_PKT_OK | RS_RST_PKT | RS_RUNT | RS_ALIGN | RS_CRC_ERR | RS_OFLW )
 89 				/* all valid RSTAT bits */
 90
 91#define RS_CLR_PKT_OK	0x80	/* clear rcvd packet interrupt */
 92#define RS_CLR_RST_PKT	0x10	/* clear RESET packet received */
 93#define RS_CLR_RUNT	0x08	/* clear Runt Pckt received */
 94#define RS_CLR_ALIGN	0x04	/* clear Alignment error */
 95#define RS_CLR_CRC_ERR	0x02	/* clear CRC error */
 96#define RS_CLR_OFLW	0x01	/* clear rcv FIFO Overflow */
 97
 98/* bits in EDLC_RMASK, mask/enable receive interrupts.  register is r/w */
 99#define RM_PKT_OK	0x80	/* =1 to enable rcvd good packet ints */
100#define RM_RST_PKT	0x10	/* =1 to enable RESET packet ints */
101#define RM_RUNT		0x08	/* =1 to enable Runt Pkt rcvd ints */
102#define RM_ALIGN	0x04	/* =1 to enable Alignment error ints */
103#define RM_CRC_ERR	0x02	/* =1 to enable Bad CRC error ints */
104#define RM_OFLW		0x01	/* =1 to enable overflow error ints */
105
106/* bits in EDLC_RMODE, set Receive Packet mode.  register is r/w */
107#define RMD_TEST	0x80	/* =1 for Chip testing.  normally 0 */
108#define RMD_ADD_SIZ	0x10	/* =1 5-byte addr match.  normally 0 */
109#define RMD_EN_RUNT	0x08	/* =1 enable runt rcv.  normally 0 */
110#define RMD_EN_RST	0x04	/* =1 to rcv RESET pkt.  normally 0 */
111
112#define RMD_PROMISC	0x03	/* receive *all* packets.  unusual */
113#define RMD_MULTICAST	0x02	/* receive multicasts too.  unusual */
114#define RMD_BROADCAST	0x01	/* receive broadcasts & normal. usual */
115#define RMD_NO_PACKETS	0x00	/* don't receive any packets. unusual */
116
117/* bits in EDLC_XMODE, set Transmit Packet mode.  register is r/w */
118#define XMD_COLL_CNT	0xf0	/* coll's since success.  read-only */
119#define XMD_IG_PAR	0x08	/* =1 to ignore parity.  ALWAYS set */
120#define XMD_T_MODE	0x04	/* =1 to power xcvr. ALWAYS set this */
121#define XMD_LBC		0x02	/* =1 for loopbakc.  normally set */
122#define XMD_DIS_C	0x01	/* =1 disables contention. normally 0 */
123
124/* bits in EDLC_RESET, write only */
125#define RS_RESET	0x80	/* =1 to hold EDLC in reset state */
126
127/* bits in IE_MMODE, write only */
128#define MM_EN_DMA	0x80	/* =1 begin DMA xfer, Cplt clrs it */
129#define MM_EN_RCV	0x40	/* =1 allows Pkt rcv.  clr'd by rcv */
130#define MM_EN_XMT	0x20	/* =1 begin Xmt pkt.  Cplt clrs it */
131#define MM_BUS_PAGE	0x18	/* =00 ALWAYS.  Used when MUX=1 */
132#define MM_NET_PAGE	0x06	/* =00 ALWAYS.  Used when MUX=0 */
133#define MM_MUX		0x01	/* =1 means Rcv Buff on system bus */
134				/* =0 means Xmt Buff on system bus */
135
136/* bits in IE_ISTAT, read only */
137#define IS_TDIAG	0x80	/* =1 if Diagnostic problem */
138#define IS_EN_RCV	0x20	/* =1 until frame is rcv'd cplt */
139#define IS_EN_XMT	0x10	/* =1 until frame is xmt'd cplt */
140#define IS_EN_DMA	0x08	/* =1 until DMA is cplt or aborted */
141#define IS_DMA_INT	0x04	/* =0 iff DMA done interrupt. */
142#define IS_R_INT	0x02	/* =0 iff unmasked Rcv interrupt */
143#define IS_X_INT	0x01	/* =0 iff unmasked Xmt interrupt */
144