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1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
24
25
26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
28*/
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
50#include <linux/prefetch.h>
51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78static const int multicast_filter_limit = 100;
79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
84static int dspcfg_workaround = 1;
85
86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
111#define NATSEMI_TIMER_FREQ 5*HZ
112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
130static const char version[] __devinitconst =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
143module_param(dspcfg_workaround, int, 0);
144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
148MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
206receive and transmit paths which are synchronised using a combination of
207hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
208
209IVb. References
210
211http://www.scyld.com/expert/100mbps.html
212http://www.scyld.com/expert/NWay.html
213Datasheet is available from:
214http://www.national.com/pf/DP/DP83815.html
215
216IVc. Errata
217
218None characterised.
219*/
220
221
222
223/*
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
227 */
228#define PHYID_AM79C874 0x0022561b
229
230enum {
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
234};
235
236enum {
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
238};
239
240/* array of board data directly indexed by pci_tbl[x].driver_data */
241static struct {
242 const char *name;
243 unsigned long flags;
244 unsigned int eeprom_size;
245} natsemi_pci_info[] __devinitdata = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
248};
249
250static DEFINE_PCI_DEVICE_TABLE(natsemi_pci_tbl) = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { } /* terminate list */
254};
255MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
256
257/* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
260 device.
261*/
262enum register_offsets {
263 ChipCmd = 0x00,
264 ChipConfig = 0x04,
265 EECtrl = 0x08,
266 PCIBusCfg = 0x0C,
267 IntrStatus = 0x10,
268 IntrMask = 0x14,
269 IntrEnable = 0x18,
270 IntrHoldoff = 0x1C, /* DP83816 only */
271 TxRingPtr = 0x20,
272 TxConfig = 0x24,
273 RxRingPtr = 0x30,
274 RxConfig = 0x34,
275 ClkRun = 0x3C,
276 WOLCmd = 0x40,
277 PauseCmd = 0x44,
278 RxFilterAddr = 0x48,
279 RxFilterData = 0x4C,
280 BootRomAddr = 0x50,
281 BootRomData = 0x54,
282 SiliconRev = 0x58,
283 StatsCtrl = 0x5C,
284 StatsData = 0x60,
285 RxPktErrs = 0x60,
286 RxMissed = 0x68,
287 RxCRCErrs = 0x64,
288 BasicControl = 0x80,
289 BasicStatus = 0x84,
290 AnegAdv = 0x90,
291 AnegPeer = 0x94,
292 PhyStatus = 0xC0,
293 MIntrCtrl = 0xC4,
294 MIntrStatus = 0xC8,
295 PhyCtrl = 0xE4,
296
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
299 PGSEL = 0xCC,
300 PMDCSR = 0xE4,
301 TSTDAT = 0xFC,
302 DSPCFG = 0xF4,
303 SDCFG = 0xF8
304};
305/* the values for the 'magic' registers above (PGSEL=1) */
306#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307#define TSTDAT_VAL 0x0
308#define DSPCFG_VAL 0x5040
309#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
313
314/* misc PCI space registers */
315enum pci_register_offsets {
316 PCIPM = 0x44,
317};
318
319enum ChipCmd_bits {
320 ChipReset = 0x100,
321 RxReset = 0x20,
322 TxReset = 0x10,
323 RxOff = 0x08,
324 RxOn = 0x04,
325 TxOff = 0x02,
326 TxOn = 0x01,
327};
328
329enum ChipConfig_bits {
330 CfgPhyDis = 0x200,
331 CfgPhyRst = 0x400,
332 CfgExtPhy = 0x1000,
333 CfgAnegEnable = 0x2000,
334 CfgAneg100 = 0x4000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
340};
341
342enum EECtrl_bits {
343 EE_ShiftClk = 0x04,
344 EE_DataIn = 0x01,
345 EE_ChipSelect = 0x08,
346 EE_DataOut = 0x02,
347 MII_Data = 0x10,
348 MII_Write = 0x20,
349 MII_ShiftClk = 0x40,
350};
351
352enum PCIBusCfg_bits {
353 EepromReload = 0x4,
354};
355
356/* Bits in the interrupt status/mask registers. */
357enum IntrStatus_bits {
358 IntrRxDone = 0x0001,
359 IntrRxIntr = 0x0002,
360 IntrRxErr = 0x0004,
361 IntrRxEarly = 0x0008,
362 IntrRxIdle = 0x0010,
363 IntrRxOverrun = 0x0020,
364 IntrTxDone = 0x0040,
365 IntrTxIntr = 0x0080,
366 IntrTxErr = 0x0100,
367 IntrTxIdle = 0x0200,
368 IntrTxUnderrun = 0x0400,
369 StatsMax = 0x0800,
370 SWInt = 0x1000,
371 WOLPkt = 0x2000,
372 LinkChange = 0x4000,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
379};
380
381/*
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
389 */
390#define DEFAULT_INTR 0x00f1cd65
391
392enum TxConfig_bits {
393 TxDrthMask = 0x3f,
394 TxFlthMask = 0x3f00,
395 TxMxdmaMask = 0x700000,
396 TxMxdma_512 = 0x0,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
409};
410
411/*
412 * Tx Configuration:
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
420 *
421 */
422#define TX_FLTH_VAL ((512/32) << 8)
423#define TX_DRTH_VAL_START (64/32)
424#define TX_DRTH_VAL_INC 2
425#define TX_DRTH_VAL_LIMIT (1472/32)
426
427enum RxConfig_bits {
428 RxDrthMask = 0x3e,
429 RxMxdmaMask = 0x700000,
430 RxMxdma_512 = 0x0,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
442};
443#define RX_DRTH_VAL (128/8)
444
445enum ClkRun_bits {
446 PMEEnable = 0x100,
447 PMEStatus = 0x8000,
448};
449
450enum WolCmd_bits {
451 WakePhy = 0x1,
452 WakeUnicast = 0x2,
453 WakeMulticast = 0x4,
454 WakeBroadcast = 0x8,
455 WakeArp = 0x10,
456 WakePMatch0 = 0x20,
457 WakePMatch1 = 0x40,
458 WakePMatch2 = 0x80,
459 WakePMatch3 = 0x100,
460 WakeMagic = 0x200,
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
463 WokePhy = 0x400000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
467 WokeArp = 0x4000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
474};
475
476enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
484};
485
486enum StatsCtrl_bits {
487 StatsWarn = 0x1,
488 StatsFreeze = 0x2,
489 StatsClear = 0x4,
490 StatsStrobe = 0x8,
491};
492
493enum MIntrCtrl_bits {
494 MICRIntEn = 0x2,
495};
496
497enum PhyCtrl_bits {
498 PhyAddrMask = 0x1f,
499};
500
501#define PHY_ADDR_NONE 32
502#define PHY_ADDR_INTERNAL 1
503
504/* values we might find in the silicon revision register */
505#define SRR_DP83815_C 0x0302
506#define SRR_DP83815_D 0x0403
507#define SRR_DP83816_A4 0x0504
508#define SRR_DP83816_A5 0x0505
509
510/* The Rx and Tx buffer descriptors. */
511/* Note that using only 32 bit fields simplifies conversion to big-endian
512 architectures. */
513struct netdev_desc {
514 __le32 next_desc;
515 __le32 cmd_status;
516 __le32 addr;
517 __le32 software_use;
518};
519
520/* Bits in network_desc.status */
521enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
524 DescSizeMask=0xfff,
525
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
530
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
536};
537
538struct netdev_private {
539 /* Descriptor rings first for alignment */
540 dma_addr_t ring_dma;
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 struct napi_struct napi;
551 /* Media monitoring timer */
552 struct timer_list timer;
553 /* Frequently used values: keep some adjacent for cache effect */
554 struct pci_dev *pci_dev;
555 struct netdev_desc *rx_head_desc;
556 /* Producer/consumer ring indices */
557 unsigned int cur_rx, dirty_rx;
558 unsigned int cur_tx, dirty_tx;
559 /* Based on MTU+slack. */
560 unsigned int rx_buf_sz;
561 int oom;
562 /* Interrupt status */
563 u32 intr_status;
564 /* Do not touch the nic registers */
565 int hands_off;
566 /* Don't pay attention to the reported link state. */
567 int ignore_phy;
568 /* external phy that is used: only valid if dev->if_port != PORT_TP */
569 int mii;
570 int phy_addr_external;
571 unsigned int full_duplex;
572 /* Rx filter */
573 u32 cur_rx_mode;
574 u32 rx_filter[16];
575 /* FIFO and PCI burst thresholds */
576 u32 tx_config, rx_config;
577 /* original contents of ClkRun register */
578 u32 SavedClkRun;
579 /* silicon revision */
580 u32 srr;
581 /* expected DSPCFG value */
582 u16 dspcfg;
583 int dspcfg_workaround;
584 /* parms saved in ethtool format */
585 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
586 u8 duplex; /* Duplex, half or full */
587 u8 autoneg; /* Autonegotiation enabled */
588 /* MII transceiver section */
589 u16 advertising;
590 unsigned int iosize;
591 spinlock_t lock;
592 u32 msg_enable;
593 /* EEPROM data */
594 int eeprom_size;
595};
596
597static void move_int_phy(struct net_device *dev, int addr);
598static int eeprom_read(void __iomem *ioaddr, int location);
599static int mdio_read(struct net_device *dev, int reg);
600static void mdio_write(struct net_device *dev, int reg, u16 data);
601static void init_phy_fixup(struct net_device *dev);
602static int miiport_read(struct net_device *dev, int phy_id, int reg);
603static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
604static int find_mii(struct net_device *dev);
605static void natsemi_reset(struct net_device *dev);
606static void natsemi_reload_eeprom(struct net_device *dev);
607static void natsemi_stop_rxtx(struct net_device *dev);
608static int netdev_open(struct net_device *dev);
609static void do_cable_magic(struct net_device *dev);
610static void undo_cable_magic(struct net_device *dev);
611static void check_link(struct net_device *dev);
612static void netdev_timer(unsigned long data);
613static void dump_ring(struct net_device *dev);
614static void ns_tx_timeout(struct net_device *dev);
615static int alloc_ring(struct net_device *dev);
616static void refill_rx(struct net_device *dev);
617static void init_ring(struct net_device *dev);
618static void drain_tx(struct net_device *dev);
619static void drain_ring(struct net_device *dev);
620static void free_ring(struct net_device *dev);
621static void reinit_ring(struct net_device *dev);
622static void init_registers(struct net_device *dev);
623static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
624static irqreturn_t intr_handler(int irq, void *dev_instance);
625static void netdev_error(struct net_device *dev, int intr_status);
626static int natsemi_poll(struct napi_struct *napi, int budget);
627static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
628static void netdev_tx_done(struct net_device *dev);
629static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
630#ifdef CONFIG_NET_POLL_CONTROLLER
631static void natsemi_poll_controller(struct net_device *dev);
632#endif
633static void __set_rx_mode(struct net_device *dev);
634static void set_rx_mode(struct net_device *dev);
635static void __get_stats(struct net_device *dev);
636static struct net_device_stats *get_stats(struct net_device *dev);
637static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
638static int netdev_set_wol(struct net_device *dev, u32 newval);
639static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
640static int netdev_set_sopass(struct net_device *dev, u8 *newval);
641static int netdev_get_sopass(struct net_device *dev, u8 *data);
642static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
643static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644static void enable_wol_mode(struct net_device *dev, int enable_intr);
645static int netdev_close(struct net_device *dev);
646static int netdev_get_regs(struct net_device *dev, u8 *buf);
647static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
648static const struct ethtool_ops ethtool_ops;
649
650#define NATSEMI_ATTR(_name) \
651static ssize_t natsemi_show_##_name(struct device *dev, \
652 struct device_attribute *attr, char *buf); \
653 static ssize_t natsemi_set_##_name(struct device *dev, \
654 struct device_attribute *attr, \
655 const char *buf, size_t count); \
656 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
657
658#define NATSEMI_CREATE_FILE(_dev, _name) \
659 device_create_file(&_dev->dev, &dev_attr_##_name)
660#define NATSEMI_REMOVE_FILE(_dev, _name) \
661 device_remove_file(&_dev->dev, &dev_attr_##_name)
662
663NATSEMI_ATTR(dspcfg_workaround);
664
665static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
666 struct device_attribute *attr,
667 char *buf)
668{
669 struct netdev_private *np = netdev_priv(to_net_dev(dev));
670
671 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
672}
673
674static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
675 struct device_attribute *attr,
676 const char *buf, size_t count)
677{
678 struct netdev_private *np = netdev_priv(to_net_dev(dev));
679 int new_setting;
680 unsigned long flags;
681
682 /* Find out the new setting */
683 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
684 new_setting = 1;
685 else if (!strncmp("off", buf, count - 1) ||
686 !strncmp("0", buf, count - 1))
687 new_setting = 0;
688 else
689 return count;
690
691 spin_lock_irqsave(&np->lock, flags);
692
693 np->dspcfg_workaround = new_setting;
694
695 spin_unlock_irqrestore(&np->lock, flags);
696
697 return count;
698}
699
700static inline void __iomem *ns_ioaddr(struct net_device *dev)
701{
702 return (void __iomem *) dev->base_addr;
703}
704
705static inline void natsemi_irq_enable(struct net_device *dev)
706{
707 writel(1, ns_ioaddr(dev) + IntrEnable);
708 readl(ns_ioaddr(dev) + IntrEnable);
709}
710
711static inline void natsemi_irq_disable(struct net_device *dev)
712{
713 writel(0, ns_ioaddr(dev) + IntrEnable);
714 readl(ns_ioaddr(dev) + IntrEnable);
715}
716
717static void move_int_phy(struct net_device *dev, int addr)
718{
719 struct netdev_private *np = netdev_priv(dev);
720 void __iomem *ioaddr = ns_ioaddr(dev);
721 int target = 31;
722
723 /*
724 * The internal phy is visible on the external mii bus. Therefore we must
725 * move it away before we can send commands to an external phy.
726 * There are two addresses we must avoid:
727 * - the address on the external phy that is used for transmission.
728 * - the address that we want to access. User space can access phys
729 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the
730 * phy that is used for transmission.
731 */
732
733 if (target == addr)
734 target--;
735 if (target == np->phy_addr_external)
736 target--;
737 writew(target, ioaddr + PhyCtrl);
738 readw(ioaddr + PhyCtrl);
739 udelay(1);
740}
741
742static void __devinit natsemi_init_media (struct net_device *dev)
743{
744 struct netdev_private *np = netdev_priv(dev);
745 u32 tmp;
746
747 if (np->ignore_phy)
748 netif_carrier_on(dev);
749 else
750 netif_carrier_off(dev);
751
752 /* get the initial settings from hardware */
753 tmp = mdio_read(dev, MII_BMCR);
754 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
755 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
756 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
757 np->advertising= mdio_read(dev, MII_ADVERTISE);
758
759 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
760 netif_msg_probe(np)) {
761 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
762 "10%s %s duplex.\n",
763 pci_name(np->pci_dev),
764 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
765 "enabled, advertise" : "disabled, force",
766 (np->advertising &
767 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
768 "0" : "",
769 (np->advertising &
770 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
771 "full" : "half");
772 }
773 if (netif_msg_probe(np))
774 printk(KERN_INFO
775 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
776 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
777 np->advertising);
778
779}
780
781static const struct net_device_ops natsemi_netdev_ops = {
782 .ndo_open = netdev_open,
783 .ndo_stop = netdev_close,
784 .ndo_start_xmit = start_tx,
785 .ndo_get_stats = get_stats,
786 .ndo_set_multicast_list = set_rx_mode,
787 .ndo_change_mtu = natsemi_change_mtu,
788 .ndo_do_ioctl = netdev_ioctl,
789 .ndo_tx_timeout = ns_tx_timeout,
790 .ndo_set_mac_address = eth_mac_addr,
791 .ndo_validate_addr = eth_validate_addr,
792#ifdef CONFIG_NET_POLL_CONTROLLER
793 .ndo_poll_controller = natsemi_poll_controller,
794#endif
795};
796
797static int __devinit natsemi_probe1 (struct pci_dev *pdev,
798 const struct pci_device_id *ent)
799{
800 struct net_device *dev;
801 struct netdev_private *np;
802 int i, option, irq, chip_idx = ent->driver_data;
803 static int find_cnt = -1;
804 resource_size_t iostart;
805 unsigned long iosize;
806 void __iomem *ioaddr;
807 const int pcibar = 1; /* PCI base address register */
808 int prev_eedata;
809 u32 tmp;
810
811/* when built into the kernel, we only print version if device is found */
812#ifndef MODULE
813 static int printed_version;
814 if (!printed_version++)
815 printk(version);
816#endif
817
818 i = pci_enable_device(pdev);
819 if (i) return i;
820
821 /* natsemi has a non-standard PM control register
822 * in PCI config space. Some boards apparently need
823 * to be brought to D0 in this manner.
824 */
825 pci_read_config_dword(pdev, PCIPM, &tmp);
826 if (tmp & PCI_PM_CTRL_STATE_MASK) {
827 /* D0 state, disable PME assertion */
828 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
829 pci_write_config_dword(pdev, PCIPM, newtmp);
830 }
831
832 find_cnt++;
833 iostart = pci_resource_start(pdev, pcibar);
834 iosize = pci_resource_len(pdev, pcibar);
835 irq = pdev->irq;
836
837 pci_set_master(pdev);
838
839 dev = alloc_etherdev(sizeof (struct netdev_private));
840 if (!dev)
841 return -ENOMEM;
842 SET_NETDEV_DEV(dev, &pdev->dev);
843
844 i = pci_request_regions(pdev, DRV_NAME);
845 if (i)
846 goto err_pci_request_regions;
847
848 ioaddr = ioremap(iostart, iosize);
849 if (!ioaddr) {
850 i = -ENOMEM;
851 goto err_ioremap;
852 }
853
854 /* Work around the dropped serial bit. */
855 prev_eedata = eeprom_read(ioaddr, 6);
856 for (i = 0; i < 3; i++) {
857 int eedata = eeprom_read(ioaddr, i + 7);
858 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
859 dev->dev_addr[i*2+1] = eedata >> 7;
860 prev_eedata = eedata;
861 }
862
863 /* Store MAC Address in perm_addr */
864 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
865
866 dev->base_addr = (unsigned long __force) ioaddr;
867 dev->irq = irq;
868
869 np = netdev_priv(dev);
870 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
871 np->dev = dev;
872
873 np->pci_dev = pdev;
874 pci_set_drvdata(pdev, dev);
875 np->iosize = iosize;
876 spin_lock_init(&np->lock);
877 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
878 np->hands_off = 0;
879 np->intr_status = 0;
880 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
881 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
882 np->ignore_phy = 1;
883 else
884 np->ignore_phy = 0;
885 np->dspcfg_workaround = dspcfg_workaround;
886
887 /* Initial port:
888 * - If configured to ignore the PHY set up for external.
889 * - If the nic was configured to use an external phy and if find_mii
890 * finds a phy: use external port, first phy that replies.
891 * - Otherwise: internal port.
892 * Note that the phy address for the internal phy doesn't matter:
893 * The address would be used to access a phy over the mii bus, but
894 * the internal phy is accessed through mapped registers.
895 */
896 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
897 dev->if_port = PORT_MII;
898 else
899 dev->if_port = PORT_TP;
900 /* Reset the chip to erase previous misconfiguration. */
901 natsemi_reload_eeprom(dev);
902 natsemi_reset(dev);
903
904 if (dev->if_port != PORT_TP) {
905 np->phy_addr_external = find_mii(dev);
906 /* If we're ignoring the PHY it doesn't matter if we can't
907 * find one. */
908 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
909 dev->if_port = PORT_TP;
910 np->phy_addr_external = PHY_ADDR_INTERNAL;
911 }
912 } else {
913 np->phy_addr_external = PHY_ADDR_INTERNAL;
914 }
915
916 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
917 if (dev->mem_start)
918 option = dev->mem_start;
919
920 /* The lower four bits are the media type. */
921 if (option) {
922 if (option & 0x200)
923 np->full_duplex = 1;
924 if (option & 15)
925 printk(KERN_INFO
926 "natsemi %s: ignoring user supplied media type %d",
927 pci_name(np->pci_dev), option & 15);
928 }
929 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
930 np->full_duplex = 1;
931
932 dev->netdev_ops = &natsemi_netdev_ops;
933 dev->watchdog_timeo = TX_TIMEOUT;
934
935 SET_ETHTOOL_OPS(dev, ðtool_ops);
936
937 if (mtu)
938 dev->mtu = mtu;
939
940 natsemi_init_media(dev);
941
942 /* save the silicon revision for later querying */
943 np->srr = readl(ioaddr + SiliconRev);
944 if (netif_msg_hw(np))
945 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
946 pci_name(np->pci_dev), np->srr);
947
948 i = register_netdev(dev);
949 if (i)
950 goto err_register_netdev;
951
952 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
953 goto err_create_file;
954
955 if (netif_msg_drv(np)) {
956 printk(KERN_INFO "natsemi %s: %s at %#08llx "
957 "(%s), %pM, IRQ %d",
958 dev->name, natsemi_pci_info[chip_idx].name,
959 (unsigned long long)iostart, pci_name(np->pci_dev),
960 dev->dev_addr, irq);
961 if (dev->if_port == PORT_TP)
962 printk(", port TP.\n");
963 else if (np->ignore_phy)
964 printk(", port MII, ignoring PHY\n");
965 else
966 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
967 }
968 return 0;
969
970 err_create_file:
971 unregister_netdev(dev);
972
973 err_register_netdev:
974 iounmap(ioaddr);
975
976 err_ioremap:
977 pci_release_regions(pdev);
978 pci_set_drvdata(pdev, NULL);
979
980 err_pci_request_regions:
981 free_netdev(dev);
982 return i;
983}
984
985
986/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
987 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
988
989/* Delay between EEPROM clock transitions.
990 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
991 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
992 made udelay() unreliable.
993 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
994 deprecated.
995*/
996#define eeprom_delay(ee_addr) readl(ee_addr)
997
998#define EE_Write0 (EE_ChipSelect)
999#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1000
1001/* The EEPROM commands include the alway-set leading bit. */
1002enum EEPROM_Cmds {
1003 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1004};
1005
1006static int eeprom_read(void __iomem *addr, int location)
1007{
1008 int i;
1009 int retval = 0;
1010 void __iomem *ee_addr = addr + EECtrl;
1011 int read_cmd = location | EE_ReadCmd;
1012
1013 writel(EE_Write0, ee_addr);
1014
1015 /* Shift the read command bits out. */
1016 for (i = 10; i >= 0; i--) {
1017 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1018 writel(dataval, ee_addr);
1019 eeprom_delay(ee_addr);
1020 writel(dataval | EE_ShiftClk, ee_addr);
1021 eeprom_delay(ee_addr);
1022 }
1023 writel(EE_ChipSelect, ee_addr);
1024 eeprom_delay(ee_addr);
1025
1026 for (i = 0; i < 16; i++) {
1027 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1028 eeprom_delay(ee_addr);
1029 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1030 writel(EE_ChipSelect, ee_addr);
1031 eeprom_delay(ee_addr);
1032 }
1033
1034 /* Terminate the EEPROM access. */
1035 writel(EE_Write0, ee_addr);
1036 writel(0, ee_addr);
1037 return retval;
1038}
1039
1040/* MII transceiver control section.
1041 * The 83815 series has an internal transceiver, and we present the
1042 * internal management registers as if they were MII connected.
1043 * External Phy registers are referenced through the MII interface.
1044 */
1045
1046/* clock transitions >= 20ns (25MHz)
1047 * One readl should be good to PCI @ 100MHz
1048 */
1049#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1050
1051static int mii_getbit (struct net_device *dev)
1052{
1053 int data;
1054 void __iomem *ioaddr = ns_ioaddr(dev);
1055
1056 writel(MII_ShiftClk, ioaddr + EECtrl);
1057 data = readl(ioaddr + EECtrl);
1058 writel(0, ioaddr + EECtrl);
1059 mii_delay(ioaddr);
1060 return (data & MII_Data)? 1 : 0;
1061}
1062
1063static void mii_send_bits (struct net_device *dev, u32 data, int len)
1064{
1065 u32 i;
1066 void __iomem *ioaddr = ns_ioaddr(dev);
1067
1068 for (i = (1 << (len-1)); i; i >>= 1)
1069 {
1070 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1071 writel(mdio_val, ioaddr + EECtrl);
1072 mii_delay(ioaddr);
1073 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1074 mii_delay(ioaddr);
1075 }
1076 writel(0, ioaddr + EECtrl);
1077 mii_delay(ioaddr);
1078}
1079
1080static int miiport_read(struct net_device *dev, int phy_id, int reg)
1081{
1082 u32 cmd;
1083 int i;
1084 u32 retval = 0;
1085
1086 /* Ensure sync */
1087 mii_send_bits (dev, 0xffffffff, 32);
1088 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1089 /* ST,OP = 0110'b for read operation */
1090 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1091 mii_send_bits (dev, cmd, 14);
1092 /* Turnaround */
1093 if (mii_getbit (dev))
1094 return 0;
1095 /* Read data */
1096 for (i = 0; i < 16; i++) {
1097 retval <<= 1;
1098 retval |= mii_getbit (dev);
1099 }
1100 /* End cycle */
1101 mii_getbit (dev);
1102 return retval;
1103}
1104
1105static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1106{
1107 u32 cmd;
1108
1109 /* Ensure sync */
1110 mii_send_bits (dev, 0xffffffff, 32);
1111 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1112 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1113 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1114 mii_send_bits (dev, cmd, 32);
1115 /* End cycle */
1116 mii_getbit (dev);
1117}
1118
1119static int mdio_read(struct net_device *dev, int reg)
1120{
1121 struct netdev_private *np = netdev_priv(dev);
1122 void __iomem *ioaddr = ns_ioaddr(dev);
1123
1124 /* The 83815 series has two ports:
1125 * - an internal transceiver
1126 * - an external mii bus
1127 */
1128 if (dev->if_port == PORT_TP)
1129 return readw(ioaddr+BasicControl+(reg<<2));
1130 else
1131 return miiport_read(dev, np->phy_addr_external, reg);
1132}
1133
1134static void mdio_write(struct net_device *dev, int reg, u16 data)
1135{
1136 struct netdev_private *np = netdev_priv(dev);
1137 void __iomem *ioaddr = ns_ioaddr(dev);
1138
1139 /* The 83815 series has an internal transceiver; handle separately */
1140 if (dev->if_port == PORT_TP)
1141 writew(data, ioaddr+BasicControl+(reg<<2));
1142 else
1143 miiport_write(dev, np->phy_addr_external, reg, data);
1144}
1145
1146static void init_phy_fixup(struct net_device *dev)
1147{
1148 struct netdev_private *np = netdev_priv(dev);
1149 void __iomem *ioaddr = ns_ioaddr(dev);
1150 int i;
1151 u32 cfg;
1152 u16 tmp;
1153
1154 /* restore stuff lost when power was out */
1155 tmp = mdio_read(dev, MII_BMCR);
1156 if (np->autoneg == AUTONEG_ENABLE) {
1157 /* renegotiate if something changed */
1158 if ((tmp & BMCR_ANENABLE) == 0 ||
1159 np->advertising != mdio_read(dev, MII_ADVERTISE))
1160 {
1161 /* turn on autonegotiation and force negotiation */
1162 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1163 mdio_write(dev, MII_ADVERTISE, np->advertising);
1164 }
1165 } else {
1166 /* turn off auto negotiation, set speed and duplexity */
1167 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1168 if (np->speed == SPEED_100)
1169 tmp |= BMCR_SPEED100;
1170 if (np->duplex == DUPLEX_FULL)
1171 tmp |= BMCR_FULLDPLX;
1172 /*
1173 * Note: there is no good way to inform the link partner
1174 * that our capabilities changed. The user has to unplug
1175 * and replug the network cable after some changes, e.g.
1176 * after switching from 10HD, autoneg off to 100 HD,
1177 * autoneg off.
1178 */
1179 }
1180 mdio_write(dev, MII_BMCR, tmp);
1181 readl(ioaddr + ChipConfig);
1182 udelay(1);
1183
1184 /* find out what phy this is */
1185 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1186 + mdio_read(dev, MII_PHYSID2);
1187
1188 /* handle external phys here */
1189 switch (np->mii) {
1190 case PHYID_AM79C874:
1191 /* phy specific configuration for fibre/tp operation */
1192 tmp = mdio_read(dev, MII_MCTRL);
1193 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1194 if (dev->if_port == PORT_FIBRE)
1195 tmp |= MII_FX_SEL;
1196 else
1197 tmp |= MII_EN_SCRM;
1198 mdio_write(dev, MII_MCTRL, tmp);
1199 break;
1200 default:
1201 break;
1202 }
1203 cfg = readl(ioaddr + ChipConfig);
1204 if (cfg & CfgExtPhy)
1205 return;
1206
1207 /* On page 78 of the spec, they recommend some settings for "optimum
1208 performance" to be done in sequence. These settings optimize some
1209 of the 100Mbit autodetection circuitry. They say we only want to
1210 do this for rev C of the chip, but engineers at NSC (Bradley
1211 Kennedy) recommends always setting them. If you don't, you get
1212 errors on some autonegotiations that make the device unusable.
1213
1214 It seems that the DSP needs a few usec to reinitialize after
1215 the start of the phy. Just retry writing these values until they
1216 stick.
1217 */
1218 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1219
1220 int dspcfg;
1221 writew(1, ioaddr + PGSEL);
1222 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1223 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1224 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1225 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1226 writew(np->dspcfg, ioaddr + DSPCFG);
1227 writew(SDCFG_VAL, ioaddr + SDCFG);
1228 writew(0, ioaddr + PGSEL);
1229 readl(ioaddr + ChipConfig);
1230 udelay(10);
1231
1232 writew(1, ioaddr + PGSEL);
1233 dspcfg = readw(ioaddr + DSPCFG);
1234 writew(0, ioaddr + PGSEL);
1235 if (np->dspcfg == dspcfg)
1236 break;
1237 }
1238
1239 if (netif_msg_link(np)) {
1240 if (i==NATSEMI_HW_TIMEOUT) {
1241 printk(KERN_INFO
1242 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1243 dev->name, i*10);
1244 } else {
1245 printk(KERN_INFO
1246 "%s: DSPCFG accepted after %d usec.\n",
1247 dev->name, i*10);
1248 }
1249 }
1250 /*
1251 * Enable PHY Specific event based interrupts. Link state change
1252 * and Auto-Negotiation Completion are among the affected.
1253 * Read the intr status to clear it (needed for wake events).
1254 */
1255 readw(ioaddr + MIntrStatus);
1256 writew(MICRIntEn, ioaddr + MIntrCtrl);
1257}
1258
1259static int switch_port_external(struct net_device *dev)
1260{
1261 struct netdev_private *np = netdev_priv(dev);
1262 void __iomem *ioaddr = ns_ioaddr(dev);
1263 u32 cfg;
1264
1265 cfg = readl(ioaddr + ChipConfig);
1266 if (cfg & CfgExtPhy)
1267 return 0;
1268
1269 if (netif_msg_link(np)) {
1270 printk(KERN_INFO "%s: switching to external transceiver.\n",
1271 dev->name);
1272 }
1273
1274 /* 1) switch back to external phy */
1275 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1276 readl(ioaddr + ChipConfig);
1277 udelay(1);
1278
1279 /* 2) reset the external phy: */
1280 /* resetting the external PHY has been known to cause a hub supplying
1281 * power over Ethernet to kill the power. We don't want to kill
1282 * power to this computer, so we avoid resetting the phy.
1283 */
1284
1285 /* 3) reinit the phy fixup, it got lost during power down. */
1286 move_int_phy(dev, np->phy_addr_external);
1287 init_phy_fixup(dev);
1288
1289 return 1;
1290}
1291
1292static int switch_port_internal(struct net_device *dev)
1293{
1294 struct netdev_private *np = netdev_priv(dev);
1295 void __iomem *ioaddr = ns_ioaddr(dev);
1296 int i;
1297 u32 cfg;
1298 u16 bmcr;
1299
1300 cfg = readl(ioaddr + ChipConfig);
1301 if (!(cfg &CfgExtPhy))
1302 return 0;
1303
1304 if (netif_msg_link(np)) {
1305 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1306 dev->name);
1307 }
1308 /* 1) switch back to internal phy: */
1309 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1310 writel(cfg, ioaddr + ChipConfig);
1311 readl(ioaddr + ChipConfig);
1312 udelay(1);
1313
1314 /* 2) reset the internal phy: */
1315 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1316 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1317 readl(ioaddr + ChipConfig);
1318 udelay(10);
1319 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1320 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1321 if (!(bmcr & BMCR_RESET))
1322 break;
1323 udelay(10);
1324 }
1325 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1326 printk(KERN_INFO
1327 "%s: phy reset did not complete in %d usec.\n",
1328 dev->name, i*10);
1329 }
1330 /* 3) reinit the phy fixup, it got lost during power down. */
1331 init_phy_fixup(dev);
1332
1333 return 1;
1334}
1335
1336/* Scan for a PHY on the external mii bus.
1337 * There are two tricky points:
1338 * - Do not scan while the internal phy is enabled. The internal phy will
1339 * crash: e.g. reads from the DSPCFG register will return odd values and
1340 * the nasty random phy reset code will reset the nic every few seconds.
1341 * - The internal phy must be moved around, an external phy could
1342 * have the same address as the internal phy.
1343 */
1344static int find_mii(struct net_device *dev)
1345{
1346 struct netdev_private *np = netdev_priv(dev);
1347 int tmp;
1348 int i;
1349 int did_switch;
1350
1351 /* Switch to external phy */
1352 did_switch = switch_port_external(dev);
1353
1354 /* Scan the possible phy addresses:
1355 *
1356 * PHY address 0 means that the phy is in isolate mode. Not yet
1357 * supported due to lack of test hardware. User space should
1358 * handle it through ethtool.
1359 */
1360 for (i = 1; i <= 31; i++) {
1361 move_int_phy(dev, i);
1362 tmp = miiport_read(dev, i, MII_BMSR);
1363 if (tmp != 0xffff && tmp != 0x0000) {
1364 /* found something! */
1365 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1366 + mdio_read(dev, MII_PHYSID2);
1367 if (netif_msg_probe(np)) {
1368 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1369 pci_name(np->pci_dev), np->mii, i);
1370 }
1371 break;
1372 }
1373 }
1374 /* And switch back to internal phy: */
1375 if (did_switch)
1376 switch_port_internal(dev);
1377 return i;
1378}
1379
1380/* CFG bits [13:16] [18:23] */
1381#define CFG_RESET_SAVE 0xfde000
1382/* WCSR bits [0:4] [9:10] */
1383#define WCSR_RESET_SAVE 0x61f
1384/* RFCR bits [20] [22] [27:31] */
1385#define RFCR_RESET_SAVE 0xf8500000
1386
1387static void natsemi_reset(struct net_device *dev)
1388{
1389 int i;
1390 u32 cfg;
1391 u32 wcsr;
1392 u32 rfcr;
1393 u16 pmatch[3];
1394 u16 sopass[3];
1395 struct netdev_private *np = netdev_priv(dev);
1396 void __iomem *ioaddr = ns_ioaddr(dev);
1397
1398 /*
1399 * Resetting the chip causes some registers to be lost.
1400 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1401 * we save the state that would have been loaded from EEPROM
1402 * on a normal power-up (see the spec EEPROM map). This assumes
1403 * whoever calls this will follow up with init_registers() eventually.
1404 */
1405
1406 /* CFG */
1407 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1408 /* WCSR */
1409 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1410 /* RFCR */
1411 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1412 /* PMATCH */
1413 for (i = 0; i < 3; i++) {
1414 writel(i*2, ioaddr + RxFilterAddr);
1415 pmatch[i] = readw(ioaddr + RxFilterData);
1416 }
1417 /* SOPAS */
1418 for (i = 0; i < 3; i++) {
1419 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1420 sopass[i] = readw(ioaddr + RxFilterData);
1421 }
1422
1423 /* now whack the chip */
1424 writel(ChipReset, ioaddr + ChipCmd);
1425 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1426 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1427 break;
1428 udelay(5);
1429 }
1430 if (i==NATSEMI_HW_TIMEOUT) {
1431 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1432 dev->name, i*5);
1433 } else if (netif_msg_hw(np)) {
1434 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1435 dev->name, i*5);
1436 }
1437
1438 /* restore CFG */
1439 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1440 /* turn on external phy if it was selected */
1441 if (dev->if_port == PORT_TP)
1442 cfg &= ~(CfgExtPhy | CfgPhyDis);
1443 else
1444 cfg |= (CfgExtPhy | CfgPhyDis);
1445 writel(cfg, ioaddr + ChipConfig);
1446 /* restore WCSR */
1447 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1448 writel(wcsr, ioaddr + WOLCmd);
1449 /* read RFCR */
1450 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1451 /* restore PMATCH */
1452 for (i = 0; i < 3; i++) {
1453 writel(i*2, ioaddr + RxFilterAddr);
1454 writew(pmatch[i], ioaddr + RxFilterData);
1455 }
1456 for (i = 0; i < 3; i++) {
1457 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1458 writew(sopass[i], ioaddr + RxFilterData);
1459 }
1460 /* restore RFCR */
1461 writel(rfcr, ioaddr + RxFilterAddr);
1462}
1463
1464static void reset_rx(struct net_device *dev)
1465{
1466 int i;
1467 struct netdev_private *np = netdev_priv(dev);
1468 void __iomem *ioaddr = ns_ioaddr(dev);
1469
1470 np->intr_status &= ~RxResetDone;
1471
1472 writel(RxReset, ioaddr + ChipCmd);
1473
1474 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1475 np->intr_status |= readl(ioaddr + IntrStatus);
1476 if (np->intr_status & RxResetDone)
1477 break;
1478 udelay(15);
1479 }
1480 if (i==NATSEMI_HW_TIMEOUT) {
1481 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1482 dev->name, i*15);
1483 } else if (netif_msg_hw(np)) {
1484 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1485 dev->name, i*15);
1486 }
1487}
1488
1489static void natsemi_reload_eeprom(struct net_device *dev)
1490{
1491 struct netdev_private *np = netdev_priv(dev);
1492 void __iomem *ioaddr = ns_ioaddr(dev);
1493 int i;
1494
1495 writel(EepromReload, ioaddr + PCIBusCfg);
1496 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1497 udelay(50);
1498 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1499 break;
1500 }
1501 if (i==NATSEMI_HW_TIMEOUT) {
1502 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1503 pci_name(np->pci_dev), i*50);
1504 } else if (netif_msg_hw(np)) {
1505 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1506 pci_name(np->pci_dev), i*50);
1507 }
1508}
1509
1510static void natsemi_stop_rxtx(struct net_device *dev)
1511{
1512 void __iomem * ioaddr = ns_ioaddr(dev);
1513 struct netdev_private *np = netdev_priv(dev);
1514 int i;
1515
1516 writel(RxOff | TxOff, ioaddr + ChipCmd);
1517 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1518 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1519 break;
1520 udelay(5);
1521 }
1522 if (i==NATSEMI_HW_TIMEOUT) {
1523 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1524 dev->name, i*5);
1525 } else if (netif_msg_hw(np)) {
1526 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1527 dev->name, i*5);
1528 }
1529}
1530
1531static int netdev_open(struct net_device *dev)
1532{
1533 struct netdev_private *np = netdev_priv(dev);
1534 void __iomem * ioaddr = ns_ioaddr(dev);
1535 int i;
1536
1537 /* Reset the chip, just in case. */
1538 natsemi_reset(dev);
1539
1540 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1541 if (i) return i;
1542
1543 if (netif_msg_ifup(np))
1544 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1545 dev->name, dev->irq);
1546 i = alloc_ring(dev);
1547 if (i < 0) {
1548 free_irq(dev->irq, dev);
1549 return i;
1550 }
1551 napi_enable(&np->napi);
1552
1553 init_ring(dev);
1554 spin_lock_irq(&np->lock);
1555 init_registers(dev);
1556 /* now set the MAC address according to dev->dev_addr */
1557 for (i = 0; i < 3; i++) {
1558 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1559
1560 writel(i*2, ioaddr + RxFilterAddr);
1561 writew(mac, ioaddr + RxFilterData);
1562 }
1563 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1564 spin_unlock_irq(&np->lock);
1565
1566 netif_start_queue(dev);
1567
1568 if (netif_msg_ifup(np))
1569 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1570 dev->name, (int)readl(ioaddr + ChipCmd));
1571
1572 /* Set the timer to check for link beat. */
1573 init_timer(&np->timer);
1574 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1575 np->timer.data = (unsigned long)dev;
1576 np->timer.function = netdev_timer; /* timer handler */
1577 add_timer(&np->timer);
1578
1579 return 0;
1580}
1581
1582static void do_cable_magic(struct net_device *dev)
1583{
1584 struct netdev_private *np = netdev_priv(dev);
1585 void __iomem *ioaddr = ns_ioaddr(dev);
1586
1587 if (dev->if_port != PORT_TP)
1588 return;
1589
1590 if (np->srr >= SRR_DP83816_A5)
1591 return;
1592
1593 /*
1594 * 100 MBit links with short cables can trip an issue with the chip.
1595 * The problem manifests as lots of CRC errors and/or flickering
1596 * activity LED while idle. This process is based on instructions
1597 * from engineers at National.
1598 */
1599 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1600 u16 data;
1601
1602 writew(1, ioaddr + PGSEL);
1603 /*
1604 * coefficient visibility should already be enabled via
1605 * DSPCFG | 0x1000
1606 */
1607 data = readw(ioaddr + TSTDAT) & 0xff;
1608 /*
1609 * the value must be negative, and within certain values
1610 * (these values all come from National)
1611 */
1612 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1613 np = netdev_priv(dev);
1614
1615 /* the bug has been triggered - fix the coefficient */
1616 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1617 /* lock the value */
1618 data = readw(ioaddr + DSPCFG);
1619 np->dspcfg = data | DSPCFG_LOCK;
1620 writew(np->dspcfg, ioaddr + DSPCFG);
1621 }
1622 writew(0, ioaddr + PGSEL);
1623 }
1624}
1625
1626static void undo_cable_magic(struct net_device *dev)
1627{
1628 u16 data;
1629 struct netdev_private *np = netdev_priv(dev);
1630 void __iomem * ioaddr = ns_ioaddr(dev);
1631
1632 if (dev->if_port != PORT_TP)
1633 return;
1634
1635 if (np->srr >= SRR_DP83816_A5)
1636 return;
1637
1638 writew(1, ioaddr + PGSEL);
1639 /* make sure the lock bit is clear */
1640 data = readw(ioaddr + DSPCFG);
1641 np->dspcfg = data & ~DSPCFG_LOCK;
1642 writew(np->dspcfg, ioaddr + DSPCFG);
1643 writew(0, ioaddr + PGSEL);
1644}
1645
1646static void check_link(struct net_device *dev)
1647{
1648 struct netdev_private *np = netdev_priv(dev);
1649 void __iomem * ioaddr = ns_ioaddr(dev);
1650 int duplex = np->duplex;
1651 u16 bmsr;
1652
1653 /* If we are ignoring the PHY then don't try reading it. */
1654 if (np->ignore_phy)
1655 goto propagate_state;
1656
1657 /* The link status field is latched: it remains low after a temporary
1658 * link failure until it's read. We need the current link status,
1659 * thus read twice.
1660 */
1661 mdio_read(dev, MII_BMSR);
1662 bmsr = mdio_read(dev, MII_BMSR);
1663
1664 if (!(bmsr & BMSR_LSTATUS)) {
1665 if (netif_carrier_ok(dev)) {
1666 if (netif_msg_link(np))
1667 printk(KERN_NOTICE "%s: link down.\n",
1668 dev->name);
1669 netif_carrier_off(dev);
1670 undo_cable_magic(dev);
1671 }
1672 return;
1673 }
1674 if (!netif_carrier_ok(dev)) {
1675 if (netif_msg_link(np))
1676 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1677 netif_carrier_on(dev);
1678 do_cable_magic(dev);
1679 }
1680
1681 duplex = np->full_duplex;
1682 if (!duplex) {
1683 if (bmsr & BMSR_ANEGCOMPLETE) {
1684 int tmp = mii_nway_result(
1685 np->advertising & mdio_read(dev, MII_LPA));
1686 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1687 duplex = 1;
1688 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1689 duplex = 1;
1690 }
1691
1692propagate_state:
1693 /* if duplex is set then bit 28 must be set, too */
1694 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1695 if (netif_msg_link(np))
1696 printk(KERN_INFO
1697 "%s: Setting %s-duplex based on negotiated "
1698 "link capability.\n", dev->name,
1699 duplex ? "full" : "half");
1700 if (duplex) {
1701 np->rx_config |= RxAcceptTx;
1702 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1703 } else {
1704 np->rx_config &= ~RxAcceptTx;
1705 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1706 }
1707 writel(np->tx_config, ioaddr + TxConfig);
1708 writel(np->rx_config, ioaddr + RxConfig);
1709 }
1710}
1711
1712static void init_registers(struct net_device *dev)
1713{
1714 struct netdev_private *np = netdev_priv(dev);
1715 void __iomem * ioaddr = ns_ioaddr(dev);
1716
1717 init_phy_fixup(dev);
1718
1719 /* clear any interrupts that are pending, such as wake events */
1720 readl(ioaddr + IntrStatus);
1721
1722 writel(np->ring_dma, ioaddr + RxRingPtr);
1723 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1724 ioaddr + TxRingPtr);
1725
1726 /* Initialize other registers.
1727 * Configure the PCI bus bursts and FIFO thresholds.
1728 * Configure for standard, in-spec Ethernet.
1729 * Start with half-duplex. check_link will update
1730 * to the correct settings.
1731 */
1732
1733 /* DRTH: 2: start tx if 64 bytes are in the fifo
1734 * FLTH: 0x10: refill with next packet if 512 bytes are free
1735 * MXDMA: 0: up to 256 byte bursts.
1736 * MXDMA must be <= FLTH
1737 * ECRETRY=1
1738 * ATP=1
1739 */
1740 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1741 TX_FLTH_VAL | TX_DRTH_VAL_START;
1742 writel(np->tx_config, ioaddr + TxConfig);
1743
1744 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1745 * MXDMA 0: up to 256 byte bursts
1746 */
1747 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1748 /* if receive ring now has bigger buffers than normal, enable jumbo */
1749 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1750 np->rx_config |= RxAcceptLong;
1751
1752 writel(np->rx_config, ioaddr + RxConfig);
1753
1754 /* Disable PME:
1755 * The PME bit is initialized from the EEPROM contents.
1756 * PCI cards probably have PME disabled, but motherboard
1757 * implementations may have PME set to enable WakeOnLan.
1758 * With PME set the chip will scan incoming packets but
1759 * nothing will be written to memory. */
1760 np->SavedClkRun = readl(ioaddr + ClkRun);
1761 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1762 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1763 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1764 dev->name, readl(ioaddr + WOLCmd));
1765 }
1766
1767 check_link(dev);
1768 __set_rx_mode(dev);
1769
1770 /* Enable interrupts by setting the interrupt mask. */
1771 writel(DEFAULT_INTR, ioaddr + IntrMask);
1772 natsemi_irq_enable(dev);
1773
1774 writel(RxOn | TxOn, ioaddr + ChipCmd);
1775 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1776}
1777
1778/*
1779 * netdev_timer:
1780 * Purpose:
1781 * 1) check for link changes. Usually they are handled by the MII interrupt
1782 * but it doesn't hurt to check twice.
1783 * 2) check for sudden death of the NIC:
1784 * It seems that a reference set for this chip went out with incorrect info,
1785 * and there exist boards that aren't quite right. An unexpected voltage
1786 * drop can cause the PHY to get itself in a weird state (basically reset).
1787 * NOTE: this only seems to affect revC chips. The user can disable
1788 * this check via dspcfg_workaround sysfs option.
1789 * 3) check of death of the RX path due to OOM
1790 */
1791static void netdev_timer(unsigned long data)
1792{
1793 struct net_device *dev = (struct net_device *)data;
1794 struct netdev_private *np = netdev_priv(dev);
1795 void __iomem * ioaddr = ns_ioaddr(dev);
1796 int next_tick = NATSEMI_TIMER_FREQ;
1797
1798 if (netif_msg_timer(np)) {
1799 /* DO NOT read the IntrStatus register,
1800 * a read clears any pending interrupts.
1801 */
1802 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1803 dev->name);
1804 }
1805
1806 if (dev->if_port == PORT_TP) {
1807 u16 dspcfg;
1808
1809 spin_lock_irq(&np->lock);
1810 /* check for a nasty random phy-reset - use dspcfg as a flag */
1811 writew(1, ioaddr+PGSEL);
1812 dspcfg = readw(ioaddr+DSPCFG);
1813 writew(0, ioaddr+PGSEL);
1814 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1815 if (!netif_queue_stopped(dev)) {
1816 spin_unlock_irq(&np->lock);
1817 if (netif_msg_drv(np))
1818 printk(KERN_NOTICE "%s: possible phy reset: "
1819 "re-initializing\n", dev->name);
1820 disable_irq(dev->irq);
1821 spin_lock_irq(&np->lock);
1822 natsemi_stop_rxtx(dev);
1823 dump_ring(dev);
1824 reinit_ring(dev);
1825 init_registers(dev);
1826 spin_unlock_irq(&np->lock);
1827 enable_irq(dev->irq);
1828 } else {
1829 /* hurry back */
1830 next_tick = HZ;
1831 spin_unlock_irq(&np->lock);
1832 }
1833 } else {
1834 /* init_registers() calls check_link() for the above case */
1835 check_link(dev);
1836 spin_unlock_irq(&np->lock);
1837 }
1838 } else {
1839 spin_lock_irq(&np->lock);
1840 check_link(dev);
1841 spin_unlock_irq(&np->lock);
1842 }
1843 if (np->oom) {
1844 disable_irq(dev->irq);
1845 np->oom = 0;
1846 refill_rx(dev);
1847 enable_irq(dev->irq);
1848 if (!np->oom) {
1849 writel(RxOn, ioaddr + ChipCmd);
1850 } else {
1851 next_tick = 1;
1852 }
1853 }
1854
1855 if (next_tick > 1)
1856 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1857 else
1858 mod_timer(&np->timer, jiffies + next_tick);
1859}
1860
1861static void dump_ring(struct net_device *dev)
1862{
1863 struct netdev_private *np = netdev_priv(dev);
1864
1865 if (netif_msg_pktdata(np)) {
1866 int i;
1867 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1868 for (i = 0; i < TX_RING_SIZE; i++) {
1869 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1870 i, np->tx_ring[i].next_desc,
1871 np->tx_ring[i].cmd_status,
1872 np->tx_ring[i].addr);
1873 }
1874 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1875 for (i = 0; i < RX_RING_SIZE; i++) {
1876 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1877 i, np->rx_ring[i].next_desc,
1878 np->rx_ring[i].cmd_status,
1879 np->rx_ring[i].addr);
1880 }
1881 }
1882}
1883
1884static void ns_tx_timeout(struct net_device *dev)
1885{
1886 struct netdev_private *np = netdev_priv(dev);
1887 void __iomem * ioaddr = ns_ioaddr(dev);
1888
1889 disable_irq(dev->irq);
1890 spin_lock_irq(&np->lock);
1891 if (!np->hands_off) {
1892 if (netif_msg_tx_err(np))
1893 printk(KERN_WARNING
1894 "%s: Transmit timed out, status %#08x,"
1895 " resetting...\n",
1896 dev->name, readl(ioaddr + IntrStatus));
1897 dump_ring(dev);
1898
1899 natsemi_reset(dev);
1900 reinit_ring(dev);
1901 init_registers(dev);
1902 } else {
1903 printk(KERN_WARNING
1904 "%s: tx_timeout while in hands_off state?\n",
1905 dev->name);
1906 }
1907 spin_unlock_irq(&np->lock);
1908 enable_irq(dev->irq);
1909
1910 dev->trans_start = jiffies; /* prevent tx timeout */
1911 dev->stats.tx_errors++;
1912 netif_wake_queue(dev);
1913}
1914
1915static int alloc_ring(struct net_device *dev)
1916{
1917 struct netdev_private *np = netdev_priv(dev);
1918 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1919 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1920 &np->ring_dma);
1921 if (!np->rx_ring)
1922 return -ENOMEM;
1923 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1924 return 0;
1925}
1926
1927static void refill_rx(struct net_device *dev)
1928{
1929 struct netdev_private *np = netdev_priv(dev);
1930
1931 /* Refill the Rx ring buffers. */
1932 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1933 struct sk_buff *skb;
1934 int entry = np->dirty_rx % RX_RING_SIZE;
1935 if (np->rx_skbuff[entry] == NULL) {
1936 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1937 skb = dev_alloc_skb(buflen);
1938 np->rx_skbuff[entry] = skb;
1939 if (skb == NULL)
1940 break; /* Better luck next round. */
1941 skb->dev = dev; /* Mark as being used by this device. */
1942 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1943 skb->data, buflen, PCI_DMA_FROMDEVICE);
1944 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1945 }
1946 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1947 }
1948 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1949 if (netif_msg_rx_err(np))
1950 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1951 np->oom = 1;
1952 }
1953}
1954
1955static void set_bufsize(struct net_device *dev)
1956{
1957 struct netdev_private *np = netdev_priv(dev);
1958 if (dev->mtu <= ETH_DATA_LEN)
1959 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1960 else
1961 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1962}
1963
1964/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1965static void init_ring(struct net_device *dev)
1966{
1967 struct netdev_private *np = netdev_priv(dev);
1968 int i;
1969
1970 /* 1) TX ring */
1971 np->dirty_tx = np->cur_tx = 0;
1972 for (i = 0; i < TX_RING_SIZE; i++) {
1973 np->tx_skbuff[i] = NULL;
1974 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1975 +sizeof(struct netdev_desc)
1976 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1977 np->tx_ring[i].cmd_status = 0;
1978 }
1979
1980 /* 2) RX ring */
1981 np->dirty_rx = 0;
1982 np->cur_rx = RX_RING_SIZE;
1983 np->oom = 0;
1984 set_bufsize(dev);
1985
1986 np->rx_head_desc = &np->rx_ring[0];
1987
1988 /* Please be careful before changing this loop - at least gcc-2.95.1
1989 * miscompiles it otherwise.
1990 */
1991 /* Initialize all Rx descriptors. */
1992 for (i = 0; i < RX_RING_SIZE; i++) {
1993 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1994 +sizeof(struct netdev_desc)
1995 *((i+1)%RX_RING_SIZE));
1996 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1997 np->rx_skbuff[i] = NULL;
1998 }
1999 refill_rx(dev);
2000 dump_ring(dev);
2001}
2002
2003static void drain_tx(struct net_device *dev)
2004{
2005 struct netdev_private *np = netdev_priv(dev);
2006 int i;
2007
2008 for (i = 0; i < TX_RING_SIZE; i++) {
2009 if (np->tx_skbuff[i]) {
2010 pci_unmap_single(np->pci_dev,
2011 np->tx_dma[i], np->tx_skbuff[i]->len,
2012 PCI_DMA_TODEVICE);
2013 dev_kfree_skb(np->tx_skbuff[i]);
2014 dev->stats.tx_dropped++;
2015 }
2016 np->tx_skbuff[i] = NULL;
2017 }
2018}
2019
2020static void drain_rx(struct net_device *dev)
2021{
2022 struct netdev_private *np = netdev_priv(dev);
2023 unsigned int buflen = np->rx_buf_sz;
2024 int i;
2025
2026 /* Free all the skbuffs in the Rx queue. */
2027 for (i = 0; i < RX_RING_SIZE; i++) {
2028 np->rx_ring[i].cmd_status = 0;
2029 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
2030 if (np->rx_skbuff[i]) {
2031 pci_unmap_single(np->pci_dev, np->rx_dma[i],
2032 buflen + NATSEMI_PADDING,
2033 PCI_DMA_FROMDEVICE);
2034 dev_kfree_skb(np->rx_skbuff[i]);
2035 }
2036 np->rx_skbuff[i] = NULL;
2037 }
2038}
2039
2040static void drain_ring(struct net_device *dev)
2041{
2042 drain_rx(dev);
2043 drain_tx(dev);
2044}
2045
2046static void free_ring(struct net_device *dev)
2047{
2048 struct netdev_private *np = netdev_priv(dev);
2049 pci_free_consistent(np->pci_dev,
2050 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2051 np->rx_ring, np->ring_dma);
2052}
2053
2054static void reinit_rx(struct net_device *dev)
2055{
2056 struct netdev_private *np = netdev_priv(dev);
2057 int i;
2058
2059 /* RX Ring */
2060 np->dirty_rx = 0;
2061 np->cur_rx = RX_RING_SIZE;
2062 np->rx_head_desc = &np->rx_ring[0];
2063 /* Initialize all Rx descriptors. */
2064 for (i = 0; i < RX_RING_SIZE; i++)
2065 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2066
2067 refill_rx(dev);
2068}
2069
2070static void reinit_ring(struct net_device *dev)
2071{
2072 struct netdev_private *np = netdev_priv(dev);
2073 int i;
2074
2075 /* drain TX ring */
2076 drain_tx(dev);
2077 np->dirty_tx = np->cur_tx = 0;
2078 for (i=0;i<TX_RING_SIZE;i++)
2079 np->tx_ring[i].cmd_status = 0;
2080
2081 reinit_rx(dev);
2082}
2083
2084static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2085{
2086 struct netdev_private *np = netdev_priv(dev);
2087 void __iomem * ioaddr = ns_ioaddr(dev);
2088 unsigned entry;
2089 unsigned long flags;
2090
2091 /* Note: Ordering is important here, set the field with the
2092 "ownership" bit last, and only then increment cur_tx. */
2093
2094 /* Calculate the next Tx descriptor entry. */
2095 entry = np->cur_tx % TX_RING_SIZE;
2096
2097 np->tx_skbuff[entry] = skb;
2098 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2099 skb->data,skb->len, PCI_DMA_TODEVICE);
2100
2101 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2102
2103 spin_lock_irqsave(&np->lock, flags);
2104
2105 if (!np->hands_off) {
2106 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2107 /* StrongARM: Explicitly cache flush np->tx_ring and
2108 * skb->data,skb->len. */
2109 wmb();
2110 np->cur_tx++;
2111 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2112 netdev_tx_done(dev);
2113 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2114 netif_stop_queue(dev);
2115 }
2116 /* Wake the potentially-idle transmit channel. */
2117 writel(TxOn, ioaddr + ChipCmd);
2118 } else {
2119 dev_kfree_skb_irq(skb);
2120 dev->stats.tx_dropped++;
2121 }
2122 spin_unlock_irqrestore(&np->lock, flags);
2123
2124 if (netif_msg_tx_queued(np)) {
2125 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2126 dev->name, np->cur_tx, entry);
2127 }
2128 return NETDEV_TX_OK;
2129}
2130
2131static void netdev_tx_done(struct net_device *dev)
2132{
2133 struct netdev_private *np = netdev_priv(dev);
2134
2135 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2136 int entry = np->dirty_tx % TX_RING_SIZE;
2137 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2138 break;
2139 if (netif_msg_tx_done(np))
2140 printk(KERN_DEBUG
2141 "%s: tx frame #%d finished, status %#08x.\n",
2142 dev->name, np->dirty_tx,
2143 le32_to_cpu(np->tx_ring[entry].cmd_status));
2144 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2145 dev->stats.tx_packets++;
2146 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
2147 } else { /* Various Tx errors */
2148 int tx_status =
2149 le32_to_cpu(np->tx_ring[entry].cmd_status);
2150 if (tx_status & (DescTxAbort|DescTxExcColl))
2151 dev->stats.tx_aborted_errors++;
2152 if (tx_status & DescTxFIFO)
2153 dev->stats.tx_fifo_errors++;
2154 if (tx_status & DescTxCarrier)
2155 dev->stats.tx_carrier_errors++;
2156 if (tx_status & DescTxOOWCol)
2157 dev->stats.tx_window_errors++;
2158 dev->stats.tx_errors++;
2159 }
2160 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2161 np->tx_skbuff[entry]->len,
2162 PCI_DMA_TODEVICE);
2163 /* Free the original skb. */
2164 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2165 np->tx_skbuff[entry] = NULL;
2166 }
2167 if (netif_queue_stopped(dev) &&
2168 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2169 /* The ring is no longer full, wake queue. */
2170 netif_wake_queue(dev);
2171 }
2172}
2173
2174/* The interrupt handler doesn't actually handle interrupts itself, it
2175 * schedules a NAPI poll if there is anything to do. */
2176static irqreturn_t intr_handler(int irq, void *dev_instance)
2177{
2178 struct net_device *dev = dev_instance;
2179 struct netdev_private *np = netdev_priv(dev);
2180 void __iomem * ioaddr = ns_ioaddr(dev);
2181
2182 /* Reading IntrStatus automatically acknowledges so don't do
2183 * that while interrupts are disabled, (for example, while a
2184 * poll is scheduled). */
2185 if (np->hands_off || !readl(ioaddr + IntrEnable))
2186 return IRQ_NONE;
2187
2188 np->intr_status = readl(ioaddr + IntrStatus);
2189
2190 if (!np->intr_status)
2191 return IRQ_NONE;
2192
2193 if (netif_msg_intr(np))
2194 printk(KERN_DEBUG
2195 "%s: Interrupt, status %#08x, mask %#08x.\n",
2196 dev->name, np->intr_status,
2197 readl(ioaddr + IntrMask));
2198
2199 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2200
2201 if (napi_schedule_prep(&np->napi)) {
2202 /* Disable interrupts and register for poll */
2203 natsemi_irq_disable(dev);
2204 __napi_schedule(&np->napi);
2205 } else
2206 printk(KERN_WARNING
2207 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2208 dev->name, np->intr_status,
2209 readl(ioaddr + IntrMask));
2210
2211 return IRQ_HANDLED;
2212}
2213
2214/* This is the NAPI poll routine. As well as the standard RX handling
2215 * it also handles all other interrupts that the chip might raise.
2216 */
2217static int natsemi_poll(struct napi_struct *napi, int budget)
2218{
2219 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2220 struct net_device *dev = np->dev;
2221 void __iomem * ioaddr = ns_ioaddr(dev);
2222 int work_done = 0;
2223
2224 do {
2225 if (netif_msg_intr(np))
2226 printk(KERN_DEBUG
2227 "%s: Poll, status %#08x, mask %#08x.\n",
2228 dev->name, np->intr_status,
2229 readl(ioaddr + IntrMask));
2230
2231 /* netdev_rx() may read IntrStatus again if the RX state
2232 * machine falls over so do it first. */
2233 if (np->intr_status &
2234 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2235 IntrRxErr | IntrRxOverrun)) {
2236 netdev_rx(dev, &work_done, budget);
2237 }
2238
2239 if (np->intr_status &
2240 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2241 spin_lock(&np->lock);
2242 netdev_tx_done(dev);
2243 spin_unlock(&np->lock);
2244 }
2245
2246 /* Abnormal error summary/uncommon events handlers. */
2247 if (np->intr_status & IntrAbnormalSummary)
2248 netdev_error(dev, np->intr_status);
2249
2250 if (work_done >= budget)
2251 return work_done;
2252
2253 np->intr_status = readl(ioaddr + IntrStatus);
2254 } while (np->intr_status);
2255
2256 napi_complete(napi);
2257
2258 /* Reenable interrupts providing nothing is trying to shut
2259 * the chip down. */
2260 spin_lock(&np->lock);
2261 if (!np->hands_off)
2262 natsemi_irq_enable(dev);
2263 spin_unlock(&np->lock);
2264
2265 return work_done;
2266}
2267
2268/* This routine is logically part of the interrupt handler, but separated
2269 for clarity and better register allocation. */
2270static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2271{
2272 struct netdev_private *np = netdev_priv(dev);
2273 int entry = np->cur_rx % RX_RING_SIZE;
2274 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2275 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2276 unsigned int buflen = np->rx_buf_sz;
2277 void __iomem * ioaddr = ns_ioaddr(dev);
2278
2279 /* If the driver owns the next entry it's a new packet. Send it up. */
2280 while (desc_status < 0) { /* e.g. & DescOwn */
2281 int pkt_len;
2282 if (netif_msg_rx_status(np))
2283 printk(KERN_DEBUG
2284 " netdev_rx() entry %d status was %#08x.\n",
2285 entry, desc_status);
2286 if (--boguscnt < 0)
2287 break;
2288
2289 if (*work_done >= work_to_do)
2290 break;
2291
2292 (*work_done)++;
2293
2294 pkt_len = (desc_status & DescSizeMask) - 4;
2295 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2296 if (desc_status & DescMore) {
2297 unsigned long flags;
2298
2299 if (netif_msg_rx_err(np))
2300 printk(KERN_WARNING
2301 "%s: Oversized(?) Ethernet "
2302 "frame spanned multiple "
2303 "buffers, entry %#08x "
2304 "status %#08x.\n", dev->name,
2305 np->cur_rx, desc_status);
2306 dev->stats.rx_length_errors++;
2307
2308 /* The RX state machine has probably
2309 * locked up beneath us. Follow the
2310 * reset procedure documented in
2311 * AN-1287. */
2312
2313 spin_lock_irqsave(&np->lock, flags);
2314 reset_rx(dev);
2315 reinit_rx(dev);
2316 writel(np->ring_dma, ioaddr + RxRingPtr);
2317 check_link(dev);
2318 spin_unlock_irqrestore(&np->lock, flags);
2319
2320 /* We'll enable RX on exit from this
2321 * function. */
2322 break;
2323
2324 } else {
2325 /* There was an error. */
2326 dev->stats.rx_errors++;
2327 if (desc_status & (DescRxAbort|DescRxOver))
2328 dev->stats.rx_over_errors++;
2329 if (desc_status & (DescRxLong|DescRxRunt))
2330 dev->stats.rx_length_errors++;
2331 if (desc_status & (DescRxInvalid|DescRxAlign))
2332 dev->stats.rx_frame_errors++;
2333 if (desc_status & DescRxCRC)
2334 dev->stats.rx_crc_errors++;
2335 }
2336 } else if (pkt_len > np->rx_buf_sz) {
2337 /* if this is the tail of a double buffer
2338 * packet, we've already counted the error
2339 * on the first part. Ignore the second half.
2340 */
2341 } else {
2342 struct sk_buff *skb;
2343 /* Omit CRC size. */
2344 /* Check if the packet is long enough to accept
2345 * without copying to a minimally-sized skbuff. */
2346 if (pkt_len < rx_copybreak &&
2347 (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2348 /* 16 byte align the IP header */
2349 skb_reserve(skb, RX_OFFSET);
2350 pci_dma_sync_single_for_cpu(np->pci_dev,
2351 np->rx_dma[entry],
2352 buflen,
2353 PCI_DMA_FROMDEVICE);
2354 skb_copy_to_linear_data(skb,
2355 np->rx_skbuff[entry]->data, pkt_len);
2356 skb_put(skb, pkt_len);
2357 pci_dma_sync_single_for_device(np->pci_dev,
2358 np->rx_dma[entry],
2359 buflen,
2360 PCI_DMA_FROMDEVICE);
2361 } else {
2362 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2363 buflen + NATSEMI_PADDING,
2364 PCI_DMA_FROMDEVICE);
2365 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2366 np->rx_skbuff[entry] = NULL;
2367 }
2368 skb->protocol = eth_type_trans(skb, dev);
2369 netif_receive_skb(skb);
2370 dev->stats.rx_packets++;
2371 dev->stats.rx_bytes += pkt_len;
2372 }
2373 entry = (++np->cur_rx) % RX_RING_SIZE;
2374 np->rx_head_desc = &np->rx_ring[entry];
2375 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2376 }
2377 refill_rx(dev);
2378
2379 /* Restart Rx engine if stopped. */
2380 if (np->oom)
2381 mod_timer(&np->timer, jiffies + 1);
2382 else
2383 writel(RxOn, ioaddr + ChipCmd);
2384}
2385
2386static void netdev_error(struct net_device *dev, int intr_status)
2387{
2388 struct netdev_private *np = netdev_priv(dev);
2389 void __iomem * ioaddr = ns_ioaddr(dev);
2390
2391 spin_lock(&np->lock);
2392 if (intr_status & LinkChange) {
2393 u16 lpa = mdio_read(dev, MII_LPA);
2394 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2395 netif_msg_link(np)) {
2396 printk(KERN_INFO
2397 "%s: Autonegotiation advertising"
2398 " %#04x partner %#04x.\n", dev->name,
2399 np->advertising, lpa);
2400 }
2401
2402 /* read MII int status to clear the flag */
2403 readw(ioaddr + MIntrStatus);
2404 check_link(dev);
2405 }
2406 if (intr_status & StatsMax) {
2407 __get_stats(dev);
2408 }
2409 if (intr_status & IntrTxUnderrun) {
2410 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2411 np->tx_config += TX_DRTH_VAL_INC;
2412 if (netif_msg_tx_err(np))
2413 printk(KERN_NOTICE
2414 "%s: increased tx threshold, txcfg %#08x.\n",
2415 dev->name, np->tx_config);
2416 } else {
2417 if (netif_msg_tx_err(np))
2418 printk(KERN_NOTICE
2419 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2420 dev->name, np->tx_config);
2421 }
2422 writel(np->tx_config, ioaddr + TxConfig);
2423 }
2424 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2425 int wol_status = readl(ioaddr + WOLCmd);
2426 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2427 dev->name, wol_status);
2428 }
2429 if (intr_status & RxStatusFIFOOver) {
2430 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2431 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2432 dev->name);
2433 }
2434 dev->stats.rx_fifo_errors++;
2435 dev->stats.rx_errors++;
2436 }
2437 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2438 if (intr_status & IntrPCIErr) {
2439 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2440 intr_status & IntrPCIErr);
2441 dev->stats.tx_fifo_errors++;
2442 dev->stats.tx_errors++;
2443 dev->stats.rx_fifo_errors++;
2444 dev->stats.rx_errors++;
2445 }
2446 spin_unlock(&np->lock);
2447}
2448
2449static void __get_stats(struct net_device *dev)
2450{
2451 void __iomem * ioaddr = ns_ioaddr(dev);
2452
2453 /* The chip only need report frame silently dropped. */
2454 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2455 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2456}
2457
2458static struct net_device_stats *get_stats(struct net_device *dev)
2459{
2460 struct netdev_private *np = netdev_priv(dev);
2461
2462 /* The chip only need report frame silently dropped. */
2463 spin_lock_irq(&np->lock);
2464 if (netif_running(dev) && !np->hands_off)
2465 __get_stats(dev);
2466 spin_unlock_irq(&np->lock);
2467
2468 return &dev->stats;
2469}
2470
2471#ifdef CONFIG_NET_POLL_CONTROLLER
2472static void natsemi_poll_controller(struct net_device *dev)
2473{
2474 disable_irq(dev->irq);
2475 intr_handler(dev->irq, dev);
2476 enable_irq(dev->irq);
2477}
2478#endif
2479
2480#define HASH_TABLE 0x200
2481static void __set_rx_mode(struct net_device *dev)
2482{
2483 void __iomem * ioaddr = ns_ioaddr(dev);
2484 struct netdev_private *np = netdev_priv(dev);
2485 u8 mc_filter[64]; /* Multicast hash filter */
2486 u32 rx_mode;
2487
2488 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2489 rx_mode = RxFilterEnable | AcceptBroadcast
2490 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2491 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2492 (dev->flags & IFF_ALLMULTI)) {
2493 rx_mode = RxFilterEnable | AcceptBroadcast
2494 | AcceptAllMulticast | AcceptMyPhys;
2495 } else {
2496 struct netdev_hw_addr *ha;
2497 int i;
2498
2499 memset(mc_filter, 0, sizeof(mc_filter));
2500 netdev_for_each_mc_addr(ha, dev) {
2501 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
2502 mc_filter[b/8] |= (1 << (b & 0x07));
2503 }
2504 rx_mode = RxFilterEnable | AcceptBroadcast
2505 | AcceptMulticast | AcceptMyPhys;
2506 for (i = 0; i < 64; i += 2) {
2507 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2508 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2509 ioaddr + RxFilterData);
2510 }
2511 }
2512 writel(rx_mode, ioaddr + RxFilterAddr);
2513 np->cur_rx_mode = rx_mode;
2514}
2515
2516static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2517{
2518 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2519 return -EINVAL;
2520
2521 dev->mtu = new_mtu;
2522
2523 /* synchronized against open : rtnl_lock() held by caller */
2524 if (netif_running(dev)) {
2525 struct netdev_private *np = netdev_priv(dev);
2526 void __iomem * ioaddr = ns_ioaddr(dev);
2527
2528 disable_irq(dev->irq);
2529 spin_lock(&np->lock);
2530 /* stop engines */
2531 natsemi_stop_rxtx(dev);
2532 /* drain rx queue */
2533 drain_rx(dev);
2534 /* change buffers */
2535 set_bufsize(dev);
2536 reinit_rx(dev);
2537 writel(np->ring_dma, ioaddr + RxRingPtr);
2538 /* restart engines */
2539 writel(RxOn | TxOn, ioaddr + ChipCmd);
2540 spin_unlock(&np->lock);
2541 enable_irq(dev->irq);
2542 }
2543 return 0;
2544}
2545
2546static void set_rx_mode(struct net_device *dev)
2547{
2548 struct netdev_private *np = netdev_priv(dev);
2549 spin_lock_irq(&np->lock);
2550 if (!np->hands_off)
2551 __set_rx_mode(dev);
2552 spin_unlock_irq(&np->lock);
2553}
2554
2555static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2556{
2557 struct netdev_private *np = netdev_priv(dev);
2558 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2559 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2560 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2561}
2562
2563static int get_regs_len(struct net_device *dev)
2564{
2565 return NATSEMI_REGS_SIZE;
2566}
2567
2568static int get_eeprom_len(struct net_device *dev)
2569{
2570 struct netdev_private *np = netdev_priv(dev);
2571 return np->eeprom_size;
2572}
2573
2574static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2575{
2576 struct netdev_private *np = netdev_priv(dev);
2577 spin_lock_irq(&np->lock);
2578 netdev_get_ecmd(dev, ecmd);
2579 spin_unlock_irq(&np->lock);
2580 return 0;
2581}
2582
2583static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2584{
2585 struct netdev_private *np = netdev_priv(dev);
2586 int res;
2587 spin_lock_irq(&np->lock);
2588 res = netdev_set_ecmd(dev, ecmd);
2589 spin_unlock_irq(&np->lock);
2590 return res;
2591}
2592
2593static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2594{
2595 struct netdev_private *np = netdev_priv(dev);
2596 spin_lock_irq(&np->lock);
2597 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2598 netdev_get_sopass(dev, wol->sopass);
2599 spin_unlock_irq(&np->lock);
2600}
2601
2602static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2603{
2604 struct netdev_private *np = netdev_priv(dev);
2605 int res;
2606 spin_lock_irq(&np->lock);
2607 netdev_set_wol(dev, wol->wolopts);
2608 res = netdev_set_sopass(dev, wol->sopass);
2609 spin_unlock_irq(&np->lock);
2610 return res;
2611}
2612
2613static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2614{
2615 struct netdev_private *np = netdev_priv(dev);
2616 regs->version = NATSEMI_REGS_VER;
2617 spin_lock_irq(&np->lock);
2618 netdev_get_regs(dev, buf);
2619 spin_unlock_irq(&np->lock);
2620}
2621
2622static u32 get_msglevel(struct net_device *dev)
2623{
2624 struct netdev_private *np = netdev_priv(dev);
2625 return np->msg_enable;
2626}
2627
2628static void set_msglevel(struct net_device *dev, u32 val)
2629{
2630 struct netdev_private *np = netdev_priv(dev);
2631 np->msg_enable = val;
2632}
2633
2634static int nway_reset(struct net_device *dev)
2635{
2636 int tmp;
2637 int r = -EINVAL;
2638 /* if autoneg is off, it's an error */
2639 tmp = mdio_read(dev, MII_BMCR);
2640 if (tmp & BMCR_ANENABLE) {
2641 tmp |= (BMCR_ANRESTART);
2642 mdio_write(dev, MII_BMCR, tmp);
2643 r = 0;
2644 }
2645 return r;
2646}
2647
2648static u32 get_link(struct net_device *dev)
2649{
2650 /* LSTATUS is latched low until a read - so read twice */
2651 mdio_read(dev, MII_BMSR);
2652 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2653}
2654
2655static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2656{
2657 struct netdev_private *np = netdev_priv(dev);
2658 u8 *eebuf;
2659 int res;
2660
2661 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2662 if (!eebuf)
2663 return -ENOMEM;
2664
2665 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2666 spin_lock_irq(&np->lock);
2667 res = netdev_get_eeprom(dev, eebuf);
2668 spin_unlock_irq(&np->lock);
2669 if (!res)
2670 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2671 kfree(eebuf);
2672 return res;
2673}
2674
2675static const struct ethtool_ops ethtool_ops = {
2676 .get_drvinfo = get_drvinfo,
2677 .get_regs_len = get_regs_len,
2678 .get_eeprom_len = get_eeprom_len,
2679 .get_settings = get_settings,
2680 .set_settings = set_settings,
2681 .get_wol = get_wol,
2682 .set_wol = set_wol,
2683 .get_regs = get_regs,
2684 .get_msglevel = get_msglevel,
2685 .set_msglevel = set_msglevel,
2686 .nway_reset = nway_reset,
2687 .get_link = get_link,
2688 .get_eeprom = get_eeprom,
2689};
2690
2691static int netdev_set_wol(struct net_device *dev, u32 newval)
2692{
2693 struct netdev_private *np = netdev_priv(dev);
2694 void __iomem * ioaddr = ns_ioaddr(dev);
2695 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2696
2697 /* translate to bitmasks this chip understands */
2698 if (newval & WAKE_PHY)
2699 data |= WakePhy;
2700 if (newval & WAKE_UCAST)
2701 data |= WakeUnicast;
2702 if (newval & WAKE_MCAST)
2703 data |= WakeMulticast;
2704 if (newval & WAKE_BCAST)
2705 data |= WakeBroadcast;
2706 if (newval & WAKE_ARP)
2707 data |= WakeArp;
2708 if (newval & WAKE_MAGIC)
2709 data |= WakeMagic;
2710 if (np->srr >= SRR_DP83815_D) {
2711 if (newval & WAKE_MAGICSECURE) {
2712 data |= WakeMagicSecure;
2713 }
2714 }
2715
2716 writel(data, ioaddr + WOLCmd);
2717
2718 return 0;
2719}
2720
2721static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2722{
2723 struct netdev_private *np = netdev_priv(dev);
2724 void __iomem * ioaddr = ns_ioaddr(dev);
2725 u32 regval = readl(ioaddr + WOLCmd);
2726
2727 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2728 | WAKE_ARP | WAKE_MAGIC);
2729
2730 if (np->srr >= SRR_DP83815_D) {
2731 /* SOPASS works on revD and higher */
2732 *supported |= WAKE_MAGICSECURE;
2733 }
2734 *cur = 0;
2735
2736 /* translate from chip bitmasks */
2737 if (regval & WakePhy)
2738 *cur |= WAKE_PHY;
2739 if (regval & WakeUnicast)
2740 *cur |= WAKE_UCAST;
2741 if (regval & WakeMulticast)
2742 *cur |= WAKE_MCAST;
2743 if (regval & WakeBroadcast)
2744 *cur |= WAKE_BCAST;
2745 if (regval & WakeArp)
2746 *cur |= WAKE_ARP;
2747 if (regval & WakeMagic)
2748 *cur |= WAKE_MAGIC;
2749 if (regval & WakeMagicSecure) {
2750 /* this can be on in revC, but it's broken */
2751 *cur |= WAKE_MAGICSECURE;
2752 }
2753
2754 return 0;
2755}
2756
2757static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2758{
2759 struct netdev_private *np = netdev_priv(dev);
2760 void __iomem * ioaddr = ns_ioaddr(dev);
2761 u16 *sval = (u16 *)newval;
2762 u32 addr;
2763
2764 if (np->srr < SRR_DP83815_D) {
2765 return 0;
2766 }
2767
2768 /* enable writing to these registers by disabling the RX filter */
2769 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2770 addr &= ~RxFilterEnable;
2771 writel(addr, ioaddr + RxFilterAddr);
2772
2773 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2774 writel(addr | 0xa, ioaddr + RxFilterAddr);
2775 writew(sval[0], ioaddr + RxFilterData);
2776
2777 writel(addr | 0xc, ioaddr + RxFilterAddr);
2778 writew(sval[1], ioaddr + RxFilterData);
2779
2780 writel(addr | 0xe, ioaddr + RxFilterAddr);
2781 writew(sval[2], ioaddr + RxFilterData);
2782
2783 /* re-enable the RX filter */
2784 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2785
2786 return 0;
2787}
2788
2789static int netdev_get_sopass(struct net_device *dev, u8 *data)
2790{
2791 struct netdev_private *np = netdev_priv(dev);
2792 void __iomem * ioaddr = ns_ioaddr(dev);
2793 u16 *sval = (u16 *)data;
2794 u32 addr;
2795
2796 if (np->srr < SRR_DP83815_D) {
2797 sval[0] = sval[1] = sval[2] = 0;
2798 return 0;
2799 }
2800
2801 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2802 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2803
2804 writel(addr | 0xa, ioaddr + RxFilterAddr);
2805 sval[0] = readw(ioaddr + RxFilterData);
2806
2807 writel(addr | 0xc, ioaddr + RxFilterAddr);
2808 sval[1] = readw(ioaddr + RxFilterData);
2809
2810 writel(addr | 0xe, ioaddr + RxFilterAddr);
2811 sval[2] = readw(ioaddr + RxFilterData);
2812
2813 writel(addr, ioaddr + RxFilterAddr);
2814
2815 return 0;
2816}
2817
2818static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2819{
2820 struct netdev_private *np = netdev_priv(dev);
2821 u32 tmp;
2822
2823 ecmd->port = dev->if_port;
2824 ethtool_cmd_speed_set(ecmd, np->speed);
2825 ecmd->duplex = np->duplex;
2826 ecmd->autoneg = np->autoneg;
2827 ecmd->advertising = 0;
2828 if (np->advertising & ADVERTISE_10HALF)
2829 ecmd->advertising |= ADVERTISED_10baseT_Half;
2830 if (np->advertising & ADVERTISE_10FULL)
2831 ecmd->advertising |= ADVERTISED_10baseT_Full;
2832 if (np->advertising & ADVERTISE_100HALF)
2833 ecmd->advertising |= ADVERTISED_100baseT_Half;
2834 if (np->advertising & ADVERTISE_100FULL)
2835 ecmd->advertising |= ADVERTISED_100baseT_Full;
2836 ecmd->supported = (SUPPORTED_Autoneg |
2837 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2838 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2839 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2840 ecmd->phy_address = np->phy_addr_external;
2841 /*
2842 * We intentionally report the phy address of the external
2843 * phy, even if the internal phy is used. This is necessary
2844 * to work around a deficiency of the ethtool interface:
2845 * It's only possible to query the settings of the active
2846 * port. Therefore
2847 * # ethtool -s ethX port mii
2848 * actually sends an ioctl to switch to port mii with the
2849 * settings that are used for the current active port.
2850 * If we would report a different phy address in this
2851 * command, then
2852 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2853 * would unintentionally change the phy address.
2854 *
2855 * Fortunately the phy address doesn't matter with the
2856 * internal phy...
2857 */
2858
2859 /* set information based on active port type */
2860 switch (ecmd->port) {
2861 default:
2862 case PORT_TP:
2863 ecmd->advertising |= ADVERTISED_TP;
2864 ecmd->transceiver = XCVR_INTERNAL;
2865 break;
2866 case PORT_MII:
2867 ecmd->advertising |= ADVERTISED_MII;
2868 ecmd->transceiver = XCVR_EXTERNAL;
2869 break;
2870 case PORT_FIBRE:
2871 ecmd->advertising |= ADVERTISED_FIBRE;
2872 ecmd->transceiver = XCVR_EXTERNAL;
2873 break;
2874 }
2875
2876 /* if autonegotiation is on, try to return the active speed/duplex */
2877 if (ecmd->autoneg == AUTONEG_ENABLE) {
2878 ecmd->advertising |= ADVERTISED_Autoneg;
2879 tmp = mii_nway_result(
2880 np->advertising & mdio_read(dev, MII_LPA));
2881 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2882 ethtool_cmd_speed_set(ecmd, SPEED_100);
2883 else
2884 ethtool_cmd_speed_set(ecmd, SPEED_10);
2885 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2886 ecmd->duplex = DUPLEX_FULL;
2887 else
2888 ecmd->duplex = DUPLEX_HALF;
2889 }
2890
2891 /* ignore maxtxpkt, maxrxpkt for now */
2892
2893 return 0;
2894}
2895
2896static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2897{
2898 struct netdev_private *np = netdev_priv(dev);
2899
2900 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2901 return -EINVAL;
2902 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2903 return -EINVAL;
2904 if (ecmd->autoneg == AUTONEG_ENABLE) {
2905 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2906 ADVERTISED_10baseT_Full |
2907 ADVERTISED_100baseT_Half |
2908 ADVERTISED_100baseT_Full)) == 0) {
2909 return -EINVAL;
2910 }
2911 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2912 u32 speed = ethtool_cmd_speed(ecmd);
2913 if (speed != SPEED_10 && speed != SPEED_100)
2914 return -EINVAL;
2915 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2916 return -EINVAL;
2917 } else {
2918 return -EINVAL;
2919 }
2920
2921 /*
2922 * If we're ignoring the PHY then autoneg and the internal
2923 * transceiver are really not going to work so don't let the
2924 * user select them.
2925 */
2926 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2927 ecmd->port == PORT_TP))
2928 return -EINVAL;
2929
2930 /*
2931 * maxtxpkt, maxrxpkt: ignored for now.
2932 *
2933 * transceiver:
2934 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2935 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2936 * selects based on ecmd->port.
2937 *
2938 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2939 * phys that are connected to the mii bus. It's used to apply fibre
2940 * specific updates.
2941 */
2942
2943 /* WHEW! now lets bang some bits */
2944
2945 /* save the parms */
2946 dev->if_port = ecmd->port;
2947 np->autoneg = ecmd->autoneg;
2948 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2949 if (np->autoneg == AUTONEG_ENABLE) {
2950 /* advertise only what has been requested */
2951 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2952 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2953 np->advertising |= ADVERTISE_10HALF;
2954 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2955 np->advertising |= ADVERTISE_10FULL;
2956 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2957 np->advertising |= ADVERTISE_100HALF;
2958 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2959 np->advertising |= ADVERTISE_100FULL;
2960 } else {
2961 np->speed = ethtool_cmd_speed(ecmd);
2962 np->duplex = ecmd->duplex;
2963 /* user overriding the initial full duplex parm? */
2964 if (np->duplex == DUPLEX_HALF)
2965 np->full_duplex = 0;
2966 }
2967
2968 /* get the right phy enabled */
2969 if (ecmd->port == PORT_TP)
2970 switch_port_internal(dev);
2971 else
2972 switch_port_external(dev);
2973
2974 /* set parms and see how this affected our link status */
2975 init_phy_fixup(dev);
2976 check_link(dev);
2977 return 0;
2978}
2979
2980static int netdev_get_regs(struct net_device *dev, u8 *buf)
2981{
2982 int i;
2983 int j;
2984 u32 rfcr;
2985 u32 *rbuf = (u32 *)buf;
2986 void __iomem * ioaddr = ns_ioaddr(dev);
2987
2988 /* read non-mii page 0 of registers */
2989 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2990 rbuf[i] = readl(ioaddr + i*4);
2991 }
2992
2993 /* read current mii registers */
2994 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2995 rbuf[i] = mdio_read(dev, i & 0x1f);
2996
2997 /* read only the 'magic' registers from page 1 */
2998 writew(1, ioaddr + PGSEL);
2999 rbuf[i++] = readw(ioaddr + PMDCSR);
3000 rbuf[i++] = readw(ioaddr + TSTDAT);
3001 rbuf[i++] = readw(ioaddr + DSPCFG);
3002 rbuf[i++] = readw(ioaddr + SDCFG);
3003 writew(0, ioaddr + PGSEL);
3004
3005 /* read RFCR indexed registers */
3006 rfcr = readl(ioaddr + RxFilterAddr);
3007 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3008 writel(j*2, ioaddr + RxFilterAddr);
3009 rbuf[i++] = readw(ioaddr + RxFilterData);
3010 }
3011 writel(rfcr, ioaddr + RxFilterAddr);
3012
3013 /* the interrupt status is clear-on-read - see if we missed any */
3014 if (rbuf[4] & rbuf[5]) {
3015 printk(KERN_WARNING
3016 "%s: shoot, we dropped an interrupt (%#08x)\n",
3017 dev->name, rbuf[4] & rbuf[5]);
3018 }
3019
3020 return 0;
3021}
3022
3023#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3024 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3025 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3026 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3027 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3028 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3029 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3030 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3031
3032static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3033{
3034 int i;
3035 u16 *ebuf = (u16 *)buf;
3036 void __iomem * ioaddr = ns_ioaddr(dev);
3037 struct netdev_private *np = netdev_priv(dev);
3038
3039 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3040 for (i = 0; i < np->eeprom_size/2; i++) {
3041 ebuf[i] = eeprom_read(ioaddr, i);
3042 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3043 * reads it back "sanely". So we swap it back here in order to
3044 * present it to userland as it is stored. */
3045 ebuf[i] = SWAP_BITS(ebuf[i]);
3046 }
3047 return 0;
3048}
3049
3050static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3051{
3052 struct mii_ioctl_data *data = if_mii(rq);
3053 struct netdev_private *np = netdev_priv(dev);
3054
3055 switch(cmd) {
3056 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3057 data->phy_id = np->phy_addr_external;
3058 /* Fall Through */
3059
3060 case SIOCGMIIREG: /* Read MII PHY register. */
3061 /* The phy_id is not enough to uniquely identify
3062 * the intended target. Therefore the command is sent to
3063 * the given mii on the current port.
3064 */
3065 if (dev->if_port == PORT_TP) {
3066 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3067 data->val_out = mdio_read(dev,
3068 data->reg_num & 0x1f);
3069 else
3070 data->val_out = 0;
3071 } else {
3072 move_int_phy(dev, data->phy_id & 0x1f);
3073 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3074 data->reg_num & 0x1f);
3075 }
3076 return 0;
3077
3078 case SIOCSMIIREG: /* Write MII PHY register. */
3079 if (dev->if_port == PORT_TP) {
3080 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3081 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3082 np->advertising = data->val_in;
3083 mdio_write(dev, data->reg_num & 0x1f,
3084 data->val_in);
3085 }
3086 } else {
3087 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3088 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3089 np->advertising = data->val_in;
3090 }
3091 move_int_phy(dev, data->phy_id & 0x1f);
3092 miiport_write(dev, data->phy_id & 0x1f,
3093 data->reg_num & 0x1f,
3094 data->val_in);
3095 }
3096 return 0;
3097 default:
3098 return -EOPNOTSUPP;
3099 }
3100}
3101
3102static void enable_wol_mode(struct net_device *dev, int enable_intr)
3103{
3104 void __iomem * ioaddr = ns_ioaddr(dev);
3105 struct netdev_private *np = netdev_priv(dev);
3106
3107 if (netif_msg_wol(np))
3108 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3109 dev->name);
3110
3111 /* For WOL we must restart the rx process in silent mode.
3112 * Write NULL to the RxRingPtr. Only possible if
3113 * rx process is stopped
3114 */
3115 writel(0, ioaddr + RxRingPtr);
3116
3117 /* read WoL status to clear */
3118 readl(ioaddr + WOLCmd);
3119
3120 /* PME on, clear status */
3121 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3122
3123 /* and restart the rx process */
3124 writel(RxOn, ioaddr + ChipCmd);
3125
3126 if (enable_intr) {
3127 /* enable the WOL interrupt.
3128 * Could be used to send a netlink message.
3129 */
3130 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3131 natsemi_irq_enable(dev);
3132 }
3133}
3134
3135static int netdev_close(struct net_device *dev)
3136{
3137 void __iomem * ioaddr = ns_ioaddr(dev);
3138 struct netdev_private *np = netdev_priv(dev);
3139
3140 if (netif_msg_ifdown(np))
3141 printk(KERN_DEBUG
3142 "%s: Shutting down ethercard, status was %#04x.\n",
3143 dev->name, (int)readl(ioaddr + ChipCmd));
3144 if (netif_msg_pktdata(np))
3145 printk(KERN_DEBUG
3146 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3147 dev->name, np->cur_tx, np->dirty_tx,
3148 np->cur_rx, np->dirty_rx);
3149
3150 napi_disable(&np->napi);
3151
3152 /*
3153 * FIXME: what if someone tries to close a device
3154 * that is suspended?
3155 * Should we reenable the nic to switch to
3156 * the final WOL settings?
3157 */
3158
3159 del_timer_sync(&np->timer);
3160 disable_irq(dev->irq);
3161 spin_lock_irq(&np->lock);
3162 natsemi_irq_disable(dev);
3163 np->hands_off = 1;
3164 spin_unlock_irq(&np->lock);
3165 enable_irq(dev->irq);
3166
3167 free_irq(dev->irq, dev);
3168
3169 /* Interrupt disabled, interrupt handler released,
3170 * queue stopped, timer deleted, rtnl_lock held
3171 * All async codepaths that access the driver are disabled.
3172 */
3173 spin_lock_irq(&np->lock);
3174 np->hands_off = 0;
3175 readl(ioaddr + IntrMask);
3176 readw(ioaddr + MIntrStatus);
3177
3178 /* Freeze Stats */
3179 writel(StatsFreeze, ioaddr + StatsCtrl);
3180
3181 /* Stop the chip's Tx and Rx processes. */
3182 natsemi_stop_rxtx(dev);
3183
3184 __get_stats(dev);
3185 spin_unlock_irq(&np->lock);
3186
3187 /* clear the carrier last - an interrupt could reenable it otherwise */
3188 netif_carrier_off(dev);
3189 netif_stop_queue(dev);
3190
3191 dump_ring(dev);
3192 drain_ring(dev);
3193 free_ring(dev);
3194
3195 {
3196 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3197 if (wol) {
3198 /* restart the NIC in WOL mode.
3199 * The nic must be stopped for this.
3200 */
3201 enable_wol_mode(dev, 0);
3202 } else {
3203 /* Restore PME enable bit unmolested */
3204 writel(np->SavedClkRun, ioaddr + ClkRun);
3205 }
3206 }
3207 return 0;
3208}
3209
3210
3211static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3212{
3213 struct net_device *dev = pci_get_drvdata(pdev);
3214 void __iomem * ioaddr = ns_ioaddr(dev);
3215
3216 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3217 unregister_netdev (dev);
3218 pci_release_regions (pdev);
3219 iounmap(ioaddr);
3220 free_netdev (dev);
3221 pci_set_drvdata(pdev, NULL);
3222}
3223
3224#ifdef CONFIG_PM
3225
3226/*
3227 * The ns83815 chip doesn't have explicit RxStop bits.
3228 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3229 * of the nic, thus this function must be very careful:
3230 *
3231 * suspend/resume synchronization:
3232 * entry points:
3233 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3234 * start_tx, ns_tx_timeout
3235 *
3236 * No function accesses the hardware without checking np->hands_off.
3237 * the check occurs under spin_lock_irq(&np->lock);
3238 * exceptions:
3239 * * netdev_ioctl: noncritical access.
3240 * * netdev_open: cannot happen due to the device_detach
3241 * * netdev_close: doesn't hurt.
3242 * * netdev_timer: timer stopped by natsemi_suspend.
3243 * * intr_handler: doesn't acquire the spinlock. suspend calls
3244 * disable_irq() to enforce synchronization.
3245 * * natsemi_poll: checks before reenabling interrupts. suspend
3246 * sets hands_off, disables interrupts and then waits with
3247 * napi_disable().
3248 *
3249 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3250 */
3251
3252static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3253{
3254 struct net_device *dev = pci_get_drvdata (pdev);
3255 struct netdev_private *np = netdev_priv(dev);
3256 void __iomem * ioaddr = ns_ioaddr(dev);
3257
3258 rtnl_lock();
3259 if (netif_running (dev)) {
3260 del_timer_sync(&np->timer);
3261
3262 disable_irq(dev->irq);
3263 spin_lock_irq(&np->lock);
3264
3265 natsemi_irq_disable(dev);
3266 np->hands_off = 1;
3267 natsemi_stop_rxtx(dev);
3268 netif_stop_queue(dev);
3269
3270 spin_unlock_irq(&np->lock);
3271 enable_irq(dev->irq);
3272
3273 napi_disable(&np->napi);
3274
3275 /* Update the error counts. */
3276 __get_stats(dev);
3277
3278 /* pci_power_off(pdev, -1); */
3279 drain_ring(dev);
3280 {
3281 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3282 /* Restore PME enable bit */
3283 if (wol) {
3284 /* restart the NIC in WOL mode.
3285 * The nic must be stopped for this.
3286 * FIXME: use the WOL interrupt
3287 */
3288 enable_wol_mode(dev, 0);
3289 } else {
3290 /* Restore PME enable bit unmolested */
3291 writel(np->SavedClkRun, ioaddr + ClkRun);
3292 }
3293 }
3294 }
3295 netif_device_detach(dev);
3296 rtnl_unlock();
3297 return 0;
3298}
3299
3300
3301static int natsemi_resume (struct pci_dev *pdev)
3302{
3303 struct net_device *dev = pci_get_drvdata (pdev);
3304 struct netdev_private *np = netdev_priv(dev);
3305 int ret = 0;
3306
3307 rtnl_lock();
3308 if (netif_device_present(dev))
3309 goto out;
3310 if (netif_running(dev)) {
3311 BUG_ON(!np->hands_off);
3312 ret = pci_enable_device(pdev);
3313 if (ret < 0) {
3314 dev_err(&pdev->dev,
3315 "pci_enable_device() failed: %d\n", ret);
3316 goto out;
3317 }
3318 /* pci_power_on(pdev); */
3319
3320 napi_enable(&np->napi);
3321
3322 natsemi_reset(dev);
3323 init_ring(dev);
3324 disable_irq(dev->irq);
3325 spin_lock_irq(&np->lock);
3326 np->hands_off = 0;
3327 init_registers(dev);
3328 netif_device_attach(dev);
3329 spin_unlock_irq(&np->lock);
3330 enable_irq(dev->irq);
3331
3332 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3333 }
3334 netif_device_attach(dev);
3335out:
3336 rtnl_unlock();
3337 return ret;
3338}
3339
3340#endif /* CONFIG_PM */
3341
3342static struct pci_driver natsemi_driver = {
3343 .name = DRV_NAME,
3344 .id_table = natsemi_pci_tbl,
3345 .probe = natsemi_probe1,
3346 .remove = __devexit_p(natsemi_remove1),
3347#ifdef CONFIG_PM
3348 .suspend = natsemi_suspend,
3349 .resume = natsemi_resume,
3350#endif
3351};
3352
3353static int __init natsemi_init_mod (void)
3354{
3355/* when a module, this is printed whether or not devices are found in probe */
3356#ifdef MODULE
3357 printk(version);
3358#endif
3359
3360 return pci_register_driver(&natsemi_driver);
3361}
3362
3363static void __exit natsemi_exit_mod (void)
3364{
3365 pci_unregister_driver (&natsemi_driver);
3366}
3367
3368module_init(natsemi_init_mod);
3369module_exit(natsemi_exit_mod);
3370