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1/*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include "ixgb_hw.h"
36#include "ixgb_ids.h"
37
38#include <linux/etherdevice.h>
39
40/* Local function prototypes */
41
42static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
43
44static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
45
46static void ixgb_get_bus_info(struct ixgb_hw *hw);
47
48static bool ixgb_link_reset(struct ixgb_hw *hw);
49
50static void ixgb_optics_reset(struct ixgb_hw *hw);
51
52static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
53
54static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
55
56static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
57
58static void ixgb_clear_vfta(struct ixgb_hw *hw);
59
60static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
61
62static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
63 u32 reg_address,
64 u32 phy_address,
65 u32 device_type);
66
67static bool ixgb_setup_fc(struct ixgb_hw *hw);
68
69static bool mac_addr_valid(u8 *mac_addr);
70
71static u32 ixgb_mac_reset(struct ixgb_hw *hw)
72{
73 u32 ctrl_reg;
74
75 ctrl_reg = IXGB_CTRL0_RST |
76 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
77 IXGB_CTRL0_SDP2_DIR |
78 IXGB_CTRL0_SDP1_DIR |
79 IXGB_CTRL0_SDP0_DIR |
80 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
81 IXGB_CTRL0_SDP2 |
82 IXGB_CTRL0_SDP0;
83
84#ifdef HP_ZX1
85 /* Workaround for 82597EX reset errata */
86 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
87#else
88 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
89#endif
90
91 /* Delay a few ms just to allow the reset to complete */
92 msleep(IXGB_DELAY_AFTER_RESET);
93 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
94#ifdef DBG
95 /* Make sure the self-clearing global reset bit did self clear */
96 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
97#endif
98
99 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
100 ctrl_reg = /* Enable interrupt from XFP and SerDes */
101 IXGB_CTRL1_GPI0_EN |
102 IXGB_CTRL1_SDP6_DIR |
103 IXGB_CTRL1_SDP7_DIR |
104 IXGB_CTRL1_SDP6 |
105 IXGB_CTRL1_SDP7;
106 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
107 ixgb_optics_reset_bcm(hw);
108 }
109
110 if (hw->phy_type == ixgb_phy_type_txn17401)
111 ixgb_optics_reset(hw);
112
113 return ctrl_reg;
114}
115
116/******************************************************************************
117 * Reset the transmit and receive units; mask and clear all interrupts.
118 *
119 * hw - Struct containing variables accessed by shared code
120 *****************************************************************************/
121bool
122ixgb_adapter_stop(struct ixgb_hw *hw)
123{
124 u32 ctrl_reg;
125 u32 icr_reg;
126
127 ENTER();
128
129 /* If we are stopped or resetting exit gracefully and wait to be
130 * started again before accessing the hardware.
131 */
132 if (hw->adapter_stopped) {
133 pr_debug("Exiting because the adapter is already stopped!!!\n");
134 return false;
135 }
136
137 /* Set the Adapter Stopped flag so other driver functions stop
138 * touching the Hardware.
139 */
140 hw->adapter_stopped = true;
141
142 /* Clear interrupt mask to stop board from generating interrupts */
143 pr_debug("Masking off all interrupts\n");
144 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
145
146 /* Disable the Transmit and Receive units. Then delay to allow
147 * any pending transactions to complete before we hit the MAC with
148 * the global reset.
149 */
150 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
151 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
152 IXGB_WRITE_FLUSH(hw);
153 msleep(IXGB_DELAY_BEFORE_RESET);
154
155 /* Issue a global reset to the MAC. This will reset the chip's
156 * transmit, receive, DMA, and link units. It will not effect
157 * the current PCI configuration. The global reset bit is self-
158 * clearing, and should clear within a microsecond.
159 */
160 pr_debug("Issuing a global reset to MAC\n");
161
162 ctrl_reg = ixgb_mac_reset(hw);
163
164 /* Clear interrupt mask to stop board from generating interrupts */
165 pr_debug("Masking off all interrupts\n");
166 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
167
168 /* Clear any pending interrupt events. */
169 icr_reg = IXGB_READ_REG(hw, ICR);
170
171 return ctrl_reg & IXGB_CTRL0_RST;
172}
173
174
175/******************************************************************************
176 * Identifies the vendor of the optics module on the adapter. The SR adapters
177 * support two different types of XPAK optics, so it is necessary to determine
178 * which optics are present before applying any optics-specific workarounds.
179 *
180 * hw - Struct containing variables accessed by shared code.
181 *
182 * Returns: the vendor of the XPAK optics module.
183 *****************************************************************************/
184static ixgb_xpak_vendor
185ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
186{
187 u32 i;
188 u16 vendor_name[5];
189 ixgb_xpak_vendor xpak_vendor;
190
191 ENTER();
192
193 /* Read the first few bytes of the vendor string from the XPAK NVR
194 * registers. These are standard XENPAK/XPAK registers, so all XPAK
195 * devices should implement them. */
196 for (i = 0; i < 5; i++) {
197 vendor_name[i] = ixgb_read_phy_reg(hw,
198 MDIO_PMA_PMD_XPAK_VENDOR_NAME
199 + i, IXGB_PHY_ADDRESS,
200 MDIO_MMD_PMAPMD);
201 }
202
203 /* Determine the actual vendor */
204 if (vendor_name[0] == 'I' &&
205 vendor_name[1] == 'N' &&
206 vendor_name[2] == 'T' &&
207 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
208 xpak_vendor = ixgb_xpak_vendor_intel;
209 } else {
210 xpak_vendor = ixgb_xpak_vendor_infineon;
211 }
212
213 return xpak_vendor;
214}
215
216/******************************************************************************
217 * Determine the physical layer module on the adapter.
218 *
219 * hw - Struct containing variables accessed by shared code. The device_id
220 * field must be (correctly) populated before calling this routine.
221 *
222 * Returns: the phy type of the adapter.
223 *****************************************************************************/
224static ixgb_phy_type
225ixgb_identify_phy(struct ixgb_hw *hw)
226{
227 ixgb_phy_type phy_type;
228 ixgb_xpak_vendor xpak_vendor;
229
230 ENTER();
231
232 /* Infer the transceiver/phy type from the device id */
233 switch (hw->device_id) {
234 case IXGB_DEVICE_ID_82597EX:
235 pr_debug("Identified TXN17401 optics\n");
236 phy_type = ixgb_phy_type_txn17401;
237 break;
238
239 case IXGB_DEVICE_ID_82597EX_SR:
240 /* The SR adapters carry two different types of XPAK optics
241 * modules; read the vendor identifier to determine the exact
242 * type of optics. */
243 xpak_vendor = ixgb_identify_xpak_vendor(hw);
244 if (xpak_vendor == ixgb_xpak_vendor_intel) {
245 pr_debug("Identified TXN17201 optics\n");
246 phy_type = ixgb_phy_type_txn17201;
247 } else {
248 pr_debug("Identified G6005 optics\n");
249 phy_type = ixgb_phy_type_g6005;
250 }
251 break;
252 case IXGB_DEVICE_ID_82597EX_LR:
253 pr_debug("Identified G6104 optics\n");
254 phy_type = ixgb_phy_type_g6104;
255 break;
256 case IXGB_DEVICE_ID_82597EX_CX4:
257 pr_debug("Identified CX4\n");
258 xpak_vendor = ixgb_identify_xpak_vendor(hw);
259 if (xpak_vendor == ixgb_xpak_vendor_intel) {
260 pr_debug("Identified TXN17201 optics\n");
261 phy_type = ixgb_phy_type_txn17201;
262 } else {
263 pr_debug("Identified G6005 optics\n");
264 phy_type = ixgb_phy_type_g6005;
265 }
266 break;
267 default:
268 pr_debug("Unknown physical layer module\n");
269 phy_type = ixgb_phy_type_unknown;
270 break;
271 }
272
273 /* update phy type for sun specific board */
274 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
275 phy_type = ixgb_phy_type_bcm;
276
277 return phy_type;
278}
279
280/******************************************************************************
281 * Performs basic configuration of the adapter.
282 *
283 * hw - Struct containing variables accessed by shared code
284 *
285 * Resets the controller.
286 * Reads and validates the EEPROM.
287 * Initializes the receive address registers.
288 * Initializes the multicast table.
289 * Clears all on-chip counters.
290 * Calls routine to setup flow control settings.
291 * Leaves the transmit and receive units disabled and uninitialized.
292 *
293 * Returns:
294 * true if successful,
295 * false if unrecoverable problems were encountered.
296 *****************************************************************************/
297bool
298ixgb_init_hw(struct ixgb_hw *hw)
299{
300 u32 i;
301 u32 ctrl_reg;
302 bool status;
303
304 ENTER();
305
306 /* Issue a global reset to the MAC. This will reset the chip's
307 * transmit, receive, DMA, and link units. It will not effect
308 * the current PCI configuration. The global reset bit is self-
309 * clearing, and should clear within a microsecond.
310 */
311 pr_debug("Issuing a global reset to MAC\n");
312
313 ctrl_reg = ixgb_mac_reset(hw);
314
315 pr_debug("Issuing an EE reset to MAC\n");
316#ifdef HP_ZX1
317 /* Workaround for 82597EX reset errata */
318 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
319#else
320 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
321#endif
322
323 /* Delay a few ms just to allow the reset to complete */
324 msleep(IXGB_DELAY_AFTER_EE_RESET);
325
326 if (!ixgb_get_eeprom_data(hw))
327 return false;
328
329 /* Use the device id to determine the type of phy/transceiver. */
330 hw->device_id = ixgb_get_ee_device_id(hw);
331 hw->phy_type = ixgb_identify_phy(hw);
332
333 /* Setup the receive addresses.
334 * Receive Address Registers (RARs 0 - 15).
335 */
336 ixgb_init_rx_addrs(hw);
337
338 /*
339 * Check that a valid MAC address has been set.
340 * If it is not valid, we fail hardware init.
341 */
342 if (!mac_addr_valid(hw->curr_mac_addr)) {
343 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
344 return(false);
345 }
346
347 /* tell the routines in this file they can access hardware again */
348 hw->adapter_stopped = false;
349
350 /* Fill in the bus_info structure */
351 ixgb_get_bus_info(hw);
352
353 /* Zero out the Multicast HASH table */
354 pr_debug("Zeroing the MTA\n");
355 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
356 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
357
358 /* Zero out the VLAN Filter Table Array */
359 ixgb_clear_vfta(hw);
360
361 /* Zero all of the hardware counters */
362 ixgb_clear_hw_cntrs(hw);
363
364 /* Call a subroutine to setup flow control. */
365 status = ixgb_setup_fc(hw);
366
367 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
368 ixgb_check_for_link(hw);
369
370 return status;
371}
372
373/******************************************************************************
374 * Initializes receive address filters.
375 *
376 * hw - Struct containing variables accessed by shared code
377 *
378 * Places the MAC address in receive address register 0 and clears the rest
379 * of the receive address registers. Clears the multicast table. Assumes
380 * the receiver is in reset when the routine is called.
381 *****************************************************************************/
382static void
383ixgb_init_rx_addrs(struct ixgb_hw *hw)
384{
385 u32 i;
386
387 ENTER();
388
389 /*
390 * If the current mac address is valid, assume it is a software override
391 * to the permanent address.
392 * Otherwise, use the permanent address from the eeprom.
393 */
394 if (!mac_addr_valid(hw->curr_mac_addr)) {
395
396 /* Get the MAC address from the eeprom for later reference */
397 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
398
399 pr_debug("Keeping Permanent MAC Addr = %pM\n",
400 hw->curr_mac_addr);
401 } else {
402
403 /* Setup the receive address. */
404 pr_debug("Overriding MAC Address in RAR[0]\n");
405 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
406
407 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
408 }
409
410 /* Zero out the other 15 receive addresses. */
411 pr_debug("Clearing RAR[1-15]\n");
412 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
413 /* Write high reg first to disable the AV bit first */
414 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
415 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
416 }
417}
418
419/******************************************************************************
420 * Updates the MAC's list of multicast addresses.
421 *
422 * hw - Struct containing variables accessed by shared code
423 * mc_addr_list - the list of new multicast addresses
424 * mc_addr_count - number of addresses
425 * pad - number of bytes between addresses in the list
426 *
427 * The given list replaces any existing list. Clears the last 15 receive
428 * address registers and the multicast table. Uses receive address registers
429 * for the first 15 multicast addresses, and hashes the rest into the
430 * multicast table.
431 *****************************************************************************/
432void
433ixgb_mc_addr_list_update(struct ixgb_hw *hw,
434 u8 *mc_addr_list,
435 u32 mc_addr_count,
436 u32 pad)
437{
438 u32 hash_value;
439 u32 i;
440 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
441 u8 *mca;
442
443 ENTER();
444
445 /* Set the new number of MC addresses that we are being requested to use. */
446 hw->num_mc_addrs = mc_addr_count;
447
448 /* Clear RAR[1-15] */
449 pr_debug("Clearing RAR[1-15]\n");
450 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
451 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
452 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
453 }
454
455 /* Clear the MTA */
456 pr_debug("Clearing MTA\n");
457 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
458 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
459
460 /* Add the new addresses */
461 mca = mc_addr_list;
462 for (i = 0; i < mc_addr_count; i++) {
463 pr_debug("Adding the multicast addresses:\n");
464 pr_debug("MC Addr #%d = %pM\n", i, mca);
465
466 /* Place this multicast address in the RAR if there is room, *
467 * else put it in the MTA
468 */
469 if (rar_used_count < IXGB_RAR_ENTRIES) {
470 ixgb_rar_set(hw, mca, rar_used_count);
471 pr_debug("Added a multicast address to RAR[%d]\n", i);
472 rar_used_count++;
473 } else {
474 hash_value = ixgb_hash_mc_addr(hw, mca);
475
476 pr_debug("Hash value = 0x%03X\n", hash_value);
477
478 ixgb_mta_set(hw, hash_value);
479 }
480
481 mca += IXGB_ETH_LENGTH_OF_ADDRESS + pad;
482 }
483
484 pr_debug("MC Update Complete\n");
485}
486
487/******************************************************************************
488 * Hashes an address to determine its location in the multicast table
489 *
490 * hw - Struct containing variables accessed by shared code
491 * mc_addr - the multicast address to hash
492 *
493 * Returns:
494 * The hash value
495 *****************************************************************************/
496static u32
497ixgb_hash_mc_addr(struct ixgb_hw *hw,
498 u8 *mc_addr)
499{
500 u32 hash_value = 0;
501
502 ENTER();
503
504 /* The portion of the address that is used for the hash table is
505 * determined by the mc_filter_type setting.
506 */
507 switch (hw->mc_filter_type) {
508 /* [0] [1] [2] [3] [4] [5]
509 * 01 AA 00 12 34 56
510 * LSB MSB - According to H/W docs */
511 case 0:
512 /* [47:36] i.e. 0x563 for above example address */
513 hash_value =
514 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
515 break;
516 case 1: /* [46:35] i.e. 0xAC6 for above example address */
517 hash_value =
518 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
519 break;
520 case 2: /* [45:34] i.e. 0x5D8 for above example address */
521 hash_value =
522 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
523 break;
524 case 3: /* [43:32] i.e. 0x634 for above example address */
525 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
526 break;
527 default:
528 /* Invalid mc_filter_type, what should we do? */
529 pr_debug("MC filter type param set incorrectly\n");
530 ASSERT(0);
531 break;
532 }
533
534 hash_value &= 0xFFF;
535 return hash_value;
536}
537
538/******************************************************************************
539 * Sets the bit in the multicast table corresponding to the hash value.
540 *
541 * hw - Struct containing variables accessed by shared code
542 * hash_value - Multicast address hash value
543 *****************************************************************************/
544static void
545ixgb_mta_set(struct ixgb_hw *hw,
546 u32 hash_value)
547{
548 u32 hash_bit, hash_reg;
549 u32 mta_reg;
550
551 /* The MTA is a register array of 128 32-bit registers.
552 * It is treated like an array of 4096 bits. We want to set
553 * bit BitArray[hash_value]. So we figure out what register
554 * the bit is in, read it, OR in the new bit, then write
555 * back the new value. The register is determined by the
556 * upper 7 bits of the hash value and the bit within that
557 * register are determined by the lower 5 bits of the value.
558 */
559 hash_reg = (hash_value >> 5) & 0x7F;
560 hash_bit = hash_value & 0x1F;
561
562 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
563
564 mta_reg |= (1 << hash_bit);
565
566 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
567}
568
569/******************************************************************************
570 * Puts an ethernet address into a receive address register.
571 *
572 * hw - Struct containing variables accessed by shared code
573 * addr - Address to put into receive address register
574 * index - Receive address register to write
575 *****************************************************************************/
576void
577ixgb_rar_set(struct ixgb_hw *hw,
578 u8 *addr,
579 u32 index)
580{
581 u32 rar_low, rar_high;
582
583 ENTER();
584
585 /* HW expects these in little endian so we reverse the byte order
586 * from network order (big endian) to little endian
587 */
588 rar_low = ((u32) addr[0] |
589 ((u32)addr[1] << 8) |
590 ((u32)addr[2] << 16) |
591 ((u32)addr[3] << 24));
592
593 rar_high = ((u32) addr[4] |
594 ((u32)addr[5] << 8) |
595 IXGB_RAH_AV);
596
597 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
598 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
599}
600
601/******************************************************************************
602 * Writes a value to the specified offset in the VLAN filter table.
603 *
604 * hw - Struct containing variables accessed by shared code
605 * offset - Offset in VLAN filer table to write
606 * value - Value to write into VLAN filter table
607 *****************************************************************************/
608void
609ixgb_write_vfta(struct ixgb_hw *hw,
610 u32 offset,
611 u32 value)
612{
613 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
614}
615
616/******************************************************************************
617 * Clears the VLAN filer table
618 *
619 * hw - Struct containing variables accessed by shared code
620 *****************************************************************************/
621static void
622ixgb_clear_vfta(struct ixgb_hw *hw)
623{
624 u32 offset;
625
626 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
627 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
628}
629
630/******************************************************************************
631 * Configures the flow control settings based on SW configuration.
632 *
633 * hw - Struct containing variables accessed by shared code
634 *****************************************************************************/
635
636static bool
637ixgb_setup_fc(struct ixgb_hw *hw)
638{
639 u32 ctrl_reg;
640 u32 pap_reg = 0; /* by default, assume no pause time */
641 bool status = true;
642
643 ENTER();
644
645 /* Get the current control reg 0 settings */
646 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
647
648 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
649 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
650
651 /* The possible values of the "flow_control" parameter are:
652 * 0: Flow control is completely disabled
653 * 1: Rx flow control is enabled (we can receive pause frames
654 * but not send pause frames).
655 * 2: Tx flow control is enabled (we can send pause frames
656 * but we do not support receiving pause frames).
657 * 3: Both Rx and TX flow control (symmetric) are enabled.
658 * other: Invalid.
659 */
660 switch (hw->fc.type) {
661 case ixgb_fc_none: /* 0 */
662 /* Set CMDC bit to disable Rx Flow control */
663 ctrl_reg |= (IXGB_CTRL0_CMDC);
664 break;
665 case ixgb_fc_rx_pause: /* 1 */
666 /* RX Flow control is enabled, and TX Flow control is
667 * disabled.
668 */
669 ctrl_reg |= (IXGB_CTRL0_RPE);
670 break;
671 case ixgb_fc_tx_pause: /* 2 */
672 /* TX Flow control is enabled, and RX Flow control is
673 * disabled, by a software over-ride.
674 */
675 ctrl_reg |= (IXGB_CTRL0_TPE);
676 pap_reg = hw->fc.pause_time;
677 break;
678 case ixgb_fc_full: /* 3 */
679 /* Flow control (both RX and TX) is enabled by a software
680 * over-ride.
681 */
682 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
683 pap_reg = hw->fc.pause_time;
684 break;
685 default:
686 /* We should never get here. The value should be 0-3. */
687 pr_debug("Flow control param set incorrectly\n");
688 ASSERT(0);
689 break;
690 }
691
692 /* Write the new settings */
693 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
694
695 if (pap_reg != 0)
696 IXGB_WRITE_REG(hw, PAP, pap_reg);
697
698 /* Set the flow control receive threshold registers. Normally,
699 * these registers will be set to a default threshold that may be
700 * adjusted later by the driver's runtime code. However, if the
701 * ability to transmit pause frames in not enabled, then these
702 * registers will be set to 0.
703 */
704 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
705 IXGB_WRITE_REG(hw, FCRTL, 0);
706 IXGB_WRITE_REG(hw, FCRTH, 0);
707 } else {
708 /* We need to set up the Receive Threshold high and low water
709 * marks as well as (optionally) enabling the transmission of XON
710 * frames. */
711 if (hw->fc.send_xon) {
712 IXGB_WRITE_REG(hw, FCRTL,
713 (hw->fc.low_water | IXGB_FCRTL_XONE));
714 } else {
715 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
716 }
717 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
718 }
719 return status;
720}
721
722/******************************************************************************
723 * Reads a word from a device over the Management Data Interface (MDI) bus.
724 * This interface is used to manage Physical layer devices.
725 *
726 * hw - Struct containing variables accessed by hw code
727 * reg_address - Offset of device register being read.
728 * phy_address - Address of device on MDI.
729 *
730 * Returns: Data word (16 bits) from MDI device.
731 *
732 * The 82597EX has support for several MDI access methods. This routine
733 * uses the new protocol MDI Single Command and Address Operation.
734 * This requires that first an address cycle command is sent, followed by a
735 * read command.
736 *****************************************************************************/
737static u16
738ixgb_read_phy_reg(struct ixgb_hw *hw,
739 u32 reg_address,
740 u32 phy_address,
741 u32 device_type)
742{
743 u32 i;
744 u32 data;
745 u32 command = 0;
746
747 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
748 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
749 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
750
751 /* Setup and write the address cycle command */
752 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
753 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
754 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
755 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
756
757 IXGB_WRITE_REG(hw, MSCA, command);
758
759 /**************************************************************
760 ** Check every 10 usec to see if the address cycle completed
761 ** The COMMAND bit will clear when the operation is complete.
762 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
763 ** from the CPU Write to the Ready bit assertion.
764 **************************************************************/
765
766 for (i = 0; i < 10; i++)
767 {
768 udelay(10);
769
770 command = IXGB_READ_REG(hw, MSCA);
771
772 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
773 break;
774 }
775
776 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
777
778 /* Address cycle complete, setup and write the read command */
779 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
780 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
781 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
782 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
783
784 IXGB_WRITE_REG(hw, MSCA, command);
785
786 /**************************************************************
787 ** Check every 10 usec to see if the read command completed
788 ** The COMMAND bit will clear when the operation is complete.
789 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
790 ** from the CPU Write to the Ready bit assertion.
791 **************************************************************/
792
793 for (i = 0; i < 10; i++)
794 {
795 udelay(10);
796
797 command = IXGB_READ_REG(hw, MSCA);
798
799 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
800 break;
801 }
802
803 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
804
805 /* Operation is complete, get the data from the MDIO Read/Write Data
806 * register and return.
807 */
808 data = IXGB_READ_REG(hw, MSRWD);
809 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
810 return((u16) data);
811}
812
813/******************************************************************************
814 * Writes a word to a device over the Management Data Interface (MDI) bus.
815 * This interface is used to manage Physical layer devices.
816 *
817 * hw - Struct containing variables accessed by hw code
818 * reg_address - Offset of device register being read.
819 * phy_address - Address of device on MDI.
820 * device_type - Also known as the Device ID or DID.
821 * data - 16-bit value to be written
822 *
823 * Returns: void.
824 *
825 * The 82597EX has support for several MDI access methods. This routine
826 * uses the new protocol MDI Single Command and Address Operation.
827 * This requires that first an address cycle command is sent, followed by a
828 * write command.
829 *****************************************************************************/
830static void
831ixgb_write_phy_reg(struct ixgb_hw *hw,
832 u32 reg_address,
833 u32 phy_address,
834 u32 device_type,
835 u16 data)
836{
837 u32 i;
838 u32 command = 0;
839
840 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
841 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
842 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
843
844 /* Put the data in the MDIO Read/Write Data register */
845 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
846
847 /* Setup and write the address cycle command */
848 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
849 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
850 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
851 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
852
853 IXGB_WRITE_REG(hw, MSCA, command);
854
855 /**************************************************************
856 ** Check every 10 usec to see if the address cycle completed
857 ** The COMMAND bit will clear when the operation is complete.
858 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
859 ** from the CPU Write to the Ready bit assertion.
860 **************************************************************/
861
862 for (i = 0; i < 10; i++)
863 {
864 udelay(10);
865
866 command = IXGB_READ_REG(hw, MSCA);
867
868 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
869 break;
870 }
871
872 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
873
874 /* Address cycle complete, setup and write the write command */
875 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
876 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
877 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
878 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
879
880 IXGB_WRITE_REG(hw, MSCA, command);
881
882 /**************************************************************
883 ** Check every 10 usec to see if the read command completed
884 ** The COMMAND bit will clear when the operation is complete.
885 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
886 ** from the CPU Write to the Ready bit assertion.
887 **************************************************************/
888
889 for (i = 0; i < 10; i++)
890 {
891 udelay(10);
892
893 command = IXGB_READ_REG(hw, MSCA);
894
895 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
896 break;
897 }
898
899 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
900
901 /* Operation is complete, return. */
902}
903
904/******************************************************************************
905 * Checks to see if the link status of the hardware has changed.
906 *
907 * hw - Struct containing variables accessed by hw code
908 *
909 * Called by any function that needs to check the link status of the adapter.
910 *****************************************************************************/
911void
912ixgb_check_for_link(struct ixgb_hw *hw)
913{
914 u32 status_reg;
915 u32 xpcss_reg;
916
917 ENTER();
918
919 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
920 status_reg = IXGB_READ_REG(hw, STATUS);
921
922 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
923 (status_reg & IXGB_STATUS_LU)) {
924 hw->link_up = true;
925 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
926 (status_reg & IXGB_STATUS_LU)) {
927 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
928 hw->link_up = ixgb_link_reset(hw);
929 } else {
930 /*
931 * 82597EX errata. Since the lane deskew problem may prevent
932 * link, reset the link before reporting link down.
933 */
934 hw->link_up = ixgb_link_reset(hw);
935 }
936 /* Anything else for 10 Gig?? */
937}
938
939/******************************************************************************
940 * Check for a bad link condition that may have occurred.
941 * The indication is that the RFC / LFC registers may be incrementing
942 * continually. A full adapter reset is required to recover.
943 *
944 * hw - Struct containing variables accessed by hw code
945 *
946 * Called by any function that needs to check the link status of the adapter.
947 *****************************************************************************/
948bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
949{
950 u32 newLFC, newRFC;
951 bool bad_link_returncode = false;
952
953 if (hw->phy_type == ixgb_phy_type_txn17401) {
954 newLFC = IXGB_READ_REG(hw, LFC);
955 newRFC = IXGB_READ_REG(hw, RFC);
956 if ((hw->lastLFC + 250 < newLFC)
957 || (hw->lastRFC + 250 < newRFC)) {
958 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
959 bad_link_returncode = true;
960 }
961 hw->lastLFC = newLFC;
962 hw->lastRFC = newRFC;
963 }
964
965 return bad_link_returncode;
966}
967
968/******************************************************************************
969 * Clears all hardware statistics counters.
970 *
971 * hw - Struct containing variables accessed by shared code
972 *****************************************************************************/
973static void
974ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
975{
976 volatile u32 temp_reg;
977
978 ENTER();
979
980 /* if we are stopped or resetting exit gracefully */
981 if (hw->adapter_stopped) {
982 pr_debug("Exiting because the adapter is stopped!!!\n");
983 return;
984 }
985
986 temp_reg = IXGB_READ_REG(hw, TPRL);
987 temp_reg = IXGB_READ_REG(hw, TPRH);
988 temp_reg = IXGB_READ_REG(hw, GPRCL);
989 temp_reg = IXGB_READ_REG(hw, GPRCH);
990 temp_reg = IXGB_READ_REG(hw, BPRCL);
991 temp_reg = IXGB_READ_REG(hw, BPRCH);
992 temp_reg = IXGB_READ_REG(hw, MPRCL);
993 temp_reg = IXGB_READ_REG(hw, MPRCH);
994 temp_reg = IXGB_READ_REG(hw, UPRCL);
995 temp_reg = IXGB_READ_REG(hw, UPRCH);
996 temp_reg = IXGB_READ_REG(hw, VPRCL);
997 temp_reg = IXGB_READ_REG(hw, VPRCH);
998 temp_reg = IXGB_READ_REG(hw, JPRCL);
999 temp_reg = IXGB_READ_REG(hw, JPRCH);
1000 temp_reg = IXGB_READ_REG(hw, GORCL);
1001 temp_reg = IXGB_READ_REG(hw, GORCH);
1002 temp_reg = IXGB_READ_REG(hw, TORL);
1003 temp_reg = IXGB_READ_REG(hw, TORH);
1004 temp_reg = IXGB_READ_REG(hw, RNBC);
1005 temp_reg = IXGB_READ_REG(hw, RUC);
1006 temp_reg = IXGB_READ_REG(hw, ROC);
1007 temp_reg = IXGB_READ_REG(hw, RLEC);
1008 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1009 temp_reg = IXGB_READ_REG(hw, ICBC);
1010 temp_reg = IXGB_READ_REG(hw, ECBC);
1011 temp_reg = IXGB_READ_REG(hw, MPC);
1012 temp_reg = IXGB_READ_REG(hw, TPTL);
1013 temp_reg = IXGB_READ_REG(hw, TPTH);
1014 temp_reg = IXGB_READ_REG(hw, GPTCL);
1015 temp_reg = IXGB_READ_REG(hw, GPTCH);
1016 temp_reg = IXGB_READ_REG(hw, BPTCL);
1017 temp_reg = IXGB_READ_REG(hw, BPTCH);
1018 temp_reg = IXGB_READ_REG(hw, MPTCL);
1019 temp_reg = IXGB_READ_REG(hw, MPTCH);
1020 temp_reg = IXGB_READ_REG(hw, UPTCL);
1021 temp_reg = IXGB_READ_REG(hw, UPTCH);
1022 temp_reg = IXGB_READ_REG(hw, VPTCL);
1023 temp_reg = IXGB_READ_REG(hw, VPTCH);
1024 temp_reg = IXGB_READ_REG(hw, JPTCL);
1025 temp_reg = IXGB_READ_REG(hw, JPTCH);
1026 temp_reg = IXGB_READ_REG(hw, GOTCL);
1027 temp_reg = IXGB_READ_REG(hw, GOTCH);
1028 temp_reg = IXGB_READ_REG(hw, TOTL);
1029 temp_reg = IXGB_READ_REG(hw, TOTH);
1030 temp_reg = IXGB_READ_REG(hw, DC);
1031 temp_reg = IXGB_READ_REG(hw, PLT64C);
1032 temp_reg = IXGB_READ_REG(hw, TSCTC);
1033 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1034 temp_reg = IXGB_READ_REG(hw, IBIC);
1035 temp_reg = IXGB_READ_REG(hw, RFC);
1036 temp_reg = IXGB_READ_REG(hw, LFC);
1037 temp_reg = IXGB_READ_REG(hw, PFRC);
1038 temp_reg = IXGB_READ_REG(hw, PFTC);
1039 temp_reg = IXGB_READ_REG(hw, MCFRC);
1040 temp_reg = IXGB_READ_REG(hw, MCFTC);
1041 temp_reg = IXGB_READ_REG(hw, XONRXC);
1042 temp_reg = IXGB_READ_REG(hw, XONTXC);
1043 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1044 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1045 temp_reg = IXGB_READ_REG(hw, RJC);
1046}
1047
1048/******************************************************************************
1049 * Turns on the software controllable LED
1050 *
1051 * hw - Struct containing variables accessed by shared code
1052 *****************************************************************************/
1053void
1054ixgb_led_on(struct ixgb_hw *hw)
1055{
1056 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1057
1058 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1059 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1060 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1061}
1062
1063/******************************************************************************
1064 * Turns off the software controllable LED
1065 *
1066 * hw - Struct containing variables accessed by shared code
1067 *****************************************************************************/
1068void
1069ixgb_led_off(struct ixgb_hw *hw)
1070{
1071 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1072
1073 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1074 ctrl0_reg |= IXGB_CTRL0_SDP0;
1075 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1076}
1077
1078/******************************************************************************
1079 * Gets the current PCI bus type, speed, and width of the hardware
1080 *
1081 * hw - Struct containing variables accessed by shared code
1082 *****************************************************************************/
1083static void
1084ixgb_get_bus_info(struct ixgb_hw *hw)
1085{
1086 u32 status_reg;
1087
1088 status_reg = IXGB_READ_REG(hw, STATUS);
1089
1090 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1091 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1092
1093 if (hw->bus.type == ixgb_bus_type_pci) {
1094 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1095 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1096 } else {
1097 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1098 case IXGB_STATUS_PCIX_SPD_66:
1099 hw->bus.speed = ixgb_bus_speed_66;
1100 break;
1101 case IXGB_STATUS_PCIX_SPD_100:
1102 hw->bus.speed = ixgb_bus_speed_100;
1103 break;
1104 case IXGB_STATUS_PCIX_SPD_133:
1105 hw->bus.speed = ixgb_bus_speed_133;
1106 break;
1107 default:
1108 hw->bus.speed = ixgb_bus_speed_reserved;
1109 break;
1110 }
1111 }
1112
1113 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1114 ixgb_bus_width_64 : ixgb_bus_width_32;
1115}
1116
1117/******************************************************************************
1118 * Tests a MAC address to ensure it is a valid Individual Address
1119 *
1120 * mac_addr - pointer to MAC address.
1121 *
1122 *****************************************************************************/
1123static bool
1124mac_addr_valid(u8 *mac_addr)
1125{
1126 bool is_valid = true;
1127 ENTER();
1128
1129 /* Make sure it is not a multicast address */
1130 if (is_multicast_ether_addr(mac_addr)) {
1131 pr_debug("MAC address is multicast\n");
1132 is_valid = false;
1133 }
1134 /* Not a broadcast address */
1135 else if (is_broadcast_ether_addr(mac_addr)) {
1136 pr_debug("MAC address is broadcast\n");
1137 is_valid = false;
1138 }
1139 /* Reject the zero address */
1140 else if (is_zero_ether_addr(mac_addr)) {
1141 pr_debug("MAC address is all zeros\n");
1142 is_valid = false;
1143 }
1144 return is_valid;
1145}
1146
1147/******************************************************************************
1148 * Resets the 10GbE link. Waits the settle time and returns the state of
1149 * the link.
1150 *
1151 * hw - Struct containing variables accessed by shared code
1152 *****************************************************************************/
1153static bool
1154ixgb_link_reset(struct ixgb_hw *hw)
1155{
1156 bool link_status = false;
1157 u8 wait_retries = MAX_RESET_ITERATIONS;
1158 u8 lrst_retries = MAX_RESET_ITERATIONS;
1159
1160 do {
1161 /* Reset the link */
1162 IXGB_WRITE_REG(hw, CTRL0,
1163 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1164
1165 /* Wait for link-up and lane re-alignment */
1166 do {
1167 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1168 link_status =
1169 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1170 && (IXGB_READ_REG(hw, XPCSS) &
1171 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1172 } while (!link_status && --wait_retries);
1173
1174 } while (!link_status && --lrst_retries);
1175
1176 return link_status;
1177}
1178
1179/******************************************************************************
1180 * Resets the 10GbE optics module.
1181 *
1182 * hw - Struct containing variables accessed by shared code
1183 *****************************************************************************/
1184static void
1185ixgb_optics_reset(struct ixgb_hw *hw)
1186{
1187 if (hw->phy_type == ixgb_phy_type_txn17401) {
1188 u16 mdio_reg;
1189
1190 ixgb_write_phy_reg(hw,
1191 MDIO_CTRL1,
1192 IXGB_PHY_ADDRESS,
1193 MDIO_MMD_PMAPMD,
1194 MDIO_CTRL1_RESET);
1195
1196 mdio_reg = ixgb_read_phy_reg(hw,
1197 MDIO_CTRL1,
1198 IXGB_PHY_ADDRESS,
1199 MDIO_MMD_PMAPMD);
1200 }
1201}
1202
1203/******************************************************************************
1204 * Resets the 10GbE optics module for Sun variant NIC.
1205 *
1206 * hw - Struct containing variables accessed by shared code
1207 *****************************************************************************/
1208
1209#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1210#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1211#define IXGB_BCM8704_USER_CTRL_REG 0xC800
1212#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1213#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1214#define IXGB_SUN_PHY_ADDRESS 0x0000
1215#define IXGB_SUN_PHY_RESET_DELAY 305
1216
1217static void
1218ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1219{
1220 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1221 ctrl &= ~IXGB_CTRL0_SDP2;
1222 ctrl |= IXGB_CTRL0_SDP3;
1223 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1224 IXGB_WRITE_FLUSH(hw);
1225
1226 /* SerDes needs extra delay */
1227 msleep(IXGB_SUN_PHY_RESET_DELAY);
1228
1229 /* Broadcom 7408L configuration */
1230 /* Reference clock config */
1231 ixgb_write_phy_reg(hw,
1232 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1233 IXGB_SUN_PHY_ADDRESS,
1234 IXGB_BCM8704_USER_DEV3_ADDR,
1235 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1236 /* we must read the registers twice */
1237 ixgb_read_phy_reg(hw,
1238 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1239 IXGB_SUN_PHY_ADDRESS,
1240 IXGB_BCM8704_USER_DEV3_ADDR);
1241 ixgb_read_phy_reg(hw,
1242 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1243 IXGB_SUN_PHY_ADDRESS,
1244 IXGB_BCM8704_USER_DEV3_ADDR);
1245
1246 ixgb_write_phy_reg(hw,
1247 IXGB_BCM8704_USER_CTRL_REG,
1248 IXGB_SUN_PHY_ADDRESS,
1249 IXGB_BCM8704_USER_DEV3_ADDR,
1250 IXGB_BCM8704_USER_CTRL_REG_VAL);
1251 ixgb_read_phy_reg(hw,
1252 IXGB_BCM8704_USER_CTRL_REG,
1253 IXGB_SUN_PHY_ADDRESS,
1254 IXGB_BCM8704_USER_DEV3_ADDR);
1255 ixgb_read_phy_reg(hw,
1256 IXGB_BCM8704_USER_CTRL_REG,
1257 IXGB_SUN_PHY_ADDRESS,
1258 IXGB_BCM8704_USER_DEV3_ADDR);
1259
1260 /* SerDes needs extra delay */
1261 msleep(IXGB_SUN_PHY_RESET_DELAY);
1262}