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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2022 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../ipa.h"
8#include "../ipa_reg.h"
9
10static const u32 reg_comp_cfg_fmask[] = {
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
28 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
29 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
30 [GENQMB_AOOOWR] = BIT(20),
31 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
32 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22),
33 /* Bits 25-29 reserved */
34 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
35 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
36};
37
38REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
39
40static const u32 reg_clkon_cfg_fmask[] = {
41 [CLKON_RX] = BIT(0),
42 [CLKON_PROC] = BIT(1),
43 [TX_WRAPPER] = BIT(2),
44 [CLKON_MISC] = BIT(3),
45 [RAM_ARB] = BIT(4),
46 [FTCH_HPS] = BIT(5),
47 [FTCH_DPS] = BIT(6),
48 [CLKON_HPS] = BIT(7),
49 [CLKON_DPS] = BIT(8),
50 [RX_HPS_CMDQS] = BIT(9),
51 [HPS_DPS_CMDQS] = BIT(10),
52 [DPS_TX_CMDQS] = BIT(11),
53 [RSRC_MNGR] = BIT(12),
54 [CTX_HANDLER] = BIT(13),
55 [ACK_MNGR] = BIT(14),
56 [D_DCPH] = BIT(15),
57 [H_DCPH] = BIT(16),
58 [CLKON_DCMP] = BIT(17),
59 [NTF_TX_CMDQS] = BIT(18),
60 [CLKON_TX_0] = BIT(19),
61 [CLKON_TX_1] = BIT(20),
62 [CLKON_FNR] = BIT(21),
63 [QSB2AXI_CMDQ_L] = BIT(22),
64 [AGGR_WRAPPER] = BIT(23),
65 [RAM_SLAVEWAY] = BIT(24),
66 [CLKON_QMB] = BIT(25),
67 [WEIGHT_ARB] = BIT(26),
68 [GSI_IF] = BIT(27),
69 [CLKON_GLOBAL] = BIT(28),
70 [GLOBAL_2X_CLK] = BIT(29),
71 [DPL_FIFO] = BIT(30),
72 [DRBIP] = BIT(31),
73};
74
75REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
76
77static const u32 reg_route_fmask[] = {
78 [ROUTE_DIS] = BIT(0),
79 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
80 [ROUTE_DEF_HDR_TABLE] = BIT(6),
81 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
82 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
83 /* Bits 22-23 reserved */
84 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
85 /* Bits 25-31 reserved */
86};
87
88REG_FIELDS(ROUTE, route, 0x00000048);
89
90static const u32 reg_shared_mem_size_fmask[] = {
91 [MEM_SIZE] = GENMASK(15, 0),
92 [MEM_BADDR] = GENMASK(31, 16),
93};
94
95REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
96
97static const u32 reg_qsb_max_writes_fmask[] = {
98 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
99 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
100 /* Bits 8-31 reserved */
101};
102
103REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
104
105static const u32 reg_qsb_max_reads_fmask[] = {
106 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
107 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
108 /* Bits 8-15 reserved */
109 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
110 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
111};
112
113REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
114
115static const u32 reg_filt_rout_hash_en_fmask[] = {
116 [IPV6_ROUTER_HASH] = BIT(0),
117 /* Bits 1-3 reserved */
118 [IPV6_FILTER_HASH] = BIT(4),
119 /* Bits 5-7 reserved */
120 [IPV4_ROUTER_HASH] = BIT(8),
121 /* Bits 9-11 reserved */
122 [IPV4_FILTER_HASH] = BIT(12),
123 /* Bits 13-31 reserved */
124};
125
126REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
127
128static const u32 reg_filt_rout_hash_flush_fmask[] = {
129 [IPV6_ROUTER_HASH] = BIT(0),
130 /* Bits 1-3 reserved */
131 [IPV6_FILTER_HASH] = BIT(4),
132 /* Bits 5-7 reserved */
133 [IPV4_ROUTER_HASH] = BIT(8),
134 /* Bits 9-11 reserved */
135 [IPV4_FILTER_HASH] = BIT(12),
136 /* Bits 13-31 reserved */
137};
138
139REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
140
141/* Valid bits defined by ipa->available */
142REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
143
144static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
145 [IPA_BASE_ADDR] = GENMASK(17, 0),
146 /* Bits 18-31 reserved */
147};
148
149/* Offset must be a multiple of 8 */
150REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
151
152/* Valid bits defined by ipa->available */
153REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
154
155static const u32 reg_ipa_tx_cfg_fmask[] = {
156 /* Bits 0-1 reserved */
157 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
158 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
159 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
160 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
161 [PA_MASK_EN] = BIT(12),
162 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
163 [DUAL_TX_ENABLE] = BIT(17),
164 [SSPND_PA_NO_START_STATE] = BIT(18),
165 /* Bits 19-31 reserved */
166};
167
168REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
169
170static const u32 reg_flavor_0_fmask[] = {
171 [MAX_PIPES] = GENMASK(3, 0),
172 /* Bits 4-7 reserved */
173 [MAX_CONS_PIPES] = GENMASK(12, 8),
174 /* Bits 13-15 reserved */
175 [MAX_PROD_PIPES] = GENMASK(20, 16),
176 /* Bits 21-23 reserved */
177 [PROD_LOWEST] = GENMASK(27, 24),
178 /* Bits 28-31 reserved */
179};
180
181REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
182
183static const u32 reg_idle_indication_cfg_fmask[] = {
184 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
185 [CONST_NON_IDLE_ENABLE] = BIT(16),
186 /* Bits 17-31 reserved */
187};
188
189REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
190
191static const u32 reg_qtime_timestamp_cfg_fmask[] = {
192 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
193 /* Bits 5-6 reserved */
194 [DPL_TIMESTAMP_SEL] = BIT(7),
195 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
196 /* Bits 13-15 reserved */
197 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
198 /* Bits 21-31 reserved */
199};
200
201REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
202
203static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
204 [DIV_VALUE] = GENMASK(8, 0),
205 /* Bits 9-30 reserved */
206 [DIV_ENABLE] = BIT(31),
207};
208
209REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
210
211static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
212 [PULSE_GRAN_0] = GENMASK(2, 0),
213 [PULSE_GRAN_1] = GENMASK(5, 3),
214 [PULSE_GRAN_2] = GENMASK(8, 6),
215};
216
217REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
218
219static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
220 [X_MIN_LIM] = GENMASK(5, 0),
221 /* Bits 6-7 reserved */
222 [X_MAX_LIM] = GENMASK(13, 8),
223 /* Bits 14-15 reserved */
224 [Y_MIN_LIM] = GENMASK(21, 16),
225 /* Bits 22-23 reserved */
226 [Y_MAX_LIM] = GENMASK(29, 24),
227 /* Bits 30-31 reserved */
228};
229
230REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
231 0x00000400, 0x0020);
232
233static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
234 [X_MIN_LIM] = GENMASK(5, 0),
235 /* Bits 6-7 reserved */
236 [X_MAX_LIM] = GENMASK(13, 8),
237 /* Bits 14-15 reserved */
238 [Y_MIN_LIM] = GENMASK(21, 16),
239 /* Bits 22-23 reserved */
240 [Y_MAX_LIM] = GENMASK(29, 24),
241 /* Bits 30-31 reserved */
242};
243
244REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
245 0x00000404, 0x0020);
246
247static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
248 [X_MIN_LIM] = GENMASK(5, 0),
249 /* Bits 6-7 reserved */
250 [X_MAX_LIM] = GENMASK(13, 8),
251 /* Bits 14-15 reserved */
252 [Y_MIN_LIM] = GENMASK(21, 16),
253 /* Bits 22-23 reserved */
254 [Y_MAX_LIM] = GENMASK(29, 24),
255 /* Bits 30-31 reserved */
256};
257
258REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
259 0x00000500, 0x0020);
260
261static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
262 [X_MIN_LIM] = GENMASK(5, 0),
263 /* Bits 6-7 reserved */
264 [X_MAX_LIM] = GENMASK(13, 8),
265 /* Bits 14-15 reserved */
266 [Y_MIN_LIM] = GENMASK(21, 16),
267 /* Bits 22-23 reserved */
268 [Y_MAX_LIM] = GENMASK(29, 24),
269 /* Bits 30-31 reserved */
270};
271
272REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
273 0x00000504, 0x0020);
274
275static const u32 reg_endp_init_cfg_fmask[] = {
276 [FRAG_OFFLOAD_EN] = BIT(0),
277 [CS_OFFLOAD_EN] = GENMASK(2, 1),
278 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
279 /* Bit 7 reserved */
280 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
281 /* Bits 9-31 reserved */
282};
283
284REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
285
286static const u32 reg_endp_init_nat_fmask[] = {
287 [NAT_EN] = GENMASK(1, 0),
288 /* Bits 2-31 reserved */
289};
290
291REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
292
293static const u32 reg_endp_init_hdr_fmask[] = {
294 [HDR_LEN] = GENMASK(5, 0),
295 [HDR_OFST_METADATA_VALID] = BIT(6),
296 [HDR_OFST_METADATA] = GENMASK(12, 7),
297 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
298 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
299 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
300 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
301 [HDR_LEN_MSB] = GENMASK(29, 28),
302 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
303};
304
305REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
306
307static const u32 reg_endp_init_hdr_ext_fmask[] = {
308 [HDR_ENDIANNESS] = BIT(0),
309 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
310 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
311 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
312 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
313 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
314 /* Bits 14-15 reserved */
315 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
316 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
317 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
318 /* Bits 22-31 reserved */
319};
320
321REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
322
323REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
324 0x00000818, 0x0070);
325
326static const u32 reg_endp_init_mode_fmask[] = {
327 [ENDP_MODE] = GENMASK(2, 0),
328 [DCPH_ENABLE] = BIT(3),
329 [DEST_PIPE_INDEX] = GENMASK(8, 4),
330 /* Bits 9-11 reserved */
331 [BYTE_THRESHOLD] = GENMASK(27, 12),
332 [PIPE_REPLICATION_EN] = BIT(28),
333 [PAD_EN] = BIT(29),
334 [DRBIP_ACL_ENABLE] = BIT(30),
335 /* Bit 31 reserved */
336};
337
338REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
339
340static const u32 reg_endp_init_aggr_fmask[] = {
341 [AGGR_EN] = GENMASK(1, 0),
342 [AGGR_TYPE] = GENMASK(4, 2),
343 [BYTE_LIMIT] = GENMASK(10, 5),
344 /* Bit 11 reserved */
345 [TIME_LIMIT] = GENMASK(16, 12),
346 [PKT_LIMIT] = GENMASK(22, 17),
347 [SW_EOF_ACTIVE] = BIT(23),
348 [FORCE_CLOSE] = BIT(24),
349 /* Bit 25 reserved */
350 [HARD_BYTE_LIMIT_EN] = BIT(26),
351 [AGGR_GRAN_SEL] = BIT(27),
352 /* Bits 28-31 reserved */
353};
354
355REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
356
357static const u32 reg_endp_init_hol_block_en_fmask[] = {
358 [HOL_BLOCK_EN] = BIT(0),
359 /* Bits 1-31 reserved */
360};
361
362REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
363 0x0000082c, 0x0070);
364
365static const u32 reg_endp_init_hol_block_timer_fmask[] = {
366 [TIMER_LIMIT] = GENMASK(4, 0),
367 /* Bits 5-7 reserved */
368 [TIMER_GRAN_SEL] = BIT(8),
369 /* Bits 9-31 reserved */
370};
371
372REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
373 0x00000830, 0x0070);
374
375static const u32 reg_endp_init_deaggr_fmask[] = {
376 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
377 [SYSPIPE_ERR_DETECTION] = BIT(6),
378 [PACKET_OFFSET_VALID] = BIT(7),
379 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
380 [IGNORE_MIN_PKT_ERR] = BIT(14),
381 /* Bit 15 reserved */
382 [MAX_PACKET_LEN] = GENMASK(31, 16),
383};
384
385REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
386
387static const u32 reg_endp_init_rsrc_grp_fmask[] = {
388 [ENDP_RSRC_GRP] = GENMASK(1, 0),
389 /* Bits 2-31 reserved */
390};
391
392REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
393
394static const u32 reg_endp_init_seq_fmask[] = {
395 [SEQ_TYPE] = GENMASK(7, 0),
396 /* Bits 8-31 reserved */
397};
398
399REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
400
401static const u32 reg_endp_status_fmask[] = {
402 [STATUS_EN] = BIT(0),
403 [STATUS_ENDP] = GENMASK(5, 1),
404 /* Bits 6-8 reserved */
405 [STATUS_PKT_SUPPRESS] = BIT(9),
406 /* Bits 10-31 reserved */
407};
408
409REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
410
411static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
412 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
413 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
414 [FILTER_HASH_MSK_DST_IP] = BIT(2),
415 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
416 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
417 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
418 [FILTER_HASH_MSK_METADATA] = BIT(6),
419 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
420 /* Bits 7-15 reserved */
421 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
422 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
423 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
424 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
425 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
426 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
427 [ROUTER_HASH_MSK_METADATA] = BIT(22),
428 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16),
429 /* Bits 23-31 reserved */
430};
431
432REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
433 0x0000085c, 0x0070);
434
435/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
436REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
437
438/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
439REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
440
441/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
442REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
443
444static const u32 reg_ipa_irq_uc_fmask[] = {
445 [UC_INTR] = BIT(0),
446 /* Bits 1-31 reserved */
447};
448
449REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
450
451/* Valid bits defined by ipa->available */
452REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
453 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
454
455/* Valid bits defined by ipa->available */
456REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
457 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
458
459/* Valid bits defined by ipa->available */
460REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
461 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);
462
463static const struct reg *reg_array[] = {
464 [COMP_CFG] = ®_comp_cfg,
465 [CLKON_CFG] = ®_clkon_cfg,
466 [ROUTE] = ®_route,
467 [SHARED_MEM_SIZE] = ®_shared_mem_size,
468 [QSB_MAX_WRITES] = ®_qsb_max_writes,
469 [QSB_MAX_READS] = ®_qsb_max_reads,
470 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en,
471 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush,
472 [STATE_AGGR_ACTIVE] = ®_state_aggr_active,
473 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,
474 [AGGR_FORCE_CLOSE] = ®_aggr_force_close,
475 [IPA_TX_CFG] = ®_ipa_tx_cfg,
476 [FLAVOR_0] = ®_flavor_0,
477 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,
478 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,
479 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,
480 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,
481 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,
482 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,
483 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,
484 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,
485 [ENDP_INIT_CFG] = ®_endp_init_cfg,
486 [ENDP_INIT_NAT] = ®_endp_init_nat,
487 [ENDP_INIT_HDR] = ®_endp_init_hdr,
488 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,
489 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,
490 [ENDP_INIT_MODE] = ®_endp_init_mode,
491 [ENDP_INIT_AGGR] = ®_endp_init_aggr,
492 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,
493 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,
494 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,
495 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,
496 [ENDP_INIT_SEQ] = ®_endp_init_seq,
497 [ENDP_STATUS] = ®_endp_status,
498 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg,
499 [IPA_IRQ_STTS] = ®_ipa_irq_stts,
500 [IPA_IRQ_EN] = ®_ipa_irq_en,
501 [IPA_IRQ_CLR] = ®_ipa_irq_clr,
502 [IPA_IRQ_UC] = ®_ipa_irq_uc,
503 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,
504 [IRQ_SUSPEND_EN] = ®_irq_suspend_en,
505 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,
506};
507
508const struct regs ipa_regs_v4_9 = {
509 .reg_count = ARRAY_SIZE(reg_array),
510 .reg = reg_array,
511};