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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
37#include <linux/clocksource.h>
38#include <linux/timecompare.h>
39#include <linux/net_tstamp.h>
40#include <linux/bitops.h>
41#include <linux/if_vlan.h>
42
43struct igb_adapter;
44
45/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
46#define IGB_START_ITR 648
47
48/* TX/RX descriptor defines */
49#define IGB_DEFAULT_TXD 256
50#define IGB_MIN_TXD 80
51#define IGB_MAX_TXD 4096
52
53#define IGB_DEFAULT_RXD 256
54#define IGB_MIN_RXD 80
55#define IGB_MAX_RXD 4096
56
57#define IGB_DEFAULT_ITR 3 /* dynamic */
58#define IGB_MAX_ITR_USECS 10000
59#define IGB_MIN_ITR_USECS 10
60#define NON_Q_VECTORS 1
61#define MAX_Q_VECTORS 8
62
63/* Transmit and receive queues */
64#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
65 (hw->mac.type > e1000_82575 ? 8 : 4))
66#define IGB_ABS_MAX_TX_QUEUES 8
67#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
68
69#define IGB_MAX_VF_MC_ENTRIES 30
70#define IGB_MAX_VF_FUNCTIONS 8
71#define IGB_MAX_VFTA_ENTRIES 128
72
73struct vf_data_storage {
74 unsigned char vf_mac_addresses[ETH_ALEN];
75 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
76 u16 num_vf_mc_hashes;
77 u16 vlans_enabled;
78 u32 flags;
79 unsigned long last_nack;
80 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
81 u16 pf_qos;
82 u16 tx_rate;
83};
84
85#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
86#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
87#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
88#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
89
90/* RX descriptor control thresholds.
91 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
92 * descriptors available in its onboard memory.
93 * Setting this to 0 disables RX descriptor prefetch.
94 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
95 * available in host memory.
96 * If PTHRESH is 0, this should also be 0.
97 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
98 * descriptors until either it has this many to write back, or the
99 * ITR timer expires.
100 */
101#define IGB_RX_PTHRESH 8
102#define IGB_RX_HTHRESH 8
103#define IGB_RX_WTHRESH 1
104#define IGB_TX_PTHRESH 8
105#define IGB_TX_HTHRESH 1
106#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
107 adapter->msix_entries) ? 1 : 16)
108
109/* this is the size past which hardware will drop packets when setting LPE=0 */
110#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
111
112/* Supported Rx Buffer Sizes */
113#define IGB_RXBUFFER_64 64 /* Used for packet split */
114#define IGB_RXBUFFER_128 128 /* Used for packet split */
115#define IGB_RXBUFFER_1024 1024
116#define IGB_RXBUFFER_2048 2048
117#define IGB_RXBUFFER_16384 16384
118
119#define MAX_STD_JUMBO_FRAME_SIZE 9234
120
121/* How many Tx Descriptors do we need to call netif_wake_queue ? */
122#define IGB_TX_QUEUE_WAKE 16
123/* How many Rx Buffers do we bundle into one write to the hardware ? */
124#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
125
126#define AUTO_ALL_MODES 0
127#define IGB_EEPROM_APME 0x0400
128
129#ifndef IGB_MASTER_SLAVE
130/* Switch to override PHY master/slave setting */
131#define IGB_MASTER_SLAVE e1000_ms_hw_default
132#endif
133
134#define IGB_MNG_VLAN_NONE -1
135
136/* wrapper around a pointer to a socket buffer,
137 * so a DMA handle can be stored along with the buffer */
138struct igb_buffer {
139 struct sk_buff *skb;
140 dma_addr_t dma;
141 union {
142 /* TX */
143 struct {
144 unsigned long time_stamp;
145 u16 length;
146 u16 next_to_watch;
147 unsigned int bytecount;
148 u16 gso_segs;
149 u8 tx_flags;
150 u8 mapped_as_page;
151 };
152 /* RX */
153 struct {
154 struct page *page;
155 dma_addr_t page_dma;
156 u16 page_offset;
157 };
158 };
159};
160
161struct igb_tx_queue_stats {
162 u64 packets;
163 u64 bytes;
164 u64 restart_queue;
165 u64 restart_queue2;
166};
167
168struct igb_rx_queue_stats {
169 u64 packets;
170 u64 bytes;
171 u64 drops;
172 u64 csum_err;
173 u64 alloc_failed;
174};
175
176struct igb_q_vector {
177 struct igb_adapter *adapter; /* backlink */
178 struct igb_ring *rx_ring;
179 struct igb_ring *tx_ring;
180 struct napi_struct napi;
181
182 u32 eims_value;
183 u16 cpu;
184
185 u16 itr_val;
186 u8 set_itr;
187 void __iomem *itr_register;
188
189 char name[IFNAMSIZ + 9];
190};
191
192struct igb_ring {
193 struct igb_q_vector *q_vector; /* backlink to q_vector */
194 struct net_device *netdev; /* back pointer to net_device */
195 struct device *dev; /* device pointer for dma mapping */
196 dma_addr_t dma; /* phys address of the ring */
197 void *desc; /* descriptor ring memory */
198 unsigned int size; /* length of desc. ring in bytes */
199 u16 count; /* number of desc. in the ring */
200 u16 next_to_use;
201 u16 next_to_clean;
202 u8 queue_index;
203 u8 reg_idx;
204 void __iomem *head;
205 void __iomem *tail;
206 struct igb_buffer *buffer_info; /* array of buffer info structs */
207
208 unsigned int total_bytes;
209 unsigned int total_packets;
210
211 u32 flags;
212
213 union {
214 /* TX */
215 struct {
216 struct igb_tx_queue_stats tx_stats;
217 struct u64_stats_sync tx_syncp;
218 struct u64_stats_sync tx_syncp2;
219 bool detect_tx_hung;
220 };
221 /* RX */
222 struct {
223 struct igb_rx_queue_stats rx_stats;
224 struct u64_stats_sync rx_syncp;
225 u32 rx_buffer_len;
226 };
227 };
228};
229
230#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
231#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
232
233#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
234
235#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
236
237#define E1000_RX_DESC_ADV(R, i) \
238 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
239#define E1000_TX_DESC_ADV(R, i) \
240 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
241#define E1000_TX_CTXTDESC_ADV(R, i) \
242 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
243
244/* igb_desc_unused - calculate if we have unused descriptors */
245static inline int igb_desc_unused(struct igb_ring *ring)
246{
247 if (ring->next_to_clean > ring->next_to_use)
248 return ring->next_to_clean - ring->next_to_use - 1;
249
250 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
251}
252
253/* board specific private data structure */
254struct igb_adapter {
255 struct timer_list watchdog_timer;
256 struct timer_list phy_info_timer;
257 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
258 u16 mng_vlan_id;
259 u32 bd_number;
260 u32 wol;
261 u32 en_mng_pt;
262 u16 link_speed;
263 u16 link_duplex;
264
265 /* Interrupt Throttle Rate */
266 u32 rx_itr_setting;
267 u32 tx_itr_setting;
268 u16 tx_itr;
269 u16 rx_itr;
270
271 struct work_struct reset_task;
272 struct work_struct watchdog_task;
273 bool fc_autoneg;
274 u8 tx_timeout_factor;
275 struct timer_list blink_timer;
276 unsigned long led_status;
277
278 /* TX */
279 struct igb_ring *tx_ring[16];
280 u32 tx_timeout_count;
281
282 /* RX */
283 struct igb_ring *rx_ring[16];
284 int num_tx_queues;
285 int num_rx_queues;
286
287 u32 max_frame_size;
288 u32 min_frame_size;
289
290 /* OS defined structs */
291 struct net_device *netdev;
292 struct pci_dev *pdev;
293 struct cyclecounter cycles;
294 struct timecounter clock;
295 struct timecompare compare;
296 struct hwtstamp_config hwtstamp_config;
297
298 spinlock_t stats64_lock;
299 struct rtnl_link_stats64 stats64;
300
301 /* structs defined in e1000_hw.h */
302 struct e1000_hw hw;
303 struct e1000_hw_stats stats;
304 struct e1000_phy_info phy_info;
305 struct e1000_phy_stats phy_stats;
306
307 u32 test_icr;
308 struct igb_ring test_tx_ring;
309 struct igb_ring test_rx_ring;
310
311 int msg_enable;
312
313 unsigned int num_q_vectors;
314 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
315 struct msix_entry *msix_entries;
316 u32 eims_enable_mask;
317 u32 eims_other;
318
319 /* to not mess up cache alignment, always add to the bottom */
320 unsigned long state;
321 unsigned int flags;
322 u32 eeprom_wol;
323
324 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
325 u16 tx_ring_count;
326 u16 rx_ring_count;
327 unsigned int vfs_allocated_count;
328 struct vf_data_storage *vf_data;
329 int vf_rate_link_speed;
330 u32 rss_queues;
331 u32 wvbr;
332};
333
334#define IGB_FLAG_HAS_MSI (1 << 0)
335#define IGB_FLAG_DCA_ENABLED (1 << 1)
336#define IGB_FLAG_QUAD_PORT_A (1 << 2)
337#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
338#define IGB_FLAG_DMAC (1 << 4)
339
340/* DMA Coalescing defines */
341#define IGB_MIN_TXPBSIZE 20408
342#define IGB_TX_BUF_4096 4096
343#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
344
345#define IGB_82576_TSYNC_SHIFT 19
346#define IGB_82580_TSYNC_SHIFT 24
347#define IGB_TS_HDR_LEN 16
348enum e1000_state_t {
349 __IGB_TESTING,
350 __IGB_RESETTING,
351 __IGB_DOWN
352};
353
354enum igb_boards {
355 board_82575,
356};
357
358extern char igb_driver_name[];
359extern char igb_driver_version[];
360
361extern int igb_up(struct igb_adapter *);
362extern void igb_down(struct igb_adapter *);
363extern void igb_reinit_locked(struct igb_adapter *);
364extern void igb_reset(struct igb_adapter *);
365extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
366extern int igb_setup_tx_resources(struct igb_ring *);
367extern int igb_setup_rx_resources(struct igb_ring *);
368extern void igb_free_tx_resources(struct igb_ring *);
369extern void igb_free_rx_resources(struct igb_ring *);
370extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
371extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
372extern void igb_setup_tctl(struct igb_adapter *);
373extern void igb_setup_rctl(struct igb_adapter *);
374extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
375extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
376 struct igb_buffer *);
377extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
378extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
379extern bool igb_has_link(struct igb_adapter *adapter);
380extern void igb_set_ethtool_ops(struct net_device *);
381extern void igb_power_up_link(struct igb_adapter *);
382
383static inline s32 igb_reset_phy(struct e1000_hw *hw)
384{
385 if (hw->phy.ops.reset)
386 return hw->phy.ops.reset(hw);
387
388 return 0;
389}
390
391static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
392{
393 if (hw->phy.ops.read_reg)
394 return hw->phy.ops.read_reg(hw, offset, data);
395
396 return 0;
397}
398
399static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
400{
401 if (hw->phy.ops.write_reg)
402 return hw->phy.ops.write_reg(hw, offset, data);
403
404 return 0;
405}
406
407static inline s32 igb_get_phy_info(struct e1000_hw *hw)
408{
409 if (hw->phy.ops.get_phy_info)
410 return hw->phy.ops.get_phy_info(hw);
411
412 return 0;
413}
414
415#endif /* _IGB_H_ */