Loading...
Note: File does not exist in v6.8.
1/*
2 * drivers/net/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * Still left to do:
20 * -Add support for module parameters
21 * -Add patch for ethtool phys id
22 */
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/spinlock.h>
38#include <linux/mm.h>
39#include <linux/mii.h>
40#include <linux/phy.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <linux/module.h>
46#include <linux/crc32.h>
47#include <linux/workqueue.h>
48#include <linux/ethtool.h>
49
50struct ethtool_flow_spec_container {
51 struct ethtool_rx_flow_spec fs;
52 struct list_head list;
53};
54
55struct ethtool_rx_list {
56 struct list_head list;
57 unsigned int count;
58};
59
60/* The maximum number of packets to be handled in one call of gfar_poll */
61#define GFAR_DEV_WEIGHT 64
62
63/* Length for FCB */
64#define GMAC_FCB_LEN 8
65
66/* Default padding amount */
67#define DEFAULT_PADDING 2
68
69/* Number of bytes to align the rx bufs to */
70#define RXBUF_ALIGNMENT 64
71
72/* The number of bytes which composes a unit for the purpose of
73 * allocating data buffers. ie-for any given MTU, the data buffer
74 * will be the next highest multiple of 512 bytes. */
75#define INCREMENTAL_BUFFER_SIZE 512
76
77
78#define MAC_ADDR_LEN 6
79
80#define PHY_INIT_TIMEOUT 100000
81#define GFAR_PHY_CHANGE_TIME 2
82
83#define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
84#define DRV_NAME "gfar-enet"
85extern const char gfar_driver_name[];
86extern const char gfar_driver_version[];
87
88/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
89#define MAX_TX_QS 0x8
90#define MAX_RX_QS 0x8
91
92/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
93#define MAXGROUPS 0x2
94
95/* These need to be powers of 2 for this driver */
96#define DEFAULT_TX_RING_SIZE 256
97#define DEFAULT_RX_RING_SIZE 256
98
99#define GFAR_RX_MAX_RING_SIZE 256
100#define GFAR_TX_MAX_RING_SIZE 256
101
102#define GFAR_MAX_FIFO_THRESHOLD 511
103#define GFAR_MAX_FIFO_STARVE 511
104#define GFAR_MAX_FIFO_STARVE_OFF 511
105
106#define DEFAULT_RX_BUFFER_SIZE 1536
107#define TX_RING_MOD_MASK(size) (size-1)
108#define RX_RING_MOD_MASK(size) (size-1)
109#define JUMBO_BUFFER_SIZE 9728
110#define JUMBO_FRAME_SIZE 9600
111
112#define DEFAULT_FIFO_TX_THR 0x100
113#define DEFAULT_FIFO_TX_STARVE 0x40
114#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
115#define DEFAULT_BD_STASH 1
116#define DEFAULT_STASH_LENGTH 96
117#define DEFAULT_STASH_INDEX 0
118
119/* The number of Exact Match registers */
120#define GFAR_EM_NUM 15
121
122/* Latency of interface clock in nanoseconds */
123/* Interface clock latency , in this case, means the
124 * time described by a value of 1 in the interrupt
125 * coalescing registers' time fields. Since those fields
126 * refer to the time it takes for 64 clocks to pass, the
127 * latencies are as such:
128 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
129 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
130 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
131 */
132#define GFAR_GBIT_TIME 512
133#define GFAR_100_TIME 2560
134#define GFAR_10_TIME 25600
135
136#define DEFAULT_TX_COALESCE 1
137#define DEFAULT_TXCOUNT 16
138#define DEFAULT_TXTIME 21
139
140#define DEFAULT_RXTIME 21
141
142#define DEFAULT_RX_COALESCE 0
143#define DEFAULT_RXCOUNT 0
144
145#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
146 | SUPPORTED_10baseT_Full \
147 | SUPPORTED_100baseT_Half \
148 | SUPPORTED_100baseT_Full \
149 | SUPPORTED_Autoneg \
150 | SUPPORTED_MII)
151
152/* TBI register addresses */
153#define MII_TBICON 0x11
154
155/* TBICON register bit fields */
156#define TBICON_CLK_SELECT 0x0020
157
158/* MAC register bits */
159#define MACCFG1_SOFT_RESET 0x80000000
160#define MACCFG1_RESET_RX_MC 0x00080000
161#define MACCFG1_RESET_TX_MC 0x00040000
162#define MACCFG1_RESET_RX_FUN 0x00020000
163#define MACCFG1_RESET_TX_FUN 0x00010000
164#define MACCFG1_LOOPBACK 0x00000100
165#define MACCFG1_RX_FLOW 0x00000020
166#define MACCFG1_TX_FLOW 0x00000010
167#define MACCFG1_SYNCD_RX_EN 0x00000008
168#define MACCFG1_RX_EN 0x00000004
169#define MACCFG1_SYNCD_TX_EN 0x00000002
170#define MACCFG1_TX_EN 0x00000001
171
172#define MACCFG2_INIT_SETTINGS 0x00007205
173#define MACCFG2_FULL_DUPLEX 0x00000001
174#define MACCFG2_IF 0x00000300
175#define MACCFG2_MII 0x00000100
176#define MACCFG2_GMII 0x00000200
177#define MACCFG2_HUGEFRAME 0x00000020
178#define MACCFG2_LENGTHCHECK 0x00000010
179#define MACCFG2_MPEN 0x00000008
180
181#define ECNTRL_FIFM 0x00008000
182#define ECNTRL_INIT_SETTINGS 0x00001000
183#define ECNTRL_TBI_MODE 0x00000020
184#define ECNTRL_REDUCED_MODE 0x00000010
185#define ECNTRL_R100 0x00000008
186#define ECNTRL_REDUCED_MII_MODE 0x00000004
187#define ECNTRL_SGMII_MODE 0x00000002
188
189#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
190
191#define MINFLR_INIT_SETTINGS 0x00000040
192
193/* Tqueue control */
194#define TQUEUE_EN0 0x00008000
195#define TQUEUE_EN1 0x00004000
196#define TQUEUE_EN2 0x00002000
197#define TQUEUE_EN3 0x00001000
198#define TQUEUE_EN4 0x00000800
199#define TQUEUE_EN5 0x00000400
200#define TQUEUE_EN6 0x00000200
201#define TQUEUE_EN7 0x00000100
202#define TQUEUE_EN_ALL 0x0000FF00
203
204#define TR03WT_WT0_MASK 0xFF000000
205#define TR03WT_WT1_MASK 0x00FF0000
206#define TR03WT_WT2_MASK 0x0000FF00
207#define TR03WT_WT3_MASK 0x000000FF
208
209#define TR47WT_WT4_MASK 0xFF000000
210#define TR47WT_WT5_MASK 0x00FF0000
211#define TR47WT_WT6_MASK 0x0000FF00
212#define TR47WT_WT7_MASK 0x000000FF
213
214/* Rqueue control */
215#define RQUEUE_EX0 0x00800000
216#define RQUEUE_EX1 0x00400000
217#define RQUEUE_EX2 0x00200000
218#define RQUEUE_EX3 0x00100000
219#define RQUEUE_EX4 0x00080000
220#define RQUEUE_EX5 0x00040000
221#define RQUEUE_EX6 0x00020000
222#define RQUEUE_EX7 0x00010000
223#define RQUEUE_EX_ALL 0x00FF0000
224
225#define RQUEUE_EN0 0x00000080
226#define RQUEUE_EN1 0x00000040
227#define RQUEUE_EN2 0x00000020
228#define RQUEUE_EN3 0x00000010
229#define RQUEUE_EN4 0x00000008
230#define RQUEUE_EN5 0x00000004
231#define RQUEUE_EN6 0x00000002
232#define RQUEUE_EN7 0x00000001
233#define RQUEUE_EN_ALL 0x000000FF
234
235/* Init to do tx snooping for buffers and descriptors */
236#define DMACTRL_INIT_SETTINGS 0x000000c3
237#define DMACTRL_GRS 0x00000010
238#define DMACTRL_GTS 0x00000008
239
240#define TSTAT_CLEAR_THALT_ALL 0xFF000000
241#define TSTAT_CLEAR_THALT 0x80000000
242#define TSTAT_CLEAR_THALT0 0x80000000
243#define TSTAT_CLEAR_THALT1 0x40000000
244#define TSTAT_CLEAR_THALT2 0x20000000
245#define TSTAT_CLEAR_THALT3 0x10000000
246#define TSTAT_CLEAR_THALT4 0x08000000
247#define TSTAT_CLEAR_THALT5 0x04000000
248#define TSTAT_CLEAR_THALT6 0x02000000
249#define TSTAT_CLEAR_THALT7 0x01000000
250
251/* Interrupt coalescing macros */
252#define IC_ICEN 0x80000000
253#define IC_ICFT_MASK 0x1fe00000
254#define IC_ICFT_SHIFT 21
255#define mk_ic_icft(x) \
256 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
257#define IC_ICTT_MASK 0x0000ffff
258#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
259
260#define mk_ic_value(count, time) (IC_ICEN | \
261 mk_ic_icft(count) | \
262 mk_ic_ictt(time))
263#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
264 IC_ICFT_SHIFT)
265#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
266
267#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
268#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
269
270#define skip_bd(bdp, stride, base, ring_size) ({ \
271 typeof(bdp) new_bd = (bdp) + (stride); \
272 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
273
274#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
275
276#define RCTRL_TS_ENABLE 0x01000000
277#define RCTRL_PAL_MASK 0x001f0000
278#define RCTRL_VLEX 0x00002000
279#define RCTRL_FILREN 0x00001000
280#define RCTRL_GHTX 0x00000400
281#define RCTRL_IPCSEN 0x00000200
282#define RCTRL_TUCSEN 0x00000100
283#define RCTRL_PRSDEP_MASK 0x000000c0
284#define RCTRL_PRSDEP_INIT 0x000000c0
285#define RCTRL_PRSFM 0x00000020
286#define RCTRL_PROM 0x00000008
287#define RCTRL_EMEN 0x00000002
288#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
289 RCTRL_TUCSEN | RCTRL_FILREN)
290#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
291 RCTRL_PRSDEP_INIT)
292#define RCTRL_EXTHASH (RCTRL_GHTX)
293#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
294#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
295
296
297#define RSTAT_CLEAR_RHALT 0x00800000
298
299#define TCTRL_IPCSEN 0x00004000
300#define TCTRL_TUCSEN 0x00002000
301#define TCTRL_VLINS 0x00001000
302#define TCTRL_THDF 0x00000800
303#define TCTRL_RFCPAUSE 0x00000010
304#define TCTRL_TFCPAUSE 0x00000008
305#define TCTRL_TXSCHED_MASK 0x00000006
306#define TCTRL_TXSCHED_INIT 0x00000000
307#define TCTRL_TXSCHED_PRIO 0x00000002
308#define TCTRL_TXSCHED_WRRS 0x00000004
309#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
310
311#define IEVENT_INIT_CLEAR 0xffffffff
312#define IEVENT_BABR 0x80000000
313#define IEVENT_RXC 0x40000000
314#define IEVENT_BSY 0x20000000
315#define IEVENT_EBERR 0x10000000
316#define IEVENT_MSRO 0x04000000
317#define IEVENT_GTSC 0x02000000
318#define IEVENT_BABT 0x01000000
319#define IEVENT_TXC 0x00800000
320#define IEVENT_TXE 0x00400000
321#define IEVENT_TXB 0x00200000
322#define IEVENT_TXF 0x00100000
323#define IEVENT_LC 0x00040000
324#define IEVENT_CRL 0x00020000
325#define IEVENT_XFUN 0x00010000
326#define IEVENT_RXB0 0x00008000
327#define IEVENT_MAG 0x00000800
328#define IEVENT_GRSC 0x00000100
329#define IEVENT_RXF0 0x00000080
330#define IEVENT_FIR 0x00000008
331#define IEVENT_FIQ 0x00000004
332#define IEVENT_DPE 0x00000002
333#define IEVENT_PERR 0x00000001
334#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
335#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
336#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
337#define IEVENT_ERR_MASK \
338(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
339 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
340 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
341 | IEVENT_MAG | IEVENT_BABR)
342
343#define IMASK_INIT_CLEAR 0x00000000
344#define IMASK_BABR 0x80000000
345#define IMASK_RXC 0x40000000
346#define IMASK_BSY 0x20000000
347#define IMASK_EBERR 0x10000000
348#define IMASK_MSRO 0x04000000
349#define IMASK_GTSC 0x02000000
350#define IMASK_BABT 0x01000000
351#define IMASK_TXC 0x00800000
352#define IMASK_TXEEN 0x00400000
353#define IMASK_TXBEN 0x00200000
354#define IMASK_TXFEN 0x00100000
355#define IMASK_LC 0x00040000
356#define IMASK_CRL 0x00020000
357#define IMASK_XFUN 0x00010000
358#define IMASK_RXB0 0x00008000
359#define IMASK_MAG 0x00000800
360#define IMASK_GRSC 0x00000100
361#define IMASK_RXFEN0 0x00000080
362#define IMASK_FIR 0x00000008
363#define IMASK_FIQ 0x00000004
364#define IMASK_DPE 0x00000002
365#define IMASK_PERR 0x00000001
366#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
367 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
368 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
369 | IMASK_PERR)
370#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
371 & IMASK_DEFAULT)
372
373/* Fifo management */
374#define FIFO_TX_THR_MASK 0x01ff
375#define FIFO_TX_STARVE_MASK 0x01ff
376#define FIFO_TX_STARVE_OFF_MASK 0x01ff
377
378/* Attribute fields */
379
380/* This enables rx snooping for buffers and descriptors */
381#define ATTR_BDSTASH 0x00000800
382
383#define ATTR_BUFSTASH 0x00004000
384
385#define ATTR_SNOOPING 0x000000c0
386#define ATTR_INIT_SETTINGS ATTR_SNOOPING
387
388#define ATTRELI_INIT_SETTINGS 0x0
389#define ATTRELI_EL_MASK 0x3fff0000
390#define ATTRELI_EL(x) (x << 16)
391#define ATTRELI_EI_MASK 0x00003fff
392#define ATTRELI_EI(x) (x)
393
394#define BD_LFLAG(flags) ((flags) << 16)
395#define BD_LENGTH_MASK 0x0000ffff
396
397#define FPR_FILER_MASK 0xFFFFFFFF
398#define MAX_FILER_IDX 0xFF
399
400/* This default RIR value directly corresponds
401 * to the 3-bit hash value generated */
402#define DEFAULT_RIR0 0x05397700
403
404/* RQFCR register bits */
405#define RQFCR_GPI 0x80000000
406#define RQFCR_HASHTBL_Q 0x00000000
407#define RQFCR_HASHTBL_0 0x00020000
408#define RQFCR_HASHTBL_1 0x00040000
409#define RQFCR_HASHTBL_2 0x00060000
410#define RQFCR_HASHTBL_3 0x00080000
411#define RQFCR_HASH 0x00010000
412#define RQFCR_QUEUE 0x0000FC00
413#define RQFCR_CLE 0x00000200
414#define RQFCR_RJE 0x00000100
415#define RQFCR_AND 0x00000080
416#define RQFCR_CMP_EXACT 0x00000000
417#define RQFCR_CMP_MATCH 0x00000020
418#define RQFCR_CMP_NOEXACT 0x00000040
419#define RQFCR_CMP_NOMATCH 0x00000060
420
421/* RQFCR PID values */
422#define RQFCR_PID_MASK 0x00000000
423#define RQFCR_PID_PARSE 0x00000001
424#define RQFCR_PID_ARB 0x00000002
425#define RQFCR_PID_DAH 0x00000003
426#define RQFCR_PID_DAL 0x00000004
427#define RQFCR_PID_SAH 0x00000005
428#define RQFCR_PID_SAL 0x00000006
429#define RQFCR_PID_ETY 0x00000007
430#define RQFCR_PID_VID 0x00000008
431#define RQFCR_PID_PRI 0x00000009
432#define RQFCR_PID_TOS 0x0000000A
433#define RQFCR_PID_L4P 0x0000000B
434#define RQFCR_PID_DIA 0x0000000C
435#define RQFCR_PID_SIA 0x0000000D
436#define RQFCR_PID_DPT 0x0000000E
437#define RQFCR_PID_SPT 0x0000000F
438
439/* RQFPR when PID is 0x0001 */
440#define RQFPR_HDR_GE_512 0x00200000
441#define RQFPR_LERR 0x00100000
442#define RQFPR_RAR 0x00080000
443#define RQFPR_RARQ 0x00040000
444#define RQFPR_AR 0x00020000
445#define RQFPR_ARQ 0x00010000
446#define RQFPR_EBC 0x00008000
447#define RQFPR_VLN 0x00004000
448#define RQFPR_CFI 0x00002000
449#define RQFPR_JUM 0x00001000
450#define RQFPR_IPF 0x00000800
451#define RQFPR_FIF 0x00000400
452#define RQFPR_IPV4 0x00000200
453#define RQFPR_IPV6 0x00000100
454#define RQFPR_ICC 0x00000080
455#define RQFPR_ICV 0x00000040
456#define RQFPR_TCP 0x00000020
457#define RQFPR_UDP 0x00000010
458#define RQFPR_TUC 0x00000008
459#define RQFPR_TUV 0x00000004
460#define RQFPR_PER 0x00000002
461#define RQFPR_EER 0x00000001
462
463/* TxBD status field bits */
464#define TXBD_READY 0x8000
465#define TXBD_PADCRC 0x4000
466#define TXBD_WRAP 0x2000
467#define TXBD_INTERRUPT 0x1000
468#define TXBD_LAST 0x0800
469#define TXBD_CRC 0x0400
470#define TXBD_DEF 0x0200
471#define TXBD_HUGEFRAME 0x0080
472#define TXBD_LATECOLLISION 0x0080
473#define TXBD_RETRYLIMIT 0x0040
474#define TXBD_RETRYCOUNTMASK 0x003c
475#define TXBD_UNDERRUN 0x0002
476#define TXBD_TOE 0x0002
477
478/* Tx FCB param bits */
479#define TXFCB_VLN 0x80
480#define TXFCB_IP 0x40
481#define TXFCB_IP6 0x20
482#define TXFCB_TUP 0x10
483#define TXFCB_UDP 0x08
484#define TXFCB_CIP 0x04
485#define TXFCB_CTU 0x02
486#define TXFCB_NPH 0x01
487#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
488
489/* RxBD status field bits */
490#define RXBD_EMPTY 0x8000
491#define RXBD_RO1 0x4000
492#define RXBD_WRAP 0x2000
493#define RXBD_INTERRUPT 0x1000
494#define RXBD_LAST 0x0800
495#define RXBD_FIRST 0x0400
496#define RXBD_MISS 0x0100
497#define RXBD_BROADCAST 0x0080
498#define RXBD_MULTICAST 0x0040
499#define RXBD_LARGE 0x0020
500#define RXBD_NONOCTET 0x0010
501#define RXBD_SHORT 0x0008
502#define RXBD_CRCERR 0x0004
503#define RXBD_OVERRUN 0x0002
504#define RXBD_TRUNCATED 0x0001
505#define RXBD_STATS 0x01ff
506#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
507 | RXBD_CRCERR | RXBD_OVERRUN \
508 | RXBD_TRUNCATED)
509
510/* Rx FCB status field bits */
511#define RXFCB_VLN 0x8000
512#define RXFCB_IP 0x4000
513#define RXFCB_IP6 0x2000
514#define RXFCB_TUP 0x1000
515#define RXFCB_CIP 0x0800
516#define RXFCB_CTU 0x0400
517#define RXFCB_EIP 0x0200
518#define RXFCB_ETU 0x0100
519#define RXFCB_CSUM_MASK 0x0f00
520#define RXFCB_PERR_MASK 0x000c
521#define RXFCB_PERR_BADL3 0x0008
522
523#define GFAR_INT_NAME_MAX IFNAMSIZ + 4
524
525struct txbd8
526{
527 union {
528 struct {
529 u16 status; /* Status Fields */
530 u16 length; /* Buffer length */
531 };
532 u32 lstatus;
533 };
534 u32 bufPtr; /* Buffer Pointer */
535};
536
537struct txfcb {
538 u8 flags;
539 u8 ptp; /* Flag to enable tx timestamping */
540 u8 l4os; /* Level 4 Header Offset */
541 u8 l3os; /* Level 3 Header Offset */
542 u16 phcs; /* Pseudo-header Checksum */
543 u16 vlctl; /* VLAN control word */
544};
545
546struct rxbd8
547{
548 union {
549 struct {
550 u16 status; /* Status Fields */
551 u16 length; /* Buffer Length */
552 };
553 u32 lstatus;
554 };
555 u32 bufPtr; /* Buffer Pointer */
556};
557
558struct rxfcb {
559 u16 flags;
560 u8 rq; /* Receive Queue index */
561 u8 pro; /* Layer 4 Protocol */
562 u16 reserved;
563 u16 vlctl; /* VLAN control word */
564};
565
566struct gianfar_skb_cb {
567 int alignamount;
568};
569
570#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
571
572struct rmon_mib
573{
574 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
575 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
576 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
577 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
578 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
579 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
580 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
581 u32 rbyt; /* 0x.69c - Receive Byte Counter */
582 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
583 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
584 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
585 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
586 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
587 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
588 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
589 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
590 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
591 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
592 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
593 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
594 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
595 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
596 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
597 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
598 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
599 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
600 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
601 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
602 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
603 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
604 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
605 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
606 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
607 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
608 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
609 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
610 u8 res1[4];
611 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
612 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
613 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
614 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
615 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
616 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
617 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
618 u32 car1; /* 0x.730 - Carry Register One */
619 u32 car2; /* 0x.734 - Carry Register Two */
620 u32 cam1; /* 0x.738 - Carry Mask Register One */
621 u32 cam2; /* 0x.73c - Carry Mask Register Two */
622};
623
624struct gfar_extra_stats {
625 u64 kernel_dropped;
626 u64 rx_large;
627 u64 rx_short;
628 u64 rx_nonoctet;
629 u64 rx_crcerr;
630 u64 rx_overrun;
631 u64 rx_bsy;
632 u64 rx_babr;
633 u64 rx_trunc;
634 u64 eberr;
635 u64 tx_babt;
636 u64 tx_underrun;
637 u64 rx_skbmissing;
638 u64 tx_timeout;
639};
640
641#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
642#define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
643
644/* Number of stats in the stats structure (ignore car and cam regs)*/
645#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
646
647#define GFAR_INFOSTR_LEN 32
648
649struct gfar_stats {
650 u64 extra[GFAR_EXTRA_STATS_LEN];
651 u64 rmon[GFAR_RMON_LEN];
652};
653
654
655struct gfar {
656 u32 tsec_id; /* 0x.000 - Controller ID register */
657 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
658 u8 res1[8];
659 u32 ievent; /* 0x.010 - Interrupt Event Register */
660 u32 imask; /* 0x.014 - Interrupt Mask Register */
661 u32 edis; /* 0x.018 - Error Disabled Register */
662 u32 emapg; /* 0x.01c - Group Error mapping register */
663 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
664 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
665 u32 ptv; /* 0x.028 - Pause Time Value Register */
666 u32 dmactrl; /* 0x.02c - DMA Control Register */
667 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
668 u8 res2[28];
669 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
670 register */
671 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
672 register */
673 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
674 register */
675 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
676 shutoff register */
677 u8 res3[44];
678 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
679 u8 res4[8];
680 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
681 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
682 u8 res5[96];
683 u32 tctrl; /* 0x.100 - Transmit Control Register */
684 u32 tstat; /* 0x.104 - Transmit Status Register */
685 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
686 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
687 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
688 u32 tqueue; /* 0x.114 - Transmit queue control register */
689 u8 res7[40];
690 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
691 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
692 u8 res8[52];
693 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
694 u8 res9a[4];
695 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
696 u8 res9b[4];
697 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
698 u8 res9c[4];
699 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
700 u8 res9d[4];
701 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
702 u8 res9e[4];
703 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
704 u8 res9f[4];
705 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
706 u8 res9g[4];
707 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
708 u8 res9h[4];
709 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
710 u8 res9[64];
711 u32 tbaseh; /* 0x.200 - TxBD base address high */
712 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
713 u8 res10a[4];
714 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
715 u8 res10b[4];
716 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
717 u8 res10c[4];
718 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
719 u8 res10d[4];
720 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
721 u8 res10e[4];
722 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
723 u8 res10f[4];
724 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
725 u8 res10g[4];
726 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
727 u8 res10[192];
728 u32 rctrl; /* 0x.300 - Receive Control Register */
729 u32 rstat; /* 0x.304 - Receive Status Register */
730 u8 res12[8];
731 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
732 u32 rqueue; /* 0x.314 - Receive queue control register */
733 u32 rir0; /* 0x.318 - Ring mapping register 0 */
734 u32 rir1; /* 0x.31c - Ring mapping register 1 */
735 u32 rir2; /* 0x.320 - Ring mapping register 2 */
736 u32 rir3; /* 0x.324 - Ring mapping register 3 */
737 u8 res13[8];
738 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
739 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
740 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
741 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
742 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
743 u8 res14[56];
744 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
745 u8 res15a[4];
746 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
747 u8 res15b[4];
748 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
749 u8 res15c[4];
750 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
751 u8 res15d[4];
752 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
753 u8 res15e[4];
754 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
755 u8 res15f[4];
756 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
757 u8 res15g[4];
758 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
759 u8 res15h[4];
760 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
761 u8 res16[64];
762 u32 rbaseh; /* 0x.400 - RxBD base address high */
763 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
764 u8 res17a[4];
765 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
766 u8 res17b[4];
767 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
768 u8 res17c[4];
769 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
770 u8 res17d[4];
771 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
772 u8 res17e[4];
773 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
774 u8 res17f[4];
775 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
776 u8 res17g[4];
777 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
778 u8 res17[192];
779 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
780 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
781 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
782 u32 hafdup; /* 0x.50c - Half Duplex Register */
783 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
784 u8 res18[12];
785 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
786 u32 ifctrl; /* 0x.538 - Interface control register */
787 u32 ifstat; /* 0x.53c - Interface Status Register */
788 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
789 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
790 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
791 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
792 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
793 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
794 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
795 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
796 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
797 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
798 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
799 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
800 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
801 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
802 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
803 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
804 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
805 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
806 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
807 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
808 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
809 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
810 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
811 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
812 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
813 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
814 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
815 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
816 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
817 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
818 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
819 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
820 u8 res20[192];
821 struct rmon_mib rmon; /* 0x.680-0x.73c */
822 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
823 u8 res21[188];
824 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
825 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
826 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
827 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
828 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
829 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
830 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
831 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
832 u8 res22[96];
833 u32 gaddr0; /* 0x.880 - Group address register 0 */
834 u32 gaddr1; /* 0x.884 - Group address register 1 */
835 u32 gaddr2; /* 0x.888 - Group address register 2 */
836 u32 gaddr3; /* 0x.88c - Group address register 3 */
837 u32 gaddr4; /* 0x.890 - Group address register 4 */
838 u32 gaddr5; /* 0x.894 - Group address register 5 */
839 u32 gaddr6; /* 0x.898 - Group address register 6 */
840 u32 gaddr7; /* 0x.89c - Group address register 7 */
841 u8 res23a[352];
842 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
843 u8 res23b[252];
844 u8 res23c[248];
845 u32 attr; /* 0x.bf8 - Attributes Register */
846 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
847 u8 res24[688];
848 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
849 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
850 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
851 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
852 u8 res25[16];
853 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
854 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
855 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
856 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
857 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
858 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
859 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
860 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
861 u8 res26[32];
862 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
863 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
864 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
865 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
866 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
867 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
868 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
869 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
870 u8 res27[208];
871};
872
873/* Flags related to gianfar device features */
874#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
875#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
876#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
877#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
878#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
879#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
880#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
881#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
882#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
883#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
884#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
885#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
886
887#if (MAXGROUPS == 2)
888#define DEFAULT_MAPPING 0xAA
889#else
890#define DEFAULT_MAPPING 0xFF
891#endif
892
893#define ISRG_SHIFT_TX 0x10
894#define ISRG_SHIFT_RX 0x18
895
896/* The same driver can operate in two modes */
897/* SQ_SG_MODE: Single Queue Single Group Mode
898 * (Backward compatible mode)
899 * MQ_MG_MODE: Multi Queue Multi Group mode
900 */
901enum {
902 SQ_SG_MODE = 0,
903 MQ_MG_MODE
904};
905
906/*
907 * Per TX queue stats
908 */
909struct tx_q_stats {
910 unsigned long tx_packets;
911 unsigned long tx_bytes;
912};
913
914/**
915 * struct gfar_priv_tx_q - per tx queue structure
916 * @txlock: per queue tx spin lock
917 * @tx_skbuff:skb pointers
918 * @skb_curtx: to be used skb pointer
919 * @skb_dirtytx:the last used skb pointer
920 * @stats: bytes/packets stats
921 * @qindex: index of this queue
922 * @dev: back pointer to the dev structure
923 * @grp: back pointer to the group to which this queue belongs
924 * @tx_bd_base: First tx buffer descriptor
925 * @cur_tx: Next free ring entry
926 * @dirty_tx: First buffer in line to be transmitted
927 * @tx_ring_size: Tx ring size
928 * @num_txbdfree: number of free TxBds
929 * @txcoalescing: enable/disable tx coalescing
930 * @txic: transmit interrupt coalescing value
931 * @txcount: coalescing value if based on tx frame count
932 * @txtime: coalescing value if based on time
933 */
934struct gfar_priv_tx_q {
935 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
936 struct sk_buff ** tx_skbuff;
937 /* Buffer descriptor pointers */
938 dma_addr_t tx_bd_dma_base;
939 struct txbd8 *tx_bd_base;
940 struct txbd8 *cur_tx;
941 struct txbd8 *dirty_tx;
942 struct tx_q_stats stats;
943 struct net_device *dev;
944 struct gfar_priv_grp *grp;
945 u16 skb_curtx;
946 u16 skb_dirtytx;
947 u16 qindex;
948 unsigned int tx_ring_size;
949 unsigned int num_txbdfree;
950 /* Configuration info for the coalescing features */
951 unsigned char txcoalescing;
952 unsigned long txic;
953 unsigned short txcount;
954 unsigned short txtime;
955};
956
957/*
958 * Per RX queue stats
959 */
960struct rx_q_stats {
961 unsigned long rx_packets;
962 unsigned long rx_bytes;
963 unsigned long rx_dropped;
964};
965
966/**
967 * struct gfar_priv_rx_q - per rx queue structure
968 * @rxlock: per queue rx spin lock
969 * @rx_skbuff: skb pointers
970 * @skb_currx: currently use skb pointer
971 * @rx_bd_base: First rx buffer descriptor
972 * @cur_rx: Next free rx ring entry
973 * @qindex: index of this queue
974 * @dev: back pointer to the dev structure
975 * @rx_ring_size: Rx ring size
976 * @rxcoalescing: enable/disable rx-coalescing
977 * @rxic: receive interrupt coalescing vlaue
978 */
979
980struct gfar_priv_rx_q {
981 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
982 struct sk_buff ** rx_skbuff;
983 dma_addr_t rx_bd_dma_base;
984 struct rxbd8 *rx_bd_base;
985 struct rxbd8 *cur_rx;
986 struct net_device *dev;
987 struct gfar_priv_grp *grp;
988 struct rx_q_stats stats;
989 u16 skb_currx;
990 u16 qindex;
991 unsigned int rx_ring_size;
992 /* RX Coalescing values */
993 unsigned char rxcoalescing;
994 unsigned long rxic;
995};
996
997/**
998 * struct gfar_priv_grp - per group structure
999 * @napi: the napi poll function
1000 * @priv: back pointer to the priv structure
1001 * @regs: the ioremapped register space for this group
1002 * @grp_id: group id for this group
1003 * @interruptTransmit: The TX interrupt number for this group
1004 * @interruptReceive: The RX interrupt number for this group
1005 * @interruptError: The ERROR interrupt number for this group
1006 * @int_name_tx: tx interrupt name for this group
1007 * @int_name_rx: rx interrupt name for this group
1008 * @int_name_er: er interrupt name for this group
1009 */
1010
1011struct gfar_priv_grp {
1012 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1013 struct napi_struct napi;
1014 struct gfar_private *priv;
1015 struct gfar __iomem *regs;
1016 unsigned int grp_id;
1017 unsigned long rx_bit_map;
1018 unsigned long tx_bit_map;
1019 unsigned long num_tx_queues;
1020 unsigned long num_rx_queues;
1021 unsigned int rstat;
1022 unsigned int tstat;
1023 unsigned int imask;
1024 unsigned int ievent;
1025 unsigned int interruptTransmit;
1026 unsigned int interruptReceive;
1027 unsigned int interruptError;
1028
1029 char int_name_tx[GFAR_INT_NAME_MAX];
1030 char int_name_rx[GFAR_INT_NAME_MAX];
1031 char int_name_er[GFAR_INT_NAME_MAX];
1032};
1033
1034enum gfar_errata {
1035 GFAR_ERRATA_74 = 0x01,
1036 GFAR_ERRATA_76 = 0x02,
1037 GFAR_ERRATA_A002 = 0x04,
1038 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
1039};
1040
1041/* Struct stolen almost completely (and shamelessly) from the FCC enet source
1042 * (Ok, that's not so true anymore, but there is a family resemblance)
1043 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1044 * and tx_bd_base always point to the currently available buffer.
1045 * The dirty_tx tracks the current buffer that is being sent by the
1046 * controller. The cur_tx and dirty_tx are equal under both completely
1047 * empty and completely full conditions. The empty/ready indicator in
1048 * the buffer descriptor determines the actual condition.
1049 */
1050struct gfar_private {
1051
1052 /* Indicates how many tx, rx queues are enabled */
1053 unsigned int num_tx_queues;
1054 unsigned int num_rx_queues;
1055 unsigned int num_grps;
1056 unsigned int mode;
1057
1058 /* The total tx and rx ring size for the enabled queues */
1059 unsigned int total_tx_ring_size;
1060 unsigned int total_rx_ring_size;
1061
1062 struct device_node *node;
1063 struct net_device *ndev;
1064 struct platform_device *ofdev;
1065 enum gfar_errata errata;
1066
1067 struct gfar_priv_grp gfargrp[MAXGROUPS];
1068 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1069 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1070
1071 /* RX per device parameters */
1072 unsigned int rx_buffer_size;
1073 unsigned int rx_stash_size;
1074 unsigned int rx_stash_index;
1075
1076 u32 cur_filer_idx;
1077
1078 struct sk_buff_head rx_recycle;
1079
1080 /* RX queue filer rule set*/
1081 struct ethtool_rx_list rx_list;
1082 struct mutex rx_queue_access;
1083
1084 /* Hash registers and their width */
1085 u32 __iomem *hash_regs[16];
1086 int hash_width;
1087
1088 /* global parameters */
1089 unsigned int fifo_threshold;
1090 unsigned int fifo_starve;
1091 unsigned int fifo_starve_off;
1092
1093 /* Bitfield update lock */
1094 spinlock_t bflock;
1095
1096 phy_interface_t interface;
1097 struct device_node *phy_node;
1098 struct device_node *tbi_node;
1099 u32 device_flags;
1100 unsigned char
1101 extended_hash:1,
1102 bd_stash_en:1,
1103 rx_filer_enable:1,
1104 wol_en:1; /* Wake-on-LAN enabled */
1105 unsigned short padding;
1106
1107 /* PHY stuff */
1108 struct phy_device *phydev;
1109 struct mii_bus *mii_bus;
1110 int oldspeed;
1111 int oldduplex;
1112 int oldlink;
1113
1114 uint32_t msg_enable;
1115
1116 struct work_struct reset_task;
1117
1118 /* Network Statistics */
1119 struct gfar_extra_stats extra_stats;
1120
1121 /* HW time stamping enabled flag */
1122 int hwts_rx_en;
1123 int hwts_tx_en;
1124
1125 /*Filer table*/
1126 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1127 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1128};
1129
1130
1131static inline int gfar_has_errata(struct gfar_private *priv,
1132 enum gfar_errata err)
1133{
1134 return priv->errata & err;
1135}
1136
1137static inline u32 gfar_read(volatile unsigned __iomem *addr)
1138{
1139 u32 val;
1140 val = in_be32(addr);
1141 return val;
1142}
1143
1144static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
1145{
1146 out_be32(addr, val);
1147}
1148
1149static inline void gfar_write_filer(struct gfar_private *priv,
1150 unsigned int far, unsigned int fcr, unsigned int fpr)
1151{
1152 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1153
1154 gfar_write(®s->rqfar, far);
1155 gfar_write(®s->rqfcr, fcr);
1156 gfar_write(®s->rqfpr, fpr);
1157}
1158
1159static inline void gfar_read_filer(struct gfar_private *priv,
1160 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1161{
1162 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1163
1164 gfar_write(®s->rqfar, far);
1165 *fcr = gfar_read(®s->rqfcr);
1166 *fpr = gfar_read(®s->rqfpr);
1167}
1168
1169extern void lock_rx_qs(struct gfar_private *priv);
1170extern void lock_tx_qs(struct gfar_private *priv);
1171extern void unlock_rx_qs(struct gfar_private *priv);
1172extern void unlock_tx_qs(struct gfar_private *priv);
1173extern irqreturn_t gfar_receive(int irq, void *dev_id);
1174extern int startup_gfar(struct net_device *dev);
1175extern void stop_gfar(struct net_device *dev);
1176extern void gfar_halt(struct net_device *dev);
1177extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
1178 int enable, u32 regnum, u32 read);
1179extern void gfar_configure_coalescing(struct gfar_private *priv,
1180 unsigned long tx_mask, unsigned long rx_mask);
1181void gfar_init_sysfs(struct net_device *dev);
1182int gfar_set_features(struct net_device *dev, u32 features);
1183extern void gfar_check_rx_parser_mode(struct gfar_private *priv);
1184extern void gfar_vlan_mode(struct net_device *dev, u32 features);
1185
1186extern const struct ethtool_ops gfar_ethtool_ops;
1187
1188#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1189
1190#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1191#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1192#define RQFCR_PID_VID_MASK 0xFFFFF000
1193#define RQFCR_PID_PORT_MASK 0xFFFF0000
1194#define RQFCR_PID_MAC_MASK 0xFF000000
1195
1196struct gfar_mask_entry {
1197 unsigned int mask; /* The mask value which is valid form start to end */
1198 unsigned int start;
1199 unsigned int end;
1200 unsigned int block; /* Same block values indicate depended entries */
1201};
1202
1203/* Represents a receive filer table entry */
1204struct gfar_filer_entry {
1205 u32 ctrl;
1206 u32 prop;
1207};
1208
1209
1210/* The 20 additional entries are a shadow for one extra element */
1211struct filer_table {
1212 u32 index;
1213 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1214};
1215
1216#endif /* __GIANFAR_H */