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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ethernet driver for the WIZnet W5100 chip.
4 *
5 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
6 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/platform_data/wiznet.h>
15#include <linux/ethtool.h>
16#include <linux/skbuff.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/gpio.h>
27
28#include "w5100.h"
29
30#define DRV_NAME "w5100"
31#define DRV_VERSION "2012-04-04"
32
33MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
34MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
35MODULE_ALIAS("platform:"DRV_NAME);
36MODULE_LICENSE("GPL");
37
38/*
39 * W5100/W5200/W5500 common registers
40 */
41#define W5100_COMMON_REGS 0x0000
42#define W5100_MR 0x0000 /* Mode Register */
43#define MR_RST 0x80 /* S/W reset */
44#define MR_PB 0x10 /* Ping block */
45#define MR_AI 0x02 /* Address Auto-Increment */
46#define MR_IND 0x01 /* Indirect mode */
47#define W5100_SHAR 0x0009 /* Source MAC address */
48#define W5100_IR 0x0015 /* Interrupt Register */
49#define W5100_COMMON_REGS_LEN 0x0040
50
51#define W5100_Sn_MR 0x0000 /* Sn Mode Register */
52#define W5100_Sn_CR 0x0001 /* Sn Command Register */
53#define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */
54#define W5100_Sn_SR 0x0003 /* Sn Status Register */
55#define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
56#define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
57#define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
58#define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
59#define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
60
61#define S0_REGS(priv) ((priv)->s0_regs)
62
63#define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR)
64#define S0_MR_MACRAW 0x04 /* MAC RAW mode */
65#define S0_MR_MF 0x40 /* MAC Filter for W5100 and W5200 */
66#define W5500_S0_MR_MF 0x80 /* MAC Filter for W5500 */
67#define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR)
68#define S0_CR_OPEN 0x01 /* OPEN command */
69#define S0_CR_CLOSE 0x10 /* CLOSE command */
70#define S0_CR_SEND 0x20 /* SEND command */
71#define S0_CR_RECV 0x40 /* RECV command */
72#define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR)
73#define S0_IR_SENDOK 0x10 /* complete sending */
74#define S0_IR_RECV 0x04 /* receiving data */
75#define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR)
76#define S0_SR_MACRAW 0x42 /* mac raw mode */
77#define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR)
78#define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD)
79#define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR)
80#define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR)
81#define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD)
82
83#define W5100_S0_REGS_LEN 0x0040
84
85/*
86 * W5100 and W5200 common registers
87 */
88#define W5100_IMR 0x0016 /* Interrupt Mask Register */
89#define IR_S0 0x01 /* S0 interrupt */
90#define W5100_RTR 0x0017 /* Retry Time-value Register */
91#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
92
93/*
94 * W5100 specific register and memory
95 */
96#define W5100_RMSR 0x001a /* Receive Memory Size */
97#define W5100_TMSR 0x001b /* Transmit Memory Size */
98
99#define W5100_S0_REGS 0x0400
100
101#define W5100_TX_MEM_START 0x4000
102#define W5100_TX_MEM_SIZE 0x2000
103#define W5100_RX_MEM_START 0x6000
104#define W5100_RX_MEM_SIZE 0x2000
105
106/*
107 * W5200 specific register and memory
108 */
109#define W5200_S0_REGS 0x4000
110
111#define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */
112#define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */
113
114#define W5200_TX_MEM_START 0x8000
115#define W5200_TX_MEM_SIZE 0x4000
116#define W5200_RX_MEM_START 0xc000
117#define W5200_RX_MEM_SIZE 0x4000
118
119/*
120 * W5500 specific register and memory
121 *
122 * W5500 register and memory are organized by multiple blocks. Each one is
123 * selected by 16bits offset address and 5bits block select bits. So we
124 * encode it into 32bits address. (lower 16bits is offset address and
125 * upper 16bits is block select bits)
126 */
127#define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
128#define W5500_RTR 0x0019 /* Retry Time-value Register */
129
130#define W5500_S0_REGS 0x10000
131
132#define W5500_Sn_RXMEM_SIZE(n) \
133 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
134#define W5500_Sn_TXMEM_SIZE(n) \
135 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
136
137#define W5500_TX_MEM_START 0x20000
138#define W5500_TX_MEM_SIZE 0x04000
139#define W5500_RX_MEM_START 0x30000
140#define W5500_RX_MEM_SIZE 0x04000
141
142/*
143 * Device driver private data structure
144 */
145
146struct w5100_priv {
147 const struct w5100_ops *ops;
148
149 /* Socket 0 register offset address */
150 u32 s0_regs;
151 /* Socket 0 TX buffer offset address and size */
152 u32 s0_tx_buf;
153 u16 s0_tx_buf_size;
154 /* Socket 0 RX buffer offset address and size */
155 u32 s0_rx_buf;
156 u16 s0_rx_buf_size;
157
158 int irq;
159 int link_irq;
160 int link_gpio;
161
162 struct napi_struct napi;
163 struct net_device *ndev;
164 bool promisc;
165 u32 msg_enable;
166
167 struct workqueue_struct *xfer_wq;
168 struct work_struct rx_work;
169 struct sk_buff *tx_skb;
170 struct work_struct tx_work;
171 struct work_struct setrx_work;
172 struct work_struct restart_work;
173};
174
175/************************************************************************
176 *
177 * Lowlevel I/O functions
178 *
179 ***********************************************************************/
180
181struct w5100_mmio_priv {
182 void __iomem *base;
183 /* Serialize access in indirect address mode */
184 spinlock_t reg_lock;
185};
186
187static inline struct w5100_mmio_priv *w5100_mmio_priv(struct net_device *dev)
188{
189 return w5100_ops_priv(dev);
190}
191
192static inline void __iomem *w5100_mmio(struct net_device *ndev)
193{
194 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
195
196 return mmio_priv->base;
197}
198
199/*
200 * In direct address mode host system can directly access W5100 registers
201 * after mapping to Memory-Mapped I/O space.
202 *
203 * 0x8000 bytes are required for memory space.
204 */
205static inline int w5100_read_direct(struct net_device *ndev, u32 addr)
206{
207 return ioread8(w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
208}
209
210static inline int __w5100_write_direct(struct net_device *ndev, u32 addr,
211 u8 data)
212{
213 iowrite8(data, w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
214
215 return 0;
216}
217
218static inline int w5100_write_direct(struct net_device *ndev, u32 addr, u8 data)
219{
220 __w5100_write_direct(ndev, addr, data);
221
222 return 0;
223}
224
225static int w5100_read16_direct(struct net_device *ndev, u32 addr)
226{
227 u16 data;
228 data = w5100_read_direct(ndev, addr) << 8;
229 data |= w5100_read_direct(ndev, addr + 1);
230 return data;
231}
232
233static int w5100_write16_direct(struct net_device *ndev, u32 addr, u16 data)
234{
235 __w5100_write_direct(ndev, addr, data >> 8);
236 __w5100_write_direct(ndev, addr + 1, data);
237
238 return 0;
239}
240
241static int w5100_readbulk_direct(struct net_device *ndev, u32 addr, u8 *buf,
242 int len)
243{
244 int i;
245
246 for (i = 0; i < len; i++, addr++)
247 *buf++ = w5100_read_direct(ndev, addr);
248
249 return 0;
250}
251
252static int w5100_writebulk_direct(struct net_device *ndev, u32 addr,
253 const u8 *buf, int len)
254{
255 int i;
256
257 for (i = 0; i < len; i++, addr++)
258 __w5100_write_direct(ndev, addr, *buf++);
259
260 return 0;
261}
262
263static int w5100_mmio_init(struct net_device *ndev)
264{
265 struct platform_device *pdev = to_platform_device(ndev->dev.parent);
266 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
267
268 spin_lock_init(&mmio_priv->reg_lock);
269
270 mmio_priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
271 if (IS_ERR(mmio_priv->base))
272 return PTR_ERR(mmio_priv->base);
273
274 return 0;
275}
276
277static const struct w5100_ops w5100_mmio_direct_ops = {
278 .chip_id = W5100,
279 .read = w5100_read_direct,
280 .write = w5100_write_direct,
281 .read16 = w5100_read16_direct,
282 .write16 = w5100_write16_direct,
283 .readbulk = w5100_readbulk_direct,
284 .writebulk = w5100_writebulk_direct,
285 .init = w5100_mmio_init,
286};
287
288/*
289 * In indirect address mode host system indirectly accesses registers by
290 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
291 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
292 * Mode Register (MR) is directly accessible.
293 *
294 * Only 0x04 bytes are required for memory space.
295 */
296#define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
297#define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
298
299static int w5100_read_indirect(struct net_device *ndev, u32 addr)
300{
301 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
302 unsigned long flags;
303 u8 data;
304
305 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
306 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
307 data = w5100_read_direct(ndev, W5100_IDM_DR);
308 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
309
310 return data;
311}
312
313static int w5100_write_indirect(struct net_device *ndev, u32 addr, u8 data)
314{
315 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
316 unsigned long flags;
317
318 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
319 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
320 w5100_write_direct(ndev, W5100_IDM_DR, data);
321 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
322
323 return 0;
324}
325
326static int w5100_read16_indirect(struct net_device *ndev, u32 addr)
327{
328 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
329 unsigned long flags;
330 u16 data;
331
332 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
333 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
334 data = w5100_read_direct(ndev, W5100_IDM_DR) << 8;
335 data |= w5100_read_direct(ndev, W5100_IDM_DR);
336 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
337
338 return data;
339}
340
341static int w5100_write16_indirect(struct net_device *ndev, u32 addr, u16 data)
342{
343 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
344 unsigned long flags;
345
346 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
347 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
348 __w5100_write_direct(ndev, W5100_IDM_DR, data >> 8);
349 w5100_write_direct(ndev, W5100_IDM_DR, data);
350 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
351
352 return 0;
353}
354
355static int w5100_readbulk_indirect(struct net_device *ndev, u32 addr, u8 *buf,
356 int len)
357{
358 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
359 unsigned long flags;
360 int i;
361
362 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
363 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
364
365 for (i = 0; i < len; i++)
366 *buf++ = w5100_read_direct(ndev, W5100_IDM_DR);
367
368 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
369
370 return 0;
371}
372
373static int w5100_writebulk_indirect(struct net_device *ndev, u32 addr,
374 const u8 *buf, int len)
375{
376 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
377 unsigned long flags;
378 int i;
379
380 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
381 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
382
383 for (i = 0; i < len; i++)
384 __w5100_write_direct(ndev, W5100_IDM_DR, *buf++);
385
386 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
387
388 return 0;
389}
390
391static int w5100_reset_indirect(struct net_device *ndev)
392{
393 w5100_write_direct(ndev, W5100_MR, MR_RST);
394 mdelay(5);
395 w5100_write_direct(ndev, W5100_MR, MR_PB | MR_AI | MR_IND);
396
397 return 0;
398}
399
400static const struct w5100_ops w5100_mmio_indirect_ops = {
401 .chip_id = W5100,
402 .read = w5100_read_indirect,
403 .write = w5100_write_indirect,
404 .read16 = w5100_read16_indirect,
405 .write16 = w5100_write16_indirect,
406 .readbulk = w5100_readbulk_indirect,
407 .writebulk = w5100_writebulk_indirect,
408 .init = w5100_mmio_init,
409 .reset = w5100_reset_indirect,
410};
411
412#if defined(CONFIG_WIZNET_BUS_DIRECT)
413
414static int w5100_read(struct w5100_priv *priv, u32 addr)
415{
416 return w5100_read_direct(priv->ndev, addr);
417}
418
419static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
420{
421 return w5100_write_direct(priv->ndev, addr, data);
422}
423
424static int w5100_read16(struct w5100_priv *priv, u32 addr)
425{
426 return w5100_read16_direct(priv->ndev, addr);
427}
428
429static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
430{
431 return w5100_write16_direct(priv->ndev, addr, data);
432}
433
434static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
435{
436 return w5100_readbulk_direct(priv->ndev, addr, buf, len);
437}
438
439static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
440 int len)
441{
442 return w5100_writebulk_direct(priv->ndev, addr, buf, len);
443}
444
445#elif defined(CONFIG_WIZNET_BUS_INDIRECT)
446
447static int w5100_read(struct w5100_priv *priv, u32 addr)
448{
449 return w5100_read_indirect(priv->ndev, addr);
450}
451
452static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
453{
454 return w5100_write_indirect(priv->ndev, addr, data);
455}
456
457static int w5100_read16(struct w5100_priv *priv, u32 addr)
458{
459 return w5100_read16_indirect(priv->ndev, addr);
460}
461
462static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
463{
464 return w5100_write16_indirect(priv->ndev, addr, data);
465}
466
467static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
468{
469 return w5100_readbulk_indirect(priv->ndev, addr, buf, len);
470}
471
472static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
473 int len)
474{
475 return w5100_writebulk_indirect(priv->ndev, addr, buf, len);
476}
477
478#else /* CONFIG_WIZNET_BUS_ANY */
479
480static int w5100_read(struct w5100_priv *priv, u32 addr)
481{
482 return priv->ops->read(priv->ndev, addr);
483}
484
485static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
486{
487 return priv->ops->write(priv->ndev, addr, data);
488}
489
490static int w5100_read16(struct w5100_priv *priv, u32 addr)
491{
492 return priv->ops->read16(priv->ndev, addr);
493}
494
495static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
496{
497 return priv->ops->write16(priv->ndev, addr, data);
498}
499
500static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
501{
502 return priv->ops->readbulk(priv->ndev, addr, buf, len);
503}
504
505static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
506 int len)
507{
508 return priv->ops->writebulk(priv->ndev, addr, buf, len);
509}
510
511#endif
512
513static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len)
514{
515 u32 addr;
516 int remain = 0;
517 int ret;
518 const u32 mem_start = priv->s0_rx_buf;
519 const u16 mem_size = priv->s0_rx_buf_size;
520
521 offset %= mem_size;
522 addr = mem_start + offset;
523
524 if (offset + len > mem_size) {
525 remain = (offset + len) % mem_size;
526 len = mem_size - offset;
527 }
528
529 ret = w5100_readbulk(priv, addr, buf, len);
530 if (ret || !remain)
531 return ret;
532
533 return w5100_readbulk(priv, mem_start, buf + len, remain);
534}
535
536static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf,
537 int len)
538{
539 u32 addr;
540 int ret;
541 int remain = 0;
542 const u32 mem_start = priv->s0_tx_buf;
543 const u16 mem_size = priv->s0_tx_buf_size;
544
545 offset %= mem_size;
546 addr = mem_start + offset;
547
548 if (offset + len > mem_size) {
549 remain = (offset + len) % mem_size;
550 len = mem_size - offset;
551 }
552
553 ret = w5100_writebulk(priv, addr, buf, len);
554 if (ret || !remain)
555 return ret;
556
557 return w5100_writebulk(priv, mem_start, buf + len, remain);
558}
559
560static int w5100_reset(struct w5100_priv *priv)
561{
562 if (priv->ops->reset)
563 return priv->ops->reset(priv->ndev);
564
565 w5100_write(priv, W5100_MR, MR_RST);
566 mdelay(5);
567 w5100_write(priv, W5100_MR, MR_PB);
568
569 return 0;
570}
571
572static int w5100_command(struct w5100_priv *priv, u16 cmd)
573{
574 unsigned long timeout;
575
576 w5100_write(priv, W5100_S0_CR(priv), cmd);
577
578 timeout = jiffies + msecs_to_jiffies(100);
579
580 while (w5100_read(priv, W5100_S0_CR(priv)) != 0) {
581 if (time_after(jiffies, timeout))
582 return -EIO;
583 cpu_relax();
584 }
585
586 return 0;
587}
588
589static void w5100_write_macaddr(struct w5100_priv *priv)
590{
591 struct net_device *ndev = priv->ndev;
592
593 w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN);
594}
595
596static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask)
597{
598 u32 imr;
599
600 if (priv->ops->chip_id == W5500)
601 imr = W5500_SIMR;
602 else
603 imr = W5100_IMR;
604
605 w5100_write(priv, imr, mask);
606}
607
608static void w5100_enable_intr(struct w5100_priv *priv)
609{
610 w5100_socket_intr_mask(priv, IR_S0);
611}
612
613static void w5100_disable_intr(struct w5100_priv *priv)
614{
615 w5100_socket_intr_mask(priv, 0);
616}
617
618static void w5100_memory_configure(struct w5100_priv *priv)
619{
620 /* Configure 16K of internal memory
621 * as 8K RX buffer and 8K TX buffer
622 */
623 w5100_write(priv, W5100_RMSR, 0x03);
624 w5100_write(priv, W5100_TMSR, 0x03);
625}
626
627static void w5200_memory_configure(struct w5100_priv *priv)
628{
629 int i;
630
631 /* Configure internal RX memory as 16K RX buffer and
632 * internal TX memory as 16K TX buffer
633 */
634 w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10);
635 w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10);
636
637 for (i = 1; i < 8; i++) {
638 w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0);
639 w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0);
640 }
641}
642
643static void w5500_memory_configure(struct w5100_priv *priv)
644{
645 int i;
646
647 /* Configure internal RX memory as 16K RX buffer and
648 * internal TX memory as 16K TX buffer
649 */
650 w5100_write(priv, W5500_Sn_RXMEM_SIZE(0), 0x10);
651 w5100_write(priv, W5500_Sn_TXMEM_SIZE(0), 0x10);
652
653 for (i = 1; i < 8; i++) {
654 w5100_write(priv, W5500_Sn_RXMEM_SIZE(i), 0);
655 w5100_write(priv, W5500_Sn_TXMEM_SIZE(i), 0);
656 }
657}
658
659static int w5100_hw_reset(struct w5100_priv *priv)
660{
661 u32 rtr;
662
663 w5100_reset(priv);
664
665 w5100_disable_intr(priv);
666 w5100_write_macaddr(priv);
667
668 switch (priv->ops->chip_id) {
669 case W5100:
670 w5100_memory_configure(priv);
671 rtr = W5100_RTR;
672 break;
673 case W5200:
674 w5200_memory_configure(priv);
675 rtr = W5100_RTR;
676 break;
677 case W5500:
678 w5500_memory_configure(priv);
679 rtr = W5500_RTR;
680 break;
681 default:
682 return -EINVAL;
683 }
684
685 if (w5100_read16(priv, rtr) != RTR_DEFAULT)
686 return -ENODEV;
687
688 return 0;
689}
690
691static void w5100_hw_start(struct w5100_priv *priv)
692{
693 u8 mode = S0_MR_MACRAW;
694
695 if (!priv->promisc) {
696 if (priv->ops->chip_id == W5500)
697 mode |= W5500_S0_MR_MF;
698 else
699 mode |= S0_MR_MF;
700 }
701
702 w5100_write(priv, W5100_S0_MR(priv), mode);
703 w5100_command(priv, S0_CR_OPEN);
704 w5100_enable_intr(priv);
705}
706
707static void w5100_hw_close(struct w5100_priv *priv)
708{
709 w5100_disable_intr(priv);
710 w5100_command(priv, S0_CR_CLOSE);
711}
712
713/***********************************************************************
714 *
715 * Device driver functions / callbacks
716 *
717 ***********************************************************************/
718
719static void w5100_get_drvinfo(struct net_device *ndev,
720 struct ethtool_drvinfo *info)
721{
722 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
723 strscpy(info->version, DRV_VERSION, sizeof(info->version));
724 strscpy(info->bus_info, dev_name(ndev->dev.parent),
725 sizeof(info->bus_info));
726}
727
728static u32 w5100_get_link(struct net_device *ndev)
729{
730 struct w5100_priv *priv = netdev_priv(ndev);
731
732 if (gpio_is_valid(priv->link_gpio))
733 return !!gpio_get_value(priv->link_gpio);
734
735 return 1;
736}
737
738static u32 w5100_get_msglevel(struct net_device *ndev)
739{
740 struct w5100_priv *priv = netdev_priv(ndev);
741
742 return priv->msg_enable;
743}
744
745static void w5100_set_msglevel(struct net_device *ndev, u32 value)
746{
747 struct w5100_priv *priv = netdev_priv(ndev);
748
749 priv->msg_enable = value;
750}
751
752static int w5100_get_regs_len(struct net_device *ndev)
753{
754 return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
755}
756
757static void w5100_get_regs(struct net_device *ndev,
758 struct ethtool_regs *regs, void *buf)
759{
760 struct w5100_priv *priv = netdev_priv(ndev);
761
762 regs->version = 1;
763 w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN);
764 buf += W5100_COMMON_REGS_LEN;
765 w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN);
766}
767
768static void w5100_restart(struct net_device *ndev)
769{
770 struct w5100_priv *priv = netdev_priv(ndev);
771
772 netif_stop_queue(ndev);
773 w5100_hw_reset(priv);
774 w5100_hw_start(priv);
775 ndev->stats.tx_errors++;
776 netif_trans_update(ndev);
777 netif_wake_queue(ndev);
778}
779
780static void w5100_restart_work(struct work_struct *work)
781{
782 struct w5100_priv *priv = container_of(work, struct w5100_priv,
783 restart_work);
784
785 w5100_restart(priv->ndev);
786}
787
788static void w5100_tx_timeout(struct net_device *ndev, unsigned int txqueue)
789{
790 struct w5100_priv *priv = netdev_priv(ndev);
791
792 if (priv->ops->may_sleep)
793 schedule_work(&priv->restart_work);
794 else
795 w5100_restart(ndev);
796}
797
798static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb)
799{
800 struct w5100_priv *priv = netdev_priv(ndev);
801 u16 offset;
802
803 offset = w5100_read16(priv, W5100_S0_TX_WR(priv));
804 w5100_writebuf(priv, offset, skb->data, skb->len);
805 w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len);
806 ndev->stats.tx_bytes += skb->len;
807 ndev->stats.tx_packets++;
808 dev_kfree_skb(skb);
809
810 w5100_command(priv, S0_CR_SEND);
811}
812
813static void w5100_tx_work(struct work_struct *work)
814{
815 struct w5100_priv *priv = container_of(work, struct w5100_priv,
816 tx_work);
817 struct sk_buff *skb = priv->tx_skb;
818
819 priv->tx_skb = NULL;
820
821 if (WARN_ON(!skb))
822 return;
823 w5100_tx_skb(priv->ndev, skb);
824}
825
826static netdev_tx_t w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
827{
828 struct w5100_priv *priv = netdev_priv(ndev);
829
830 netif_stop_queue(ndev);
831
832 if (priv->ops->may_sleep) {
833 WARN_ON(priv->tx_skb);
834 priv->tx_skb = skb;
835 queue_work(priv->xfer_wq, &priv->tx_work);
836 } else {
837 w5100_tx_skb(ndev, skb);
838 }
839
840 return NETDEV_TX_OK;
841}
842
843static struct sk_buff *w5100_rx_skb(struct net_device *ndev)
844{
845 struct w5100_priv *priv = netdev_priv(ndev);
846 struct sk_buff *skb;
847 u16 rx_len;
848 u16 offset;
849 u8 header[2];
850 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv));
851
852 if (rx_buf_len == 0)
853 return NULL;
854
855 offset = w5100_read16(priv, W5100_S0_RX_RD(priv));
856 w5100_readbuf(priv, offset, header, 2);
857 rx_len = get_unaligned_be16(header) - 2;
858
859 skb = netdev_alloc_skb_ip_align(ndev, rx_len);
860 if (unlikely(!skb)) {
861 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len);
862 w5100_command(priv, S0_CR_RECV);
863 ndev->stats.rx_dropped++;
864 return NULL;
865 }
866
867 skb_put(skb, rx_len);
868 w5100_readbuf(priv, offset + 2, skb->data, rx_len);
869 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len);
870 w5100_command(priv, S0_CR_RECV);
871 skb->protocol = eth_type_trans(skb, ndev);
872
873 ndev->stats.rx_packets++;
874 ndev->stats.rx_bytes += rx_len;
875
876 return skb;
877}
878
879static void w5100_rx_work(struct work_struct *work)
880{
881 struct w5100_priv *priv = container_of(work, struct w5100_priv,
882 rx_work);
883 struct sk_buff *skb;
884
885 while ((skb = w5100_rx_skb(priv->ndev)))
886 netif_rx(skb);
887
888 w5100_enable_intr(priv);
889}
890
891static int w5100_napi_poll(struct napi_struct *napi, int budget)
892{
893 struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
894 int rx_count;
895
896 for (rx_count = 0; rx_count < budget; rx_count++) {
897 struct sk_buff *skb = w5100_rx_skb(priv->ndev);
898
899 if (skb)
900 netif_receive_skb(skb);
901 else
902 break;
903 }
904
905 if (rx_count < budget) {
906 napi_complete_done(napi, rx_count);
907 w5100_enable_intr(priv);
908 }
909
910 return rx_count;
911}
912
913static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
914{
915 struct net_device *ndev = ndev_instance;
916 struct w5100_priv *priv = netdev_priv(ndev);
917
918 int ir = w5100_read(priv, W5100_S0_IR(priv));
919 if (!ir)
920 return IRQ_NONE;
921 w5100_write(priv, W5100_S0_IR(priv), ir);
922
923 if (ir & S0_IR_SENDOK) {
924 netif_dbg(priv, tx_done, ndev, "tx done\n");
925 netif_wake_queue(ndev);
926 }
927
928 if (ir & S0_IR_RECV) {
929 w5100_disable_intr(priv);
930
931 if (priv->ops->may_sleep)
932 queue_work(priv->xfer_wq, &priv->rx_work);
933 else
934 napi_schedule(&priv->napi);
935 }
936
937 return IRQ_HANDLED;
938}
939
940static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
941{
942 struct net_device *ndev = ndev_instance;
943 struct w5100_priv *priv = netdev_priv(ndev);
944
945 if (netif_running(ndev)) {
946 if (gpio_get_value(priv->link_gpio) != 0) {
947 netif_info(priv, link, ndev, "link is up\n");
948 netif_carrier_on(ndev);
949 } else {
950 netif_info(priv, link, ndev, "link is down\n");
951 netif_carrier_off(ndev);
952 }
953 }
954
955 return IRQ_HANDLED;
956}
957
958static void w5100_setrx_work(struct work_struct *work)
959{
960 struct w5100_priv *priv = container_of(work, struct w5100_priv,
961 setrx_work);
962
963 w5100_hw_start(priv);
964}
965
966static void w5100_set_rx_mode(struct net_device *ndev)
967{
968 struct w5100_priv *priv = netdev_priv(ndev);
969 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
970
971 if (priv->promisc != set_promisc) {
972 priv->promisc = set_promisc;
973
974 if (priv->ops->may_sleep)
975 schedule_work(&priv->setrx_work);
976 else
977 w5100_hw_start(priv);
978 }
979}
980
981static int w5100_set_macaddr(struct net_device *ndev, void *addr)
982{
983 struct w5100_priv *priv = netdev_priv(ndev);
984 struct sockaddr *sock_addr = addr;
985
986 if (!is_valid_ether_addr(sock_addr->sa_data))
987 return -EADDRNOTAVAIL;
988 eth_hw_addr_set(ndev, sock_addr->sa_data);
989 w5100_write_macaddr(priv);
990 return 0;
991}
992
993static int w5100_open(struct net_device *ndev)
994{
995 struct w5100_priv *priv = netdev_priv(ndev);
996
997 netif_info(priv, ifup, ndev, "enabling\n");
998 w5100_hw_start(priv);
999 napi_enable(&priv->napi);
1000 netif_start_queue(ndev);
1001 if (!gpio_is_valid(priv->link_gpio) ||
1002 gpio_get_value(priv->link_gpio) != 0)
1003 netif_carrier_on(ndev);
1004 return 0;
1005}
1006
1007static int w5100_stop(struct net_device *ndev)
1008{
1009 struct w5100_priv *priv = netdev_priv(ndev);
1010
1011 netif_info(priv, ifdown, ndev, "shutting down\n");
1012 w5100_hw_close(priv);
1013 netif_carrier_off(ndev);
1014 netif_stop_queue(ndev);
1015 napi_disable(&priv->napi);
1016 return 0;
1017}
1018
1019static const struct ethtool_ops w5100_ethtool_ops = {
1020 .get_drvinfo = w5100_get_drvinfo,
1021 .get_msglevel = w5100_get_msglevel,
1022 .set_msglevel = w5100_set_msglevel,
1023 .get_link = w5100_get_link,
1024 .get_regs_len = w5100_get_regs_len,
1025 .get_regs = w5100_get_regs,
1026};
1027
1028static const struct net_device_ops w5100_netdev_ops = {
1029 .ndo_open = w5100_open,
1030 .ndo_stop = w5100_stop,
1031 .ndo_start_xmit = w5100_start_tx,
1032 .ndo_tx_timeout = w5100_tx_timeout,
1033 .ndo_set_rx_mode = w5100_set_rx_mode,
1034 .ndo_set_mac_address = w5100_set_macaddr,
1035 .ndo_validate_addr = eth_validate_addr,
1036};
1037
1038static int w5100_mmio_probe(struct platform_device *pdev)
1039{
1040 struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
1041 const void *mac_addr = NULL;
1042 struct resource *mem;
1043 const struct w5100_ops *ops;
1044 int irq;
1045
1046 if (data && is_valid_ether_addr(data->mac_addr))
1047 mac_addr = data->mac_addr;
1048
1049 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050 if (!mem)
1051 return -EINVAL;
1052 if (resource_size(mem) < W5100_BUS_DIRECT_SIZE)
1053 ops = &w5100_mmio_indirect_ops;
1054 else
1055 ops = &w5100_mmio_direct_ops;
1056
1057 irq = platform_get_irq(pdev, 0);
1058 if (irq < 0)
1059 return irq;
1060
1061 return w5100_probe(&pdev->dev, ops, sizeof(struct w5100_mmio_priv),
1062 mac_addr, irq, data ? data->link_gpio : -EINVAL);
1063}
1064
1065static void w5100_mmio_remove(struct platform_device *pdev)
1066{
1067 w5100_remove(&pdev->dev);
1068}
1069
1070void *w5100_ops_priv(const struct net_device *ndev)
1071{
1072 return netdev_priv(ndev) +
1073 ALIGN(sizeof(struct w5100_priv), NETDEV_ALIGN);
1074}
1075EXPORT_SYMBOL_GPL(w5100_ops_priv);
1076
1077int w5100_probe(struct device *dev, const struct w5100_ops *ops,
1078 int sizeof_ops_priv, const void *mac_addr, int irq,
1079 int link_gpio)
1080{
1081 struct w5100_priv *priv;
1082 struct net_device *ndev;
1083 int err;
1084 size_t alloc_size;
1085
1086 alloc_size = sizeof(*priv);
1087 if (sizeof_ops_priv) {
1088 alloc_size = ALIGN(alloc_size, NETDEV_ALIGN);
1089 alloc_size += sizeof_ops_priv;
1090 }
1091 alloc_size += NETDEV_ALIGN - 1;
1092
1093 ndev = alloc_etherdev(alloc_size);
1094 if (!ndev)
1095 return -ENOMEM;
1096 SET_NETDEV_DEV(ndev, dev);
1097 dev_set_drvdata(dev, ndev);
1098 priv = netdev_priv(ndev);
1099
1100 switch (ops->chip_id) {
1101 case W5100:
1102 priv->s0_regs = W5100_S0_REGS;
1103 priv->s0_tx_buf = W5100_TX_MEM_START;
1104 priv->s0_tx_buf_size = W5100_TX_MEM_SIZE;
1105 priv->s0_rx_buf = W5100_RX_MEM_START;
1106 priv->s0_rx_buf_size = W5100_RX_MEM_SIZE;
1107 break;
1108 case W5200:
1109 priv->s0_regs = W5200_S0_REGS;
1110 priv->s0_tx_buf = W5200_TX_MEM_START;
1111 priv->s0_tx_buf_size = W5200_TX_MEM_SIZE;
1112 priv->s0_rx_buf = W5200_RX_MEM_START;
1113 priv->s0_rx_buf_size = W5200_RX_MEM_SIZE;
1114 break;
1115 case W5500:
1116 priv->s0_regs = W5500_S0_REGS;
1117 priv->s0_tx_buf = W5500_TX_MEM_START;
1118 priv->s0_tx_buf_size = W5500_TX_MEM_SIZE;
1119 priv->s0_rx_buf = W5500_RX_MEM_START;
1120 priv->s0_rx_buf_size = W5500_RX_MEM_SIZE;
1121 break;
1122 default:
1123 err = -EINVAL;
1124 goto err_register;
1125 }
1126
1127 priv->ndev = ndev;
1128 priv->ops = ops;
1129 priv->irq = irq;
1130 priv->link_gpio = link_gpio;
1131
1132 ndev->netdev_ops = &w5100_netdev_ops;
1133 ndev->ethtool_ops = &w5100_ethtool_ops;
1134 netif_napi_add_weight(ndev, &priv->napi, w5100_napi_poll, 16);
1135
1136 /* This chip doesn't support VLAN packets with normal MTU,
1137 * so disable VLAN for this device.
1138 */
1139 ndev->features |= NETIF_F_VLAN_CHALLENGED;
1140
1141 err = register_netdev(ndev);
1142 if (err < 0)
1143 goto err_register;
1144
1145 priv->xfer_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0,
1146 netdev_name(ndev));
1147 if (!priv->xfer_wq) {
1148 err = -ENOMEM;
1149 goto err_wq;
1150 }
1151
1152 INIT_WORK(&priv->rx_work, w5100_rx_work);
1153 INIT_WORK(&priv->tx_work, w5100_tx_work);
1154 INIT_WORK(&priv->setrx_work, w5100_setrx_work);
1155 INIT_WORK(&priv->restart_work, w5100_restart_work);
1156
1157 if (mac_addr)
1158 eth_hw_addr_set(ndev, mac_addr);
1159 else
1160 eth_hw_addr_random(ndev);
1161
1162 if (priv->ops->init) {
1163 err = priv->ops->init(priv->ndev);
1164 if (err)
1165 goto err_hw;
1166 }
1167
1168 err = w5100_hw_reset(priv);
1169 if (err)
1170 goto err_hw;
1171
1172 if (ops->may_sleep) {
1173 err = request_threaded_irq(priv->irq, NULL, w5100_interrupt,
1174 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1175 netdev_name(ndev), ndev);
1176 } else {
1177 err = request_irq(priv->irq, w5100_interrupt,
1178 IRQF_TRIGGER_LOW, netdev_name(ndev), ndev);
1179 }
1180 if (err)
1181 goto err_hw;
1182
1183 if (gpio_is_valid(priv->link_gpio)) {
1184 char *link_name = devm_kzalloc(dev, 16, GFP_KERNEL);
1185
1186 if (!link_name) {
1187 err = -ENOMEM;
1188 goto err_gpio;
1189 }
1190 snprintf(link_name, 16, "%s-link", netdev_name(ndev));
1191 priv->link_irq = gpio_to_irq(priv->link_gpio);
1192 if (request_any_context_irq(priv->link_irq, w5100_detect_link,
1193 IRQF_TRIGGER_RISING |
1194 IRQF_TRIGGER_FALLING,
1195 link_name, priv->ndev) < 0)
1196 priv->link_gpio = -EINVAL;
1197 }
1198
1199 return 0;
1200
1201err_gpio:
1202 free_irq(priv->irq, ndev);
1203err_hw:
1204 destroy_workqueue(priv->xfer_wq);
1205err_wq:
1206 unregister_netdev(ndev);
1207err_register:
1208 free_netdev(ndev);
1209 return err;
1210}
1211EXPORT_SYMBOL_GPL(w5100_probe);
1212
1213void w5100_remove(struct device *dev)
1214{
1215 struct net_device *ndev = dev_get_drvdata(dev);
1216 struct w5100_priv *priv = netdev_priv(ndev);
1217
1218 w5100_hw_reset(priv);
1219 free_irq(priv->irq, ndev);
1220 if (gpio_is_valid(priv->link_gpio))
1221 free_irq(priv->link_irq, ndev);
1222
1223 flush_work(&priv->setrx_work);
1224 flush_work(&priv->restart_work);
1225 destroy_workqueue(priv->xfer_wq);
1226
1227 unregister_netdev(ndev);
1228 free_netdev(ndev);
1229}
1230EXPORT_SYMBOL_GPL(w5100_remove);
1231
1232#ifdef CONFIG_PM_SLEEP
1233static int w5100_suspend(struct device *dev)
1234{
1235 struct net_device *ndev = dev_get_drvdata(dev);
1236 struct w5100_priv *priv = netdev_priv(ndev);
1237
1238 if (netif_running(ndev)) {
1239 netif_carrier_off(ndev);
1240 netif_device_detach(ndev);
1241
1242 w5100_hw_close(priv);
1243 }
1244 return 0;
1245}
1246
1247static int w5100_resume(struct device *dev)
1248{
1249 struct net_device *ndev = dev_get_drvdata(dev);
1250 struct w5100_priv *priv = netdev_priv(ndev);
1251
1252 if (netif_running(ndev)) {
1253 w5100_hw_reset(priv);
1254 w5100_hw_start(priv);
1255
1256 netif_device_attach(ndev);
1257 if (!gpio_is_valid(priv->link_gpio) ||
1258 gpio_get_value(priv->link_gpio) != 0)
1259 netif_carrier_on(ndev);
1260 }
1261 return 0;
1262}
1263#endif /* CONFIG_PM_SLEEP */
1264
1265SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
1266EXPORT_SYMBOL_GPL(w5100_pm_ops);
1267
1268static struct platform_driver w5100_mmio_driver = {
1269 .driver = {
1270 .name = DRV_NAME,
1271 .pm = &w5100_pm_ops,
1272 },
1273 .probe = w5100_mmio_probe,
1274 .remove_new = w5100_mmio_remove,
1275};
1276module_platform_driver(w5100_mmio_driver);